^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_crtc_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drmP.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <uapi/linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "rockchip_drm_drv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "rockchip_drm_vop.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "rockchip-mipi-csi-tx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DSI_PHY_TMR_LPCLK_CFG 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DSI_PHY_TMR_CFG 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DSI_PHY_RSTZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_DISFORCEPLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_ENFORCEPLL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_DISABLECLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_ENABLECLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_RSTZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_UNRSTZ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_SHUTDOWNZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_UNSHUTDOWNZ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DSI_PHY_TST_CTRL0 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_TESTCLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_UNTESTCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_TESTCLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_UNTESTCLR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DSI_PHY_TST_CTRL1 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_TESTEN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_UNTESTEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BYPASS_VCO_RANGE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VCO_IN_CAP_CON_LOW (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REF_BIAS_CUR_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CP_CURRENT_3MA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CP_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LPF_PROGRAM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LPF_RESISTORS_20_KOHM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LOW_PROGRAM_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HIGH_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLL_LOOP_DIV_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLL_INPUT_DIV_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define POWER_CONTROL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INTERNAL_REG_CURRENT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BIAS_BLOCK_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BANDGAP_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TER_RESISTOR_HIGH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TER_RESISTOR_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LEVEL_SHIFTERS_ON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TER_CAL_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SETRD_MAX (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define POWER_MANAGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TER_RESISTORS_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BIASEXTR_SEL(val) ((val) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BANDGAP_SEL(val) ((val) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TLP_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define THS_PRE_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define THS_ZERO_PROGRAM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FPGA_DSI_PHY_TST_READ 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FPGA_DSI_PHY_TST_CTRL0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* #define FPGA_PLATFORM_TEST 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dphy_pll_testdin_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int max_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 testdin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The table is based on 27MHz DPHY pll reference clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct dphy_pll_testdin_map dp_tdin_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) BANDGAP_97_07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) BANDGAP_98_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) BANDGAP_99_02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) BANDGAP_100_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) BANDGAP_93_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) BANDGAP_94_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BANDGAP_95_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BANDGAP_96_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) BIASEXTR_87_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BIASEXTR_91_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BIASEXTR_95_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BIASEXTR_100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BIASEXTR_105_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BIASEXTR_111_88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) BIASEXTR_118_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BIASEXTR_127_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const csi_tx_intr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "RX frame start interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "RX frame end interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "RX line end interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "TX frame start interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "TX frame end interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "TX line end interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "Line flag0 interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "Line flag1 interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "PHY stopstate interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "PHY PLL lock interrupt status!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "CSITX idle interrupt status!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const csi_tx_err_intr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "IDI header fifo overflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "IDI header fifo underflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "IDI payload fifo overflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "IDI payload fifo underflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "Header fifo overflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "Header fifo underflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "Payload fifo overflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "Payload fifo underflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "Output fifo overflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "Output fifo underflow raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "Txreadyhs error0 raw interrupt!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "Txreadyhs error1 raw interrupt!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) grf_field_write(struct rockchip_mipi_csi *csi, enum grf_reg_fields index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const u32 field = csi->pdata->csi0_grf_reg_fields[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 msb, lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!field || !csi->grf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg = (field >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) lsb = (field >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) msb = (field >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regmap_write(csi->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline void csi_writel(struct rockchip_mipi_csi *csi, u32 offset, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(v, csi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) csi->regsbak[offset >> 2] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline u32 csi_readl(struct rockchip_mipi_csi *csi, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return readl(csi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline void csi_mask_write(struct rockchip_mipi_csi *csi, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 mask, u32 val, bool regbak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 cached_val = csi->regsbak[offset >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) v = (cached_val & ~(mask)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (regbak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) csi_writel(csi, offset, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(v, csi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int phy_max_mbps_to_testdin(unsigned int max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 0; i < ARRAY_SIZE(dp_tdin_map); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (dp_tdin_map[i].max_mbps > max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return dp_tdin_map[i].testdin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline struct rockchip_mipi_csi *host_to_csi(struct mipi_dsi_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return container_of(host, struct rockchip_mipi_csi, dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline struct rockchip_mipi_csi *con_to_csi(struct drm_connector *con)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return container_of(con, struct rockchip_mipi_csi, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct rockchip_mipi_csi *encoder_to_csi(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return container_of(encoder, struct rockchip_mipi_csi, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void rockchip_mipi_csi_phy_write(struct rockchip_mipi_csi *csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 test_code, u8 test_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * is latched internally as the current test code. Test data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * programmed internally by rising edge on TESTCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(0x00ff0000 | test_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(0x02000200, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(0x00ff0000 | test_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static u8 __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rockchip_mipi_csi_phy_read(struct rockchip_mipi_csi *csi, u8 test_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(0x02ff0200 | test_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val = readl(csi->test_code_regs + FPGA_DSI_PHY_TST_READ) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(0x03000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void rockchip_bidir4l_board_phy_reset(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(0x04000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(0x08000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(0x80008000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(0x80000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel(0x40004000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void rockchip_bidir4l_board_phy_enable(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(0x08000800, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) writel(0x04000400, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void rockchip_mipi_csi_irq_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* enable csi err irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(m_ERR_INTR_EN | m_ERR_INTR_MASK, csi->regs + CSITX_ERR_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* disable csi frame end tx irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(m_FRM_END_TX | v_FRM_END_TX(0), csi->regs + CSITX_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void rockchip_mipi_csi_irq_disable(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* disable csi err irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(m_ERR_INTR_MASK, csi->regs + CSITX_ERR_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* disable csi tx irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writel(m_INTR_MASK, csi->regs + CSITX_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int rockchip_mipi_dphy_power_on(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (csi->dphy.phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) phy_power_on(csi->dphy.phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void rockchip_mipi_dphy_power_off(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (csi->dphy.phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) phy_power_off(csi->dphy.phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void rockchip_mipi_csi_tx_en(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* enable csi tx, dphy and config lane num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mask = m_CSITX_EN | m_DPHY_EN | m_LANE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val = v_CSITX_EN(1) | v_DPHY_EN(1) | v_LANE_NUM(csi->lanes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) csi_mask_write(csi, CSITX_ENABLE, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void rockchip_mipi_csi_host_power_on(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rockchip_mipi_csi_tx_en(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rockchip_mipi_csi_irq_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mask = m_CONFIG_DONE | m_CONFIG_DONE_IMD | m_CONFIG_DONE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = v_CONFIG_DONE(0) | v_CONFIG_DONE_IMD(1) | v_CONFIG_DONE_MODE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) csi_mask_write(csi, CSITX_CONFIG_DONE, mask, val, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void rockchip_mipi_csi_host_power_off(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rockchip_mipi_csi_irq_disable(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* disable csi tx, dphy and config lane num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mask = m_CSITX_EN | m_DPHY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val = v_CSITX_EN(0) | v_DPHY_EN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) csi_mask_write(csi, CSITX_ENABLE, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) csi_mask_write(csi, CSITX_CONFIG_DONE, m_CONFIG_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) v_CONFIG_DONE(1), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void rockchip_mipi_csi_phy_pll_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rockchip_mipi_csi_phy_write(csi, 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) INPUT_DIVIDER(csi->dphy.input_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rockchip_mipi_csi_phy_write(csi, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) LOOP_DIV_LOW_SEL(csi->dphy.feedback_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) LOW_PROGRAM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rockchip_mipi_csi_phy_write(csi, 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rockchip_mipi_csi_phy_write(csi, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) LOOP_DIV_HIGH_SEL(csi->dphy.feedback_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) HIGH_PROGRAM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rockchip_mipi_csi_phy_write(csi, 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) rockchip_mipi_csi_phy_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int testdin, vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) vco = (csi->lane_mbps < 200) ? 0 : (csi->lane_mbps + 100) / 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) testdin = phy_max_mbps_to_testdin(csi->lane_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (testdin < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(csi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "failed to get testdin for %dmbps lane clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) csi->lane_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return testdin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rockchip_mipi_csi_phy_write(csi, 0xb0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rockchip_mipi_csi_phy_write(csi, 0xb1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rockchip_mipi_csi_phy_write(csi, 0xb2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rockchip_mipi_csi_phy_write(csi, 0xb3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rockchip_mipi_csi_phy_write(csi, 0x10, BYPASS_VCO_RANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) VCO_RANGE_CON_SEL(vco) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) VCO_IN_CAP_CON_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) REF_BIAS_CUR_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rockchip_mipi_csi_phy_write(csi, 0x11, CP_CURRENT_3MA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) rockchip_mipi_csi_phy_write(csi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) LPF_RESISTORS_20_KOHM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rockchip_mipi_csi_phy_write(csi, 0x44, HSFREQRANGE_SEL(testdin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rockchip_mipi_csi_phy_pll_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rockchip_mipi_csi_phy_write(csi, 0x20, POWER_CONTROL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) INTERNAL_REG_CURRENT | BIAS_BLOCK_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BANDGAP_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) rockchip_mipi_csi_phy_write(csi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SETRD_MAX | TER_RESISTORS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rockchip_mipi_csi_phy_write(csi, 0x21, TER_RESISTOR_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) LEVEL_SHIFTERS_ON | SETRD_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) POWER_MANAGE | TER_RESISTORS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rockchip_mipi_csi_phy_write(csi, 0x22, LOW_PROGRAM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BIASEXTR_SEL(BIASEXTR_127_7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rockchip_mipi_csi_phy_write(csi, 0x22, HIGH_PROGRAM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) BANDGAP_SEL(BANDGAP_96_10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rockchip_mipi_csi_phy_write(csi, 0x70, TLP_PROGRAM_EN | 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rockchip_mipi_csi_phy_write(csi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rockchip_mipi_csi_phy_write(csi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * mipi_csi_pixel_format_to_bpp - obtain the number of bits per pixel for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * given pixel format defined by the MIPI CSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @fmt: MIPI CSI pixel format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Returns: The number of bits per pixel of the given pixel format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline int mipi_csi_pixel_format_to_bpp(int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case MIPI_CSI_FMT_RAW8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case MIPI_CSI_FMT_RAW10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_info("mipi csi unsupported format: %d\n", fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rockchip_mipi_csi_calc_bandwidth(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long mpclk, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long target_mbps = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct device_node *np = csi->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int max_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* optional override of the desired bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) max_mbps = csi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) bpp = mipi_csi_pixel_format_to_bpp(csi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (bpp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(csi->dev, "failed to get bpp for pixel format %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) csi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bpp = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) lanes = csi->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mpclk = DIV_ROUND_UP(csi->mode.clock, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (mpclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * vop raw 1 cycle pclk can process 4 pixel, so multiply 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tmp = mpclk * (bpp / lanes) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (tmp <= max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) target_mbps = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(csi->dev, "DPHY clock freq is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return target_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int rockchip_mipi_csi_get_lane_bps(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int i, pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned long pllref, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int m = 1, n = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long target_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) target_mbps = rockchip_mipi_csi_calc_bandwidth(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #ifdef FPGA_PLATFORM_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pllref = DIV_ROUND_UP(27000000, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pllref = DIV_ROUND_UP(clk_get_rate(csi->dphy.ref_clk), USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tmp = pllref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 1; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pre = pllref / i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tmp = target_mbps % pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) n = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) m = target_mbps / pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (tmp == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) csi->lane_mbps = pllref / n * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) csi->dphy.input_div = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) csi->dphy.feedback_div = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void rockchip_mipi_csi_set_hs_clk(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned long target_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned long bw, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) target_mbps = rockchip_mipi_csi_calc_bandwidth(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bw = target_mbps * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) rate = clk_round_rate(csi->dphy.hs_clk, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = clk_set_rate(csi->dphy.hs_clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(csi->dev, "failed to set hs clock rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) csi->lane_mbps = rate / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int rockchip_mipi_csi_host_attach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct rockchip_mipi_csi *csi = host_to_csi(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (device->lanes == 0 || device->lanes > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(csi->dev, "the number of data lanes(%u) is too many\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) device->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) csi->client = device->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) csi->lanes = device->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) csi->channel = device->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) csi->format = device->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) csi->mode_flags = device->mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int rockchip_mipi_csi_host_detach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct rockchip_mipi_csi *csi = host_to_csi(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) drm_panel_detach(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) csi->panel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct mipi_dsi_host_ops rockchip_mipi_csi_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .attach = rockchip_mipi_csi_host_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .detach = rockchip_mipi_csi_host_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void rockchip_mipi_csi_path_config(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 vop_wc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 data_type = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) switch (csi->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case MIPI_CSI_FMT_RAW8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) vop_wc = csi->mode.hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) data_type = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case MIPI_CSI_FMT_RAW10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) vop_wc = csi->mode.hdisplay * 5 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) data_type = 0x2b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) vop_wc = csi->mode.hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) data_type = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (csi->path_mode == VOP_PATH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* bypass select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mask = m_BYPASS_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) val = v_BYPASS_SELECT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) csi_mask_write(csi, CSITX_SYS_CTRL1, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* enable vop path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * todo: vc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mask = m_VOP_PATH_EN | m_VOP_WC_USERDEFINE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) m_VOP_WC_USERDEFINE | m_VOP_DT_USERDEFINE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) m_VOP_DT_USERDEFINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) val = v_VOP_PATH_EN(1) | v_VOP_WC_USERDEFINE_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) v_VOP_WC_USERDEFINE(vop_wc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v_VOP_DT_USERDEFINE_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) v_VOP_DT_USERDEFINE(data_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) csi_mask_write(csi, CSITX_VOP_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* disable bypass path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) mask = m_BYPASS_PATH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val = v_BYPASS_PATH_EN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) csi_mask_write(csi, CSITX_BYPASS_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mask = m_BYPASS_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val = v_BYPASS_SELECT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* bypass select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) csi_mask_write(csi, CSITX_SYS_CTRL1, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* disable vop path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * todo: dt, vc, wc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mask = m_VOP_PATH_EN | m_VOP_WC_USERDEFINE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) m_VOP_DT_USERDEFINE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val = v_VOP_PATH_EN(0) | v_VOP_WC_USERDEFINE_EN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) v_VOP_DT_USERDEFINE_EN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) csi_mask_write(csi, CSITX_VOP_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* enable bypass path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mask = m_BYPASS_PATH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val = v_BYPASS_PATH_EN(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) csi_mask_write(csi, CSITX_BYPASS_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* enable idi_48bit path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mask = m_IDI_48BIT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = v_IDI_48BIT_EN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) csi_mask_write(csi, CSITX_ENABLE, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void rockchip_mipi_csi_video_mode_config(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (csi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* enable non continue mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = v_NON_CONTINUES_MODE_EN(1) | v_CONT_MODE_CLK_SET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* disable non continue mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val = v_NON_CONTINUES_MODE_EN(0) | v_CONT_MODE_CLK_SET(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mask = m_NON_CONTINUES_MODE_EN | m_CONT_MODE_CLK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) csi_mask_write(csi, CSITX_SYS_CTRL3, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void rockchip_mipi_dphy_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 map[] = {0x1, 0x3, 0x7, 0xf};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Configures DPHY Selete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) grf_field_write(csi, DPHY_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Configures DPHY to work as a Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) grf_field_write(csi, MASTERSLAVEZ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Configures lane as TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) grf_field_write(csi, BASEDIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Set all REQUEST inputs to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) grf_field_write(csi, TURNREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) grf_field_write(csi, TURNDISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) grf_field_write(csi, FORCETXSTOPMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) grf_field_write(csi, FORCERXMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Enable Data Lane Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) grf_field_write(csi, ENABLE_N, map[csi->lanes - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Enable Clock Lane Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) grf_field_write(csi, ENABLECLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!csi->dphy.phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* reset dphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rockchip_bidir4l_board_phy_reset(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #ifdef FPGA_PLATFORM_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* init dphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rockchip_mipi_csi_phy_write(csi, 0xb0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rockchip_mipi_csi_phy_write(csi, 0x44, 0x0a);/* fpga:324Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) rockchip_mipi_csi_phy_write(csi, 0x19, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rockchip_mipi_csi_phy_write(csi, 0x17, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rockchip_mipi_csi_phy_write(csi, 0x18, 0xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) rockchip_mipi_csi_phy_write(csi, 0x18, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rockchip_mipi_csi_phy_write(csi, 0x10, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rockchip_mipi_csi_phy_write(csi, 0x11, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) rockchip_mipi_csi_phy_write(csi, 0x12, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rockchip_mipi_csi_phy_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* enable dphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) rockchip_bidir4l_board_phy_enable(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void rockchip_mipi_csi_fmt_config(struct rockchip_mipi_csi *csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mask = m_PIXEL_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val = v_PIXEL_FORMAT(csi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) csi_mask_write(csi, CSITX_VOP_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mask = m_CAM_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) val = v_CAM_FORMAT(csi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) csi_mask_write(csi, CSITX_BYPASS_PATH_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rockchip_mipi_csi_encoder_mode_set(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct rockchip_mipi_csi *csi = encoder_to_csi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) drm_mode_copy(&csi->mode, adjusted_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void rockchip_mipi_csi_post_disable(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) rockchip_mipi_csi_host_power_off(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rockchip_mipi_dphy_power_off(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pm_runtime_put(csi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) clk_disable_unprepare(csi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) clk_disable_unprepare(csi->dphy.hs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) clk_disable_unprepare(csi->dphy.ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static void rockchip_mipi_csi_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct rockchip_mipi_csi *csi = encoder_to_csi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) drm_panel_disable(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) drm_panel_unprepare(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rockchip_mipi_csi_post_disable(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rockchip_mipi_csi_encoder_mode_fixup(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void rockchip_mipi_csi_pre_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (csi->dphy.phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) rockchip_mipi_csi_set_hs_clk(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rockchip_mipi_csi_get_lane_bps(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_info(csi->dev, "final CSI-Link bandwidth: %u x %d Mbps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) csi->lane_mbps, csi->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void rockchip_mipi_csihost_enable_phy(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 map[] = {0x3, 0x7, 0xf, 0x1f};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mask = m_CSITX_ENABLE_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val = v_CSITX_ENABLE_PHY(map[csi->lanes - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) csi_mask_write(csi, CSITX_DPHY_CTRL, mask, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void rockchip_mipi_csi_host_init(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) rockchip_mipi_csi_fmt_config(csi, &csi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rockchip_mipi_csi_video_mode_config(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rockchip_mipi_csi_path_config(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) rockchip_mipi_csihost_enable_phy(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* timging config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int rockchip_mipi_csi_calibration(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned int val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) grf_field_write(csi, TXSKEWCALHS, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) udelay(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) grf_field_write(csi, TXSKEWCALHS, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = readl_poll_timeout(csi->regs + CSITX_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val, (val & m_DPHY_PLL_LOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 1000, PHY_STATUS_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(csi->dev, "PHY is not locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mask = PHY_STOPSTATELANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = readl_poll_timeout(csi->regs + CSITX_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) val, (val & mask) == mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 1000, PHY_STATUS_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(csi->dev, "lane module is not in stop state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int rockchip_mipi_csi_pre_enable(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) rockchip_mipi_csi_pre_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk_prepare_enable(csi->dphy.ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clk_prepare_enable(csi->dphy.hs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) clk_prepare_enable(csi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pm_runtime_get_sync(csi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* MIPI CSI TX software reset request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) for (i = 0; i < csi->pdata->rsts_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (csi->tx_rsts[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) reset_control_assert(csi->tx_rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) usleep_range(20, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) for (i = 0; i < csi->pdata->rsts_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (csi->tx_rsts[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) reset_control_deassert(csi->tx_rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!csi->regsbak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) csi->regsbak =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) devm_kzalloc(csi->dev, csi->regs_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!csi->regsbak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) memcpy(csi->regsbak, csi->regs, csi->regs_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rockchip_mipi_csi_host_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rockchip_mipi_dphy_init(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) rockchip_mipi_dphy_power_on(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rockchip_mipi_csi_calibration(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) rockchip_mipi_csi_host_power_on(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void rockchip_mipi_csi_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct rockchip_mipi_csi *csi = encoder_to_csi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) rockchip_mipi_csi_pre_enable(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) drm_panel_prepare(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) drm_panel_enable(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) rockchip_mipi_csi_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct rockchip_mipi_csi *csi = encoder_to_csi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct drm_connector *connector = conn_state->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct drm_display_info *info = &connector->display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (csi->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case MIPI_CSI_FMT_RAW8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) s->output_mode = ROCKCHIP_OUT_MODE_P888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case MIPI_CSI_FMT_RAW10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) s->output_mode = ROCKCHIP_OUT_MODE_P666;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) s->output_mode = ROCKCHIP_OUT_MODE_P888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) s->output_type = DRM_MODE_CONNECTOR_DSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (info->num_bus_formats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) s->bus_format = info->bus_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) s->tv_state = &conn_state->tv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) s->eotf = TRADITIONAL_GAMMA_SDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) s->color_space = V4L2_COLORSPACE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const struct drm_encoder_helper_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rockchip_mipi_csi_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .mode_fixup = rockchip_mipi_csi_encoder_mode_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .mode_set = rockchip_mipi_csi_encoder_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .enable = rockchip_mipi_csi_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .disable = rockchip_mipi_csi_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .atomic_check = rockchip_mipi_csi_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct drm_encoder_funcs rockchip_mipi_csi_encoder_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .destroy = drm_encoder_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) rockchip_mipi_csi_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return drm_panel_get_modes(csi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct drm_encoder *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rockchip_mipi_csi_connector_best_encoder(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return &csi->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) rockchip_mipi_loader_protect(struct drm_connector *connector, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (csi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) drm_panel_loader_protect(csi->panel, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pm_runtime_get_sync(csi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!csi->regsbak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) csi->regsbak = devm_kzalloc(csi->dev, csi->regs_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!csi->regsbak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) memcpy(csi->regsbak, csi->regs, csi->regs_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) pm_runtime_put(csi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) rockchip_mipi_csi_connector_atomic_flush(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) rockchip_mipi_csi_path_config(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mask = m_CONFIG_DONE | m_CONFIG_DONE_IMD | m_CONFIG_DONE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) val = v_CONFIG_DONE(0) | v_CONFIG_DONE_IMD(1) | v_CONFIG_DONE_MODE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) csi_mask_write(csi, CSITX_CONFIG_DONE, mask, val, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const struct drm_connector_helper_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) rockchip_mipi_csi_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .loader_protect = rockchip_mipi_loader_protect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .get_modes = rockchip_mipi_csi_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .best_encoder = rockchip_mipi_csi_connector_best_encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .atomic_flush = rockchip_mipi_csi_connector_atomic_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) rockchip_mipi_csi_detect(struct drm_connector *connector, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return connector_status_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) rockchip_mipi_csi_drm_connector_destroy(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) drm_connector_unregister(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) drm_connector_cleanup(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) rockchip_mipi_csi_connector_set_property(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct drm_connector_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct drm_property *property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) uint64_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (property == csi->csi_tx_path_property) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * csi->path_mode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * we get path mode from dts now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) DRM_ERROR("failed to set mipi csi tx cproperty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rockchip_mipi_csi_connector_get_property(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) const struct drm_connector_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct drm_property *property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) uint64_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct rockchip_mipi_csi *csi = con_to_csi(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (property == csi->csi_tx_path_property) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) *val = csi->path_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) DRM_ERROR("failed to get mipi csi tx cproperty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct drm_connector_funcs rockchip_mipi_csi_atomic_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .dpms = drm_atomic_helper_connector_dpms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .detect = rockchip_mipi_csi_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .destroy = rockchip_mipi_csi_drm_connector_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .atomic_set_property = rockchip_mipi_csi_connector_set_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .atomic_get_property = rockchip_mipi_csi_connector_get_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int rockchip_mipi_csi_property_create(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct drm_property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) prop = drm_property_create_range(csi->connector.dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "CSI-TX-PATH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) 0, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) csi->csi_tx_path_property = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) drm_object_attach_property(&csi->connector.base, prop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int rockchip_mipi_csi_register(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct drm_encoder *encoder = &csi->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct drm_connector *connector = &csi->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct device *dev = csi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * If we failed to find the CRTC(s) which this encoder is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * supposed to be connected to, it's because the CRTC has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * not been registered yet. Defer probing, and hope that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * the required CRTC is added later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (encoder->possible_crtcs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) drm_encoder_helper_add(&csi->encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) &rockchip_mipi_csi_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = drm_encoder_init(drm, &csi->encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) &rockchip_mipi_csi_encoder_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) DRM_MODE_ENCODER_DSI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_err(dev, "Failed to initialize encoder with drm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) csi->connector.port = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = drm_connector_init(drm, &csi->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) &rockchip_mipi_csi_atomic_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev_err(dev, "Failed to initialize connector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) goto encoder_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) drm_connector_helper_add(connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) &rockchip_mipi_csi_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) drm_mode_connector_attach_encoder(connector, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = drm_panel_attach(csi->panel, &csi->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev_err(dev, "Failed to attach panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) goto connector_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) connector_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) drm_connector_cleanup(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) encoder_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) drm_encoder_cleanup(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int rockchip_mipi_csi_bind(struct device *dev, struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct drm_device *drm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct rockchip_mipi_csi *csi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) csi->panel = of_drm_find_panel(csi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!csi->panel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) DRM_ERROR("failed to find panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = rockchip_mipi_csi_register(drm, csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_err(dev, "Failed to register mipi_csi: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) rockchip_mipi_csi_property_create(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static void rockchip_mipi_csi_unbind(struct device *dev, struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static const struct component_ops rockchip_mipi_csi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .bind = rockchip_mipi_csi_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .unbind = rockchip_mipi_csi_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static irqreturn_t rockchip_mipi_csi_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct rockchip_mipi_csi *csi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 int_status, err_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int_status = csi_readl(csi, CSITX_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) err_int_status = csi_readl(csi, CSITX_ERR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) for (i = 0; i < ARRAY_SIZE(csi_tx_intr); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (int_status & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) DRM_DEV_ERROR_RATELIMITED(csi->dev, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) csi_tx_intr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; i < ARRAY_SIZE(csi_tx_err_intr); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (err_int_status & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) DRM_DEV_ERROR_RATELIMITED(csi->dev, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) csi_tx_err_intr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) writel(int_status | m_INTR_MASK, csi->regs + CSITX_INTR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) writel(err_int_status | m_ERR_INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) csi->regs + CSITX_ERR_INTR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int rockchip_mipi_dphy_attach(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct device *dev = csi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) csi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (IS_ERR(csi->dphy.phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = PTR_ERR(csi->dphy.phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_err(dev, "failed to get mipi dphy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (csi->dphy.phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_dbg(dev, "Use Non-SNPS PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) csi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (IS_ERR(csi->dphy.hs_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_err(dev, "failed to get PHY high-speed clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return PTR_ERR(csi->dphy.hs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_dbg(dev, "Use SNPS PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) csi->dphy.ref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (IS_ERR(csi->dphy.ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_err(dev, "failed to get PHY reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return PTR_ERR(csi->dphy.ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int dw_mipi_csi_parse_dt(struct rockchip_mipi_csi *csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct device *dev = csi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct device_node *endpoint, *remote = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) remote = of_graph_get_remote_port_parent(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(dev, "no panel/bridge connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) of_node_put(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) csi->client = remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int rockchip_mipi_csi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct rockchip_mipi_csi *csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int ret, val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) csi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) csi->pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) platform_set_drvdata(pdev, csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = dw_mipi_csi_parse_dt(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_err(dev, "failed to parse DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csi_regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) csi->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (IS_ERR(csi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return PTR_ERR(csi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) csi->regs_len = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) csi->regsbak = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) IORESOURCE_MEM, "test_code_regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) csi->test_code_regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (IS_ERR(csi->test_code_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(dev, "Unable to get test_code_regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) csi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (csi->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_err(dev, "Failed to ger csi tx irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) csi->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (IS_ERR(csi->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = PTR_ERR(csi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_err(dev, "Unable to get pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) csi->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (IS_ERR(csi->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_err(dev, "Unable to get rockchip,grf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) csi->grf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) for (i = 0; i < csi->pdata->rsts_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct reset_control *rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) devm_reset_control_get(dev, csi->pdata->rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_err(dev, "failed to get %s\n", csi->pdata->rsts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) csi->tx_rsts[i] = rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = rockchip_mipi_dphy_attach(csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret = devm_request_irq(dev, csi->irq, rockchip_mipi_csi_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) IRQF_SHARED, dev_name(dev), csi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_err(dev, "failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) csi->dsi_host.ops = &rockchip_mipi_csi_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) csi->dsi_host.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = mipi_dsi_host_register(&csi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = component_add(dev, &rockchip_mipi_csi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) mipi_dsi_host_unregister(&csi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!of_property_read_u32(np, "csi-tx-bypass-mode", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) csi->path_mode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int rockchip_mipi_csi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct rockchip_mipi_csi *csi = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) mipi_dsi_host_unregister(&csi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) component_del(&pdev->dev, &rockchip_mipi_csi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static const u32 rk1808_csi_grf_reg_fields[MAX_FIELDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) [DPHY_SEL] = GRF_REG_FIELD(0x0440, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) [TXSKEWCALHS] = GRF_REG_FIELD(0x0444, 11, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static const char * const rk1808_csi_tx_rsts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) "tx_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "tx_bytehs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) "tx_esc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) "tx_cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "tx_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const struct rockchip_mipi_csi_plat_data rk1808_socdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .csi0_grf_reg_fields = rk1808_csi_grf_reg_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .max_bit_rate_per_lane = 2000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .soc_type = RK1808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .rsts = rk1808_csi_tx_rsts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .rsts_num = ARRAY_SIZE(rk1808_csi_tx_rsts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const struct of_device_id rockchip_mipi_csi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { .compatible = "rockchip,rk1808-mipi-csi", .data = &rk1808_socdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) MODULE_DEVICE_TABLE(of, rockchip_mipi_csi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct platform_driver rockchip_mipi_csi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .probe = rockchip_mipi_csi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .remove = rockchip_mipi_csi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .of_match_table = rockchip_mipi_csi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) module_platform_driver(rockchip_mipi_csi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) MODULE_DESCRIPTION("ROCKCHIP MIPI CSI TX controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) MODULE_AUTHOR("Sandy huang <hjc@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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