^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chris Zhong <zyw@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Nickey Yang <nickey.yang@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_dsc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <uapi/linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/bridge/dw_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "rockchip_drm_drv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "rockchip_drm_vop.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DSI_PHY_RSTZ 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_DISFORCEPLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_ENFORCEPLL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_DISABLECLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_ENABLECLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHY_RSTZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_UNRSTZ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_SHUTDOWNZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_UNSHUTDOWNZ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DSI_PHY_IF_CFG 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSI_PHY_STATUS 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STOP_STATE_CLK_LANE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DSI_PHY_TST_CTRL0 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_TESTCLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_UNTESTCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_TESTCLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_UNTESTCLR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DSI_PHY_TST_CTRL1 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PHY_TESTEN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_UNTESTEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DSI_INT_ST0 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DSI_INT_ST1 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DSI_INT_MSK0 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DSI_INT_MSK1 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_STATUS_TIMEOUT_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMD_PKT_STATUS_TIMEOUT_US 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BYPASS_VCO_RANGE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VCO_IN_CAP_CON_LOW (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REF_BIAS_CUR_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CP_CURRENT_3UA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CP_CURRENT_4_5UA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CP_CURRENT_7_5UA 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CP_CURRENT_6UA 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CP_CURRENT_12UA 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CP_CURRENT_SEL(val) ((val) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CP_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LPF_RESISTORS_15_5KOHM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LPF_RESISTORS_13KOHM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LPF_RESISTORS_11_5KOHM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LPF_RESISTORS_10_5KOHM 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LPF_RESISTORS_8KOHM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LPF_PROGRAM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LOW_PROGRAM_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HIGH_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLL_LOOP_DIV_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLL_INPUT_DIV_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define POWER_CONTROL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INTERNAL_REG_CURRENT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BIAS_BLOCK_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BANDGAP_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TER_RESISTOR_HIGH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TER_RESISTOR_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LEVEL_SHIFTERS_ON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TER_CAL_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SETRD_MAX (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define POWER_MANAGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TER_RESISTORS_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BIASEXTR_SEL(val) ((val) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BANDGAP_SEL(val) ((val) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TLP_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define THS_PRE_PROGRAM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define THS_ZERO_PROGRAM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PLL_LPF_AND_CP_CONTROL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PLL_INPUT_DIVIDER_RATIO 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PLL_LOOP_DIVIDER_RATIO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BANDGAP_AND_BIAS_CONTROL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TERMINATION_RESISTER_CONTROL 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HS_RX_CONTROL_OF_LANE_0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DW_MIPI_NEEDS_HCLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PX30_GRF_PD_VO_CON1 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PX30_DSI_FORCERXMODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PX30_DSI_TURNDISABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PX30_DSI_LCDC_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RK3128_GRF_LVDS_CON0 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RK3128_DSI_FORCETXSTOPMODE (0xf << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RK3128_DSI_FORCERXMODE (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RK3128_DSI_TURNDISABLE (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RK3288_GRF_SOC_CON6 0x025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RK3288_DSI0_LCDC_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RK3288_DSI1_LCDC_SEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RK3399_GRF_SOC_CON20 0x6250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RK3399_DSI0_LCDC_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RK3399_DSI1_LCDC_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RK3399_GRF_SOC_CON22 0x6258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RK3399_DSI0_TURNREQUEST (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RK3399_DSI0_TURNDISABLE (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RK3399_DSI0_FORCERXMODE (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RK3399_GRF_SOC_CON23 0x625c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RK3399_DSI1_TURNDISABLE (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RK3399_DSI1_FORCERXMODE (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RK3399_DSI1_ENABLE (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RK3399_GRF_SOC_CON24 0x6260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RK3399_TXRX_ENABLECLK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RK3399_TXRX_BASEDIR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RK3568_GRF_VO_CON2 0x0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RK3568_GRF_VO_CON3 0x036c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RK3568_DSI_FORCETXSTOPMODE (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RK3568_DSI_TURNDISABLE (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RK3568_DSI_FORCERXMODE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RV1126_GRF_DSIPHY_CON 0x10220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RV1126_DSI_FORCETXSTOPMODE (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RV1126_DSI_TURNDISABLE (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RV1126_DSI_FORCERXMODE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BANDGAP_97_07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) BANDGAP_98_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BANDGAP_99_02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BANDGAP_100_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BANDGAP_93_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BANDGAP_94_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BANDGAP_95_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) BANDGAP_96_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BIASEXTR_87_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) BIASEXTR_91_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) BIASEXTR_95_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) BIASEXTR_100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BIASEXTR_105_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BIASEXTR_111_88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BIASEXTR_118_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BIASEXTR_127_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum soc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PX30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) RK3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) RV1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct cmd_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct rockchip_dw_dsi_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 lcdsel_grf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 lcdsel_big;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 lcdsel_lit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 enable_grf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 lanecfg1_grf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 lanecfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 lanecfg2_grf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 lanecfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum soc_type soc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int max_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long max_bit_rate_per_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct dw_mipi_dsi_rockchip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct drm_encoder encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bool c_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bool scrambling_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int slice_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int slice_per_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool block_pred_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bool dsc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct drm_dsc_picture_parameter_set *pps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct regmap *grf_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk *pllref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct clk *grf_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct clk *phy_cfg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* dual-channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool is_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct dw_mipi_dsi_rockchip *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* optional external dphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool phy_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) union phy_configure_opts phy_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int lane_mbps; /* per lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 input_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 feedback_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct dw_mipi_dsi *dmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const struct rockchip_dw_dsi_chip_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct dw_mipi_dsi_plat_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int devcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct rockchip_drm_sub_dev sub_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct dphy_pll_parameter_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int max_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 hsfreqrange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 icpctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 lpfctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* The table is based on 27MHz DPHY pll reference clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct dphy_pll_parameter_map dppa_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int max_mbps_to_parameter(unsigned int max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (dppa_map[i].max_mbps >= max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(val, dsi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return readl(dsi->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 test_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 test_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * is latched internally as the current test code. Test data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * programmed internally by rising edge on TESTCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PHY_TESTDIN(test_code));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PHY_TESTDIN(test_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * ns2bc - Nanoseconds to byte clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * ns2ui - Nanoseconds to UI time periods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void dw_mipi_dsi_phy_tx_config(struct dw_mipi_dsi_rockchip *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (dsi->cdata->lanecfg1_grf_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dsi->cdata->lanecfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (dsi->cdata->lanecfg2_grf_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dsi->cdata->lanecfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (dsi->cdata->enable_grf_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dsi->cdata->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int dw_mipi_dsi_phy_init(void *priv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i, vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dw_mipi_dsi_phy_tx_config(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (dsi->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Get vco from frequency(lane_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * vco frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * 000 - between 80 and 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * 001 - between 200 and 300 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * 010 - between 300 and 500 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * 011 - between 500 and 700 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * 100 - between 700 and 900 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * 101 - between 900 and 1100 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * 110 - between 1100 and 1300 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * 111 - between 1300 and 1500 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i = max_mbps_to_parameter(dsi->lane_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "failed to get parameter for %dmbps clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dsi->lane_mbps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) BYPASS_VCO_RANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) VCO_RANGE_CON_SEL(vco) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) VCO_IN_CAP_CON_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) REF_BIAS_CUR_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CP_CURRENT_SEL(dppa_map[i].icpctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CP_PROGRAM_EN | LPF_PROGRAM_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) INPUT_DIVIDER(dsi->input_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) LOOP_DIV_LOW_SEL(dsi->feedback_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) LOW_PROGRAM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * to make the configured LSB effective according to IP simulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * and lab test results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Only in this way can we get correct mipi phy pll frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) HIGH_PROGRAM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) POWER_CONTROL | INTERNAL_REG_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BIAS_BLOCK_ON | BANDGAP_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) TER_RESISTOR_LOW | TER_CAL_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SETRD_MAX | TER_RESISTORS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SETRD_MAX | POWER_MANAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TER_RESISTORS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) TLP_PROGRAM_EN | ns2bc(dsi, 60));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) BIT(5) | ns2bc(dsi, 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) BIT(5) | (ns2bc(dsi, 60) + 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) TLP_PROGRAM_EN | ns2bc(dsi, 60));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BIT(5) | ns2bc(dsi, 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void dw_mipi_dsi_phy_power_on(void *priv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (dsi->phy_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) phy_power_on(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dsi->phy_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void dw_mipi_dsi_phy_power_off(void *priv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!dsi->phy_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) phy_power_off(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dsi->phy_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long mode_flags, u32 lanes, u32 format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int *lane_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned long mpclk, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int target_mbps = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int max_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned long best_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned long fvco_min, fvco_max, fin, fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int min_prediv, max_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int _prediv, best_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned long _fbdiv, best_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned long min_delta = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long target_pclk, hs_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dsi->format = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (bpp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "failed to get bpp for pixel format %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* optional override of the desired bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) target_mbps = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (mpclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tmp = mpclk * (bpp / lanes) * 10 / 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (tmp < max_mbps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) target_mbps = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "DPHY clock frequency is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) target_mbps = max_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* for external phy only a the mipi_dphy_config is necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (dsi->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) target_pclk = DIV_ROUND_CLOSEST_ULL(target_mbps * lanes, bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) phy_mipi_dphy_get_default_config(target_pclk * USEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bpp, lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) &dsi->phy_opts.mipi_dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "failed to set phy mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) phy_configure(dsi->phy, &dsi->phy_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) hs_clk_rate = dsi->phy_opts.mipi_dphy.hs_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dsi->lane_mbps = DIV_ROUND_UP(hs_clk_rate, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *lane_mbps = dsi->lane_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fin = clk_get_rate(dsi->pllref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fout = target_mbps * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* constraint: 5Mhz <= Fref / N <= 40MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) max_prediv = fin / (5 * USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* constraint: 80MHz <= Fvco <= 1500Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fvco_min = 80 * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fvco_max = 1500 * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Fvco = Fref * M / N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) tmp = (u64)fout * _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) do_div(tmp, fin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) _fbdiv = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Due to the use of a "by 2 pre-scaler," the range of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * feedback multiplication value M is limited to even division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * numbers, and m must be greater than 6, not bigger than 512.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (_fbdiv < 6 || _fbdiv > 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) _fbdiv += _fbdiv % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) tmp = (u64)_fbdiv * fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) do_div(tmp, _prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (tmp < fvco_min || tmp > fvco_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) delta = abs(fout - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (delta < min_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) best_prediv = _prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) best_fbdiv = _fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) best_freq = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (best_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *lane_mbps = dsi->lane_mbps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dsi->input_div = best_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dsi->feedback_div = best_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct hstt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int maxfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct dw_mipi_dsi_dphy_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct dw_mipi_dsi_dphy_timing dphy_hstt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .clk_lp2hs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .clk_hs2lp = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .data_lp2hs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .data_hs2lp = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct dw_mipi_dsi_dphy_timing *timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *timing = dphy_hstt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .init = dw_mipi_dsi_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .power_on = dw_mipi_dsi_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .power_off = dw_mipi_dsi_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .get_timing = dw_mipi_dsi_phy_get_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void dw_mipi_dsi_rockchip_vop_routing(struct dw_mipi_dsi_rockchip *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &dsi->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (mux < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (dsi->cdata->lcdsel_grf_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (dsi->slave && dsi->slave->cdata->lcdsel_grf_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) regmap_write(dsi->slave->grf_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dsi->slave->cdata->lcdsel_grf_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mux ? dsi->slave->cdata->lcdsel_lit :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dsi->slave->cdata->lcdsel_big);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct drm_connector *connector = conn_state->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct drm_display_info *info = &connector->display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) switch (dsi->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) s->output_mode = ROCKCHIP_OUT_MODE_P888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) s->output_mode = ROCKCHIP_OUT_MODE_P666;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) s->output_mode = ROCKCHIP_OUT_MODE_P565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (info->num_bus_formats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) s->bus_format = info->bus_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* rk356x series drive mipi pixdata on posedge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (dsi->cdata->soc_type == RK3568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) s->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) s->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) s->output_type = DRM_MODE_CONNECTOR_DSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) s->color_space = V4L2_COLORSPACE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) s->output_if = dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) s->output_if |= VOP_OUTPUT_IF_MIPI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* dual link dsi for rk3399 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (dsi->id && dsi->cdata->soc_type == RK3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (dsi->dsc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) s->dsc_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) s->dsc_sink_cap.version_major = dsi->version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) s->dsc_sink_cap.version_minor = dsi->version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) s->dsc_sink_cap.slice_width = dsi->slice_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) s->dsc_sink_cap.slice_height = dsi->slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* only can support rgb888 panel now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) s->dsc_sink_cap.block_pred = dsi->block_pred_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) s->dsc_sink_cap.native_420 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) memcpy(&s->pps, dsi->pps, sizeof(struct drm_dsc_picture_parameter_set));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dw_mipi_dsi_rockchip_vop_routing(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static void dw_mipi_dsi_rockchip_loader_protect(struct dw_mipi_dsi_rockchip *dsi, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pm_runtime_get_sync(dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) phy_init(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dsi->phy_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (dsi->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dsi->phy->power_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pm_runtime_put(dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) phy_exit(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dsi->phy_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (dsi->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dsi->phy->power_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dw_mipi_dsi_rockchip_loader_protect(dsi->slave, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int dw_mipi_dsi_rockchip_encoder_loader_protect(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (dsi->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) panel_simple_loader_protect(dsi->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dw_mipi_dsi_rockchip_loader_protect(dsi, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const struct drm_encoder_helper_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dw_mipi_dsi_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .atomic_check = dw_mipi_dsi_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .enable = dw_mipi_dsi_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .disable = dw_mipi_dsi_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct drm_device *drm_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct drm_encoder *encoder = &dsi->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dsi->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) DRM_ERROR("Failed to initialize encoder with drm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static struct device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct device_node *node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct dw_mipi_dsi_rockchip *dsi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) node = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pdev = of_find_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dsi2 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!dsi2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static int dw_mipi_dsi_get_dsc_info_from_sink(struct dw_mipi_dsi_rockchip *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct drm_dsc_picture_parameter_set *pps = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct cmd_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) char *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint8_t *dsc_packed_pps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!panel && !bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) np = panel->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) np = bridge->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dsi->c_option = of_property_read_bool(np, "phy-c-option");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dsi->scrambling_en = of_property_read_bool(np, "scrambling-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dsi->dsc_enable = of_property_read_bool(np, "compressed-data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dsi->block_pred_enable = of_property_read_bool(np, "blk-pred-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) of_property_read_u32(np, "slice-width", &dsi->slice_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) of_property_read_u32(np, "slice-height", &dsi->slice_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) of_property_read_u32(np, "slice-per-pkt", &dsi->slice_per_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) of_property_read_u8(np, "version-major", &dsi->version_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) of_property_read_u8(np, "version-minor", &dsi->version_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) data = of_get_property(np, "panel-init-sequence", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) d = devm_kmemdup(dsi->dev, data, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) while (len > sizeof(*header)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) header = (struct cmd_header *)d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) d += sizeof(*header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) len -= sizeof(*header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (header->payload_length > len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dsc_packed_pps = devm_kmemdup(dsi->dev, d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) header->payload_length, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!dsc_packed_pps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) d += header->payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) len -= header->payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dsi->pps = pps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int dw_mipi_dsi_rockchip_bind(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct drm_device *drm_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct device *second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) second = dw_mipi_dsi_rockchip_find_second(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (IS_ERR(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return PTR_ERR(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (second) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* we are the slave in dual-DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dsi->slave = dev_get_drvdata(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) DRM_DEV_ERROR(dev, "could not get slaves data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dsi->slave->is_slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) put_device(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (dsi->is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = clk_prepare_enable(dsi->pllref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) &dsi->panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_err(dsi->dev, "failed to find panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dsi->sub_dev.connector = dw_mipi_dsi_get_connector(dsi->dmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (dsi->sub_dev.connector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dsi->sub_dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dsi->sub_dev.loader_protect = dw_mipi_dsi_rockchip_encoder_loader_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rockchip_drm_register_sub_dev(&dsi->sub_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (dsi->is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (dsi->sub_dev.connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) rockchip_drm_unregister_sub_dev(&dsi->sub_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dw_mipi_dsi_unbind(dsi->dmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) clk_disable_unprepare(dsi->pllref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const struct component_ops dw_mipi_dsi_rockchip_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .bind = dw_mipi_dsi_rockchip_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .unbind = dw_mipi_dsi_rockchip_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct device *second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) second = dw_mipi_dsi_rockchip_find_second(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (IS_ERR(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return PTR_ERR(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (second) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) DRM_DEV_ERROR(second,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "Failed to register component: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct dw_mipi_dsi_rockchip *dsi = priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct device *second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) second = dw_mipi_dsi_rockchip_find_second(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (second && !IS_ERR(second))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) component_del(second, &dw_mipi_dsi_rockchip_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .attach = dw_mipi_dsi_rockchip_host_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .detach = dw_mipi_dsi_rockchip_host_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct dw_mipi_dsi_rockchip *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) const struct rockchip_dw_dsi_chip_data *cdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (!dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dsi->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (IS_ERR(dsi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return PTR_ERR(dsi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) while (cdata[i].reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (cdata[i].reg == res->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dsi->cdata = &cdata[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dsi->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!dsi->cdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* try to get a possible external dphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dsi->phy = devm_phy_optional_get(dev, "dphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (IS_ERR(dsi->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = PTR_ERR(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dsi->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (IS_ERR(dsi->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = PTR_ERR(dsi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(dev, "Unable to get pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dsi->pllref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (IS_ERR(dsi->pllref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (dsi->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * if external phy is present, pll will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * generated there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dsi->pllref_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = PTR_ERR(dsi->pllref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) DRM_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "Unable to get pll reference clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (IS_ERR(dsi->phy_cfg_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ret = PTR_ERR(dsi->phy_cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) DRM_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) "Unable to get phy_cfg_clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dsi->grf_clk = devm_clk_get(dev, "grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (IS_ERR(dsi->grf_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ret = PTR_ERR(dsi->grf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (dsi->cdata->flags & DW_MIPI_NEEDS_HCLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dsi->hclk = devm_clk_get(dev, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (IS_ERR(dsi->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = PTR_ERR(dsi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) DRM_DEV_ERROR(dev, "Unable to get hclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (IS_ERR(dsi->grf_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return PTR_ERR(dsi->grf_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dsi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dsi->pdata.base = dsi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dsi->pdata.priv_data = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) platform_set_drvdata(pdev, dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (IS_ERR(dsi->dmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = PTR_ERR(dsi->dmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) DRM_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) "Failed to probe dw_mipi_dsi: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto err_clkdisable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) err_clkdisable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) clk_disable_unprepare(dsi->pllref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (dsi->devcnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dw_mipi_dsi_remove(dsi->dmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static __maybe_unused int dw_mipi_dsi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) clk_disable_unprepare(dsi->grf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) clk_disable_unprepare(dsi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) clk_disable_unprepare(dsi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) clk_disable_unprepare(dsi->phy_cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static __maybe_unused int dw_mipi_dsi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) clk_prepare_enable(dsi->phy_cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) clk_prepare_enable(dsi->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) clk_prepare_enable(dsi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) clk_prepare_enable(dsi->grf_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) SET_RUNTIME_PM_OPS(dw_mipi_dsi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dw_mipi_dsi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .reg = 0xff450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PX30_DSI_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PX30_DSI_FORCERXMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PX30_DSI_FORCETXSTOPMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .max_bit_rate_per_lane = 1000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .soc_type = PX30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .reg = 0x10110000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) RK3128_DSI_FORCETXSTOPMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) RK3128_DSI_FORCERXMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .flags = DW_MIPI_NEEDS_HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .max_bit_rate_per_lane = 1000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .soc_type = RK3128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .reg = 0xff960000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .max_bit_rate_per_lane = 1500000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .soc_type = RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .reg = 0xff964000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .max_bit_rate_per_lane = 1500000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .soc_type = RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .reg = 0xff960000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) RK3399_DSI0_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) RK3399_DSI0_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RK3399_DSI0_FORCETXSTOPMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) RK3399_DSI0_FORCERXMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .max_bit_rate_per_lane = 1500000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .soc_type = RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .reg = 0xff968000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) RK3399_DSI1_LCDC_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) RK3399_DSI1_FORCETXSTOPMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) RK3399_DSI1_FORCERXMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) RK3399_DSI1_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) RK3399_TXRX_ENABLECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) RK3399_TXRX_MASTERSLAVEZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) RK3399_TXRX_ENABLECLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) RK3399_TXRX_BASEDIR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .enable_grf_reg = RK3399_GRF_SOC_CON23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .max_bit_rate_per_lane = 1500000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .soc_type = RK3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .reg = 0xfe060000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RK3568_DSI_FORCERXMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) RK3568_DSI_FORCETXSTOPMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .flags = DW_MIPI_NEEDS_HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .max_bit_rate_per_lane = 1200000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .soc_type = RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .reg = 0xfe070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) RK3568_DSI_FORCERXMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) RK3568_DSI_FORCETXSTOPMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .flags = DW_MIPI_NEEDS_HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .max_bit_rate_per_lane = 1200000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .soc_type = RK3568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .reg = 0xffb30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) RV1126_DSI_FORCERXMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) RV1126_DSI_FORCETXSTOPMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .flags = DW_MIPI_NEEDS_HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .max_data_lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .max_bit_rate_per_lane = 1000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .soc_type = RV1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .compatible = "rockchip,px30-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .data = &px30_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .compatible = "rockchip,rk3128-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .data = &rk3128_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .compatible = "rockchip,rk3288-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .data = &rk3288_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .compatible = "rockchip,rk3399-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .data = &rk3399_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .compatible = "rockchip,rk3568-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .data = &rk3568_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .compatible = "rockchip,rv1126-mipi-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .data = &rv1126_chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct platform_driver dw_mipi_dsi_rockchip_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .probe = dw_mipi_dsi_rockchip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .remove = dw_mipi_dsi_rockchip_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .pm = &dw_mipi_dsi_rockchip_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .name = "dw-mipi-dsi-rockchip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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