^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chris Zhong <zyw@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _CDN_DP_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _CDN_DP_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ADDR_IMEM 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ADDR_DMEM 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* APB CFG addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define APB_CTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XT_INT_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAILBOX_FULL_ADDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAILBOX_EMPTY_ADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAILBOX0_WR_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAILBOX0_RD_DATA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define KEEP_ALIVE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VER_L 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VER_H 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VER_LIB_L_ADDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VER_LIB_H_ADDR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SW_DEBUG_L 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SW_DEBUG_H 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAILBOX_INT_MASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAILBOX_INT_STATUS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SW_CLK_L 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SW_CLK_H 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SW_EVENTS0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SW_EVENTS1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SW_EVENTS2 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SW_EVENTS3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XT_OCD_CTRL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define APB_INT_MASK 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define APB_STATUS_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* audio decoder addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AUDIO_SRC_CNTL 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AUDIO_SRC_CNFG 0x30004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define COM_CH_STTS_BITS 0x30008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STTS_BIT_CH(x) (0x3000c + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIF_CTRL_ADDR 0x3004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPDIF_CH1_CS_3100_ADDR 0x30050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPDIF_CH1_CS_6332_ADDR 0x30054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPDIF_CH1_CS_9564_ADDR 0x30058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPDIF_CH1_CS_12796_ADDR 0x3005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPDIF_CH1_CS_159128_ADDR 0x30060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPDIF_CH1_CS_191160_ADDR 0x30064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIF_CH2_CS_3100_ADDR 0x30068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPDIF_CH2_CS_6332_ADDR 0x3006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPDIF_CH2_CS_9564_ADDR 0x30070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIF_CH2_CS_12796_ADDR 0x30074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIF_CH2_CS_159128_ADDR 0x30078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIF_CH2_CS_191160_ADDR 0x3007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SMPL2PKT_CNTL 0x30080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SMPL2PKT_CNFG 0x30084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FIFO_CNTL 0x30088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FIFO_STTS 0x3008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* source pif addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SOURCE_PIF_WR_ADDR 0x30800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SOURCE_PIF_WR_REQ 0x30804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOURCE_PIF_RD_ADDR 0x30808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SOURCE_PIF_RD_REQ 0x3080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SOURCE_PIF_DATA_WR 0x30810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SOURCE_PIF_DATA_RD 0x30814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SOURCE_PIF_FIFO1_FLUSH 0x30818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SOURCE_PIF_FIFO2_FLUSH 0x3081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SOURCE_PIF_STATUS 0x30820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SOURCE_PIF_INTERRUPT_MASK 0x30828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOURCE_PIF_SW_RESET 0x30834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* bellow registers need access by mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* source car addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SOURCE_HDTX_CAR 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOURCE_DPTX_CAR 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SOURCE_PHY_CAR 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SOURCE_CEC_CAR 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SOURCE_CBUS_CAR 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOURCE_PKT_CAR 0x0918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOURCE_AIF_CAR 0x091c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SOURCE_CIPHER_CAR 0x0920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SOURCE_CRYPTO_CAR 0x0924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* clock meters addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CM_CTRL 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CM_I2S_CTRL 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CM_SPDIF_CTRL 0x0a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CM_VID_CTRL 0x0a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CM_LANE_CTRL 0x0a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2S_NM_STABLE 0x0a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define I2S_NCTS_STABLE 0x0a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPDIF_NM_STABLE 0x0a1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPDIF_NCTS_STABLE 0x0a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NMVID_MEAS_STABLE 0x0a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2S_MEAS 0x0a40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPDIF_MEAS 0x0a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NMVID_MEAS 0x0ac0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* source vif addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BND_HSYNC2VSYNC 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HSYNC2VSYNC_F1_L1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HSYNC2VSYNC_F2_L1 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HSYNC2VSYNC_STATUS 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HSYNC2VSYNC_POL_CTRL 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* dptx phy addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DP_TX_PHY_CONFIG_REG 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DP_TX_PHY_SW_RESET 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DP_TX_PHY_SCRAMBLER_SEED 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DP_TX_PHY_TRAINING_01_04 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DP_TX_PHY_TRAINING_05_08 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DP_TX_PHY_TRAINING_09_10 0x2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEST_COR 0x23fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* dptx hpd addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HPD_IRQ_DET_MIN_TIMER 0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HPD_IRQ_DET_MAX_TIMER 0x2104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HPD_UNPLGED_DET_MIN_TIMER 0x2108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HPD_STABLE_TIMER 0x210c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HPD_FILTER_TIMER 0x2110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HPD_EVENT_MASK 0x211c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HPD_EVENT_DET 0x2120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* dpyx framer addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DP_FRAMER_GLOBAL_CONFIG 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DP_SW_RESET 0x2204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DP_FRAMER_TU 0x2208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DP_FRAMER_PXL_REPR 0x220c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DP_FRAMER_SP 0x2210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AUDIO_PACK_CONTROL 0x2214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DP_VB_ID 0x2258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DP_MTPH_LVP_CONTROL 0x225c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DP_MTPH_SYMBOL_VALUES 0x2260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DP_MTPH_ECF_CONTROL 0x2264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DP_MTPH_ACT_CONTROL 0x2268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DP_MTPH_STATUS 0x226c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DP_INTERRUPT_SOURCE 0x2270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DP_INTERRUPT_MASK 0x2274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DP_FRONT_BACK_PORCH 0x2278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DP_BYTE_COUNT 0x227c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* dptx stream addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MSA_HORIZONTAL_0 0x2280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MSA_HORIZONTAL_1 0x2284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MSA_VERTICAL_0 0x2288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MSA_VERTICAL_1 0x228c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MSA_MISC 0x2290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STREAM_CONFIG 0x2294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AUDIO_PACK_STATUS 0x2298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIF_STATUS 0x229c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCK_STUFF_STATUS_0 0x22a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCK_STUFF_STATUS_1 0x22a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define INFO_PACK_STATUS 0x22a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RATE_GOVERNOR_STATUS 0x22ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DP_HORIZONTAL 0x22b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DP_VERTICAL_0 0x22b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DP_VERTICAL_1 0x22b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DP_BLOCK_SDP 0x22bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* dptx glbl addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DPTX_LANE_EN 0x2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DPTX_ENHNCD 0x2304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DPTX_INT_MASK 0x2308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DPTX_INT_STATUS 0x230c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* dp aux addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DP_AUX_HOST_CONTROL 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DP_AUX_INTERRUPT_SOURCE 0x2804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DP_AUX_INTERRUPT_MASK 0x2808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DP_AUX_SEND_NACK_TRANSACTION 0x2810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DP_AUX_CLEAR_RX 0x2814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DP_AUX_CLEAR_TX 0x2818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DP_AUX_TIMER_STOP 0x281c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DP_AUX_TIMER_CLEAR 0x2820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DP_AUX_RESET_SW 0x2824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DP_AUX_DIVIDE_2M 0x2828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DP_AUX_FREQUENCY_1M_MAX 0x2830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DP_AUX_FREQUENCY_1M_MIN 0x2834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DP_AUX_RX_PRE_MIN 0x2838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DP_AUX_RX_PRE_MAX 0x283c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DP_AUX_TIMER_PRESET 0x2840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DP_AUX_NACK_FORMAT 0x2844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DP_AUX_TX_DATA 0x2848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DP_AUX_RX_DATA 0x284c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DP_AUX_TX_STATUS 0x2850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DP_AUX_RX_STATUS 0x2854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DP_AUX_RX_CYCLE_COUNTER 0x2858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DP_AUX_MAIN_STATES 0x285c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DP_AUX_MAIN_TIMER 0x2860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DP_AUX_AFE_OUT 0x2864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* crypto addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CRYPTO_HDCP_REVISION 0x5800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HDCP_CRYPTO_CONFIG 0x5804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CRYPTO_INTERRUPT_SOURCE 0x5808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CRYPTO_INTERRUPT_MASK 0x580c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CRYPTO22_CONFIG 0x5818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CRYPTO22_STATUS 0x581c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SHA_256_DATA_IN 0x583c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AES_32_KEY_(x) (0x5870 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AES_32_DATA_IN 0x5880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CRYPTO14_CONFIG 0x58a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CRYPTO14_STATUS 0x58a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CRYPTO14_PRNM_OUT 0x58a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CRYPTO14_KM_0 0x58ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CRYPTO14_KM_1 0x58b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CRYPTO14_AN_0 0x58b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CRYPTO14_AN_1 0x58b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CRYPTO14_YOUR_KSV_0 0x58bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CRYPTO14_YOUR_KSV_1 0x58c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CRYPTO14_MI_0 0x58c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CRYPTO14_MI_1 0x58c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CRYPTO14_TI_0 0x58cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CRYPTO14_KI_0 0x58d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CRYPTO14_KI_1 0x58d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CRYPTO14_BLOCKS_NUM 0x58d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CRYPTO14_KEY_MEM_DATA_0 0x58dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CRYPTO14_KEY_MEM_DATA_1 0x58e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CRYPTO14_SHA1_MSG_DATA 0x58e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TRNG_CTRL 0x58fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TRNG_DATA_RDY 0x5900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TRNG_DATA 0x5904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* cipher addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HDCP_REVISION 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define INTERRUPT_SOURCE 0x60004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define INTERRUPT_MASK 0x60008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HDCP_CIPHER_CONFIG 0x6000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AES_128_KEY_0 0x60010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AES_128_KEY_1 0x60014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AES_128_KEY_2 0x60018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AES_128_KEY_3 0x6001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AES_128_RANDOM_0 0x60020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AES_128_RANDOM_1 0x60024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CIPHER14_KM_0 0x60028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CIPHER14_KM_1 0x6002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CIPHER14_STATUS 0x60030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CIPHER14_RI_PJ_STATUS 0x60034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CIPHER_MODE 0x60038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CIPHER14_AN_0 0x6003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CIPHER14_AN_1 0x60040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CIPHER22_AUTH 0x60044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CIPHER14_R0_DP_STATUS 0x60048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CIPHER14_BOOTSTRAP 0x6004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DPTX_FRMR_DATA_CLK_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DPTX_PHY_DATA_RSTN_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DPTX_PHY_DATA_CLK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DPTX_PHY_CHAR_RSTN_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DPTX_PHY_CHAR_CLK_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SOURCE_AUX_SYS_CLK_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DPTX_SYS_CLK_RSTN_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DPTX_SYS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CFG_DPTX_VIF_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SOURCE_PHY_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SOURCE_PHY_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SOURCE_PKT_SYS_RSTN_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SOURCE_PKT_SYS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SOURCE_PKT_DATA_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SOURCE_PKT_DATA_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SPDIF_CDR_CLK_RSTN_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SPDIF_CDR_CLK_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SOURCE_AIF_SYS_RSTN_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SOURCE_AIF_SYS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SOURCE_AIF_CLK_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SOURCE_AIF_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SOURCE_CIPHER_SYS_CLK_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SOURCE_CIPHER_CHAR_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SOURCE_CRYPTO_SYS_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define APB_IRAM_PATH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define APB_DRAM_PATH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define APB_XT_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MAILBOX_INT_MASK_BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PIF_INT_MASK_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ALL_INT_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MB_OPCODE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MB_MODULE_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MB_SIZE_MSB_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MB_SIZE_LSB_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MB_DATA_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MB_MODULE_ID_DP_TX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MB_MODULE_ID_HDCP_TX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MB_MODULE_ID_HDCP_RX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MB_MODULE_ID_HDCP_GENERAL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MB_MODULE_ID_GENERAL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* general opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GENERAL_MAIN_CONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GENERAL_TEST_ECHO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GENERAL_BUS_SETTINGS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GENERAL_TEST_ACCESS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DPTX_SET_POWER_MNG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DPTX_SET_HOST_CAPABILITIES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DPTX_GET_EDID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DPTX_READ_DPCD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DPTX_WRITE_DPCD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DPTX_ENABLE_EVENT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DPTX_WRITE_REGISTER 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DPTX_READ_REGISTER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DPTX_WRITE_FIELD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DPTX_TRAINING_CONTROL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DPTX_READ_EVENT 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DPTX_READ_LINK_STAT 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DPTX_SET_VIDEO 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DPTX_SET_AUDIO 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DPTX_GET_LAST_AUX_STAUS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DPTX_SET_LINK_BREAK_POINT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DPTX_FORCE_LANES 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DPTX_HPD_STATE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FW_STANDBY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FW_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DPTX_EVENT_ENABLE_HPD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DPTX_EVENT_ENABLE_TRAINING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define LINK_TRAINING_NOT_ACTIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define LINK_TRAINING_RUN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define LINK_TRAINING_RESTART 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CONTROL_VIDEO_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CONTROL_VIDEO_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TU_CNT_RST_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define VIF_BYPASS_INTERLACE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define INTERLACE_FMT_DET BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define INTERLACE_DTCT_WIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DP_FRAMER_SP_INTERLACE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DP_FRAMER_SP_HSP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DP_FRAMER_SP_VSP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AUX_HOST_INVERT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FAST_LT_SUPPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FAST_LT_NOT_SUPPORT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define LANE_MAPPING_NORMAL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define LANE_MAPPING_FLIPPED 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ENHANCED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SCRAMBLER_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define FULL_LT_STARTED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FASE_LT_STARTED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLK_RECOVERY_FINISHED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EQ_PHASE_FINISHED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define FASE_LT_START_FINISHED BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_RECOVERY_FAILED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define EQ_PHASE_FAILED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FASE_LT_FAILED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DPTX_HPD_EVENT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DPTX_TRAINING_EVENT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HDCP_TX_STATUS_EVENT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define HDCP2_TX_IS_KM_STORED_EVENT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define HDCP2_TX_STORE_KM_EVENT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TU_SIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AUDIO_PACK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SAMPLING_FREQ(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SYNC_WR_TO_CH_ZERO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define I2S_DEC_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AUDIO_SW_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SMPL2PKT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define AUDIO_TYPE_LPCM (2 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TRANS_SMPL_WIDTH_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TRANS_SMPL_WIDTH_24 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TRANS_SMPL_WIDTH_32 (2 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SPDIF_ENABLE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SPDIF_AVG_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SPDIF_JITTER_BYPASS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Reference cycles when using lane clock as reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define LANE_REF_CYC 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) enum voltage_swing_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) VOLTAGE_LEVEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) VOLTAGE_LEVEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) VOLTAGE_LEVEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) VOLTAGE_LEVEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) enum pre_emphasis_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PRE_EMPHASIS_LEVEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PRE_EMPHASIS_LEVEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PRE_EMPHASIS_LEVEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PRE_EMPHASIS_LEVEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enum pattern_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PTS1 = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PTS2 = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PTS3 = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PTS4 = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DP_NONE = BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) enum vic_color_depth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BCS_6 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BCS_8 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BCS_10 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BCS_12 = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BCS_16 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum vic_bt_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BT_601 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) BT_709 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void cdn_dp_clock_reset(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 i_size, const u32 *d_mem, u32 d_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int cdn_dp_event_config(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 cdn_dp_get_event(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int cdn_dp_get_edid_block(void *dp, u8 *edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int block, size_t length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int cdn_dp_train_link(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int cdn_dp_config_video(struct cdn_dp_device *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif /* _CDN_DP_REG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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