^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chris Zhong <zyw@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cdn-dp-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "cdn-dp-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct cdn_dp_port *port = dp->port[dp->active_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int rate = drm_dp_bw_code_to_link_rate(dp->link.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DP_TRAIN_VOLTAGE_SWING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) tcphy_dp_set_phy_config(port->phy, rate, dp->link.num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) swing, pre_emphasis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t dp_train_pat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 phy_config, global_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) global_config = NUM_LANES(dp->link.num_lanes - 1) | SST_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DP_TX_PHY_SKEW_BYPASS(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DP_TX_PHY_DISPARITY_RST(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DP_TX_PHY_LANE0_SKEW(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DP_TX_PHY_LANE1_SKEW(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DP_TX_PHY_LANE2_SKEW(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DP_TX_PHY_LANE3_SKEW(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DP_TX_PHY_10BIT_ENABLE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (pattern != DP_TRAINING_PATTERN_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) global_config |= NO_VIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) phy_config |= DP_TX_PHY_TRAINING_ENABLE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DP_TX_PHY_SCRAMBLER_BYPASS(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DP_TX_PHY_TRAINING_PATTERN(pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = cdn_dp_reg_write(dp, DP_FRAMER_GLOBAL_CONFIG, global_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DRM_ERROR("fail to set DP_FRAMER_GLOBAL_CONFIG, error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret = cdn_dp_reg_write(dp, DP_TX_PHY_CONFIG_REG, phy_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DRM_ERROR("fail to set DP_TX_PHY_CONFIG_REG, error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->link.num_lanes) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (drm_dp_enhanced_frame_cap(dp->dpcd) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * A setting of 1 indicates that this is an eDP device that uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * only Enhanced Framing, independently of the setting by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * source of ENHANCED_FRAME_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_FRAMING_CHANGE_CAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DRM_ERROR("failed to set DPTX_ENHNCD, error: %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u8 cdn_dp_pre_emphasis_max(u8 voltage_swing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return DP_TRAIN_PRE_EMPH_LEVEL_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return DP_TRAIN_PRE_EMPH_LEVEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return DP_TRAIN_PRE_EMPH_LEVEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return DP_TRAIN_PRE_EMPH_LEVEL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void cdn_dp_get_adjust_train(struct cdn_dp_device *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uint8_t link_status[DP_LINK_STATUS_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint8_t v = 0, p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uint8_t preemph_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) for (i = 0; i < dp->link.num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) v = max(v, drm_dp_get_adjust_request_voltage(link_status, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (v >= VOLTAGE_LEVEL_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v = VOLTAGE_LEVEL_2 | DP_TRAIN_MAX_SWING_REACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) preemph_max = cdn_dp_pre_emphasis_max(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (p >= preemph_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 0; i < dp->link.num_lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dp->train_set[i] = v | p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * or 1.2 devices that support it, Training Pattern 2 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u32 cdn_dp_select_chaneq_pattern(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 training_pattern = DP_TRAINING_PATTERN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * cdn dp support HBR2 also support TPS3. TPS3 support is also mandatory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * for downstream devices that support HBR2. However, not all sinks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * follow the spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (drm_dp_tps3_supported(dp->dpcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) training_pattern = DP_TRAINING_PATTERN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return training_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static bool cdn_dp_link_max_vswing_reached(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (lane = 0; lane < dp->link.num_lanes; lane++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int cdn_dp_update_link_train(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cdn_dp_set_signal_levels(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dp->train_set, dp->link.num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret != dp->link.num_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int cdn_dp_set_link_train(struct cdn_dp_device *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint8_t dp_train_pat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) uint8_t buf[sizeof(dp->train_set) + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) buf[0] = dp_train_pat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DP_TRAINING_PATTERN_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* don't write DP_TRAINING_LANEx_SET on disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) memcpy(buf + 1, dp->train_set, dp->link.num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) len = dp->link.num_lanes + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret != len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int cdn_dp_reset_link_train(struct cdn_dp_device *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) uint8_t dp_train_pat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) memset(dp->train_set, 0, sizeof(dp->train_set));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cdn_dp_set_signal_levels(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = cdn_dp_set_pattern(dp, dp_train_pat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return cdn_dp_set_link_train(dp, dp_train_pat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Enable corresponding port and start training pattern 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int cdn_dp_link_training_clock_recovery(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 link_status[DP_LINK_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 voltage_tries, max_vswing_tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* clock recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = cdn_dp_reset_link_train(dp, DP_TRAINING_PATTERN_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DP_LINK_SCRAMBLING_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DRM_ERROR("failed to start link train\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) voltage_tries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) max_vswing_tries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) drm_dp_link_train_clock_recovery_delay(dp->dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DP_LINK_STATUS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DRM_ERROR("failed to get link status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (drm_dp_clock_recovery_ok(link_status, dp->link.num_lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DRM_DEBUG_KMS("clock recovery OK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (voltage_tries >= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DRM_DEBUG_KMS("Same voltage tried 5 times\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (max_vswing_tries >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DRM_DEBUG_KMS("Max Voltage Swing reached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Update training set as requested by target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cdn_dp_get_adjust_train(dp, link_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (cdn_dp_update_link_train(dp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DRM_ERROR("failed to update link training\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ++voltage_tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) voltage_tries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (cdn_dp_link_max_vswing_reached(dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ++max_vswing_tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int cdn_dp_link_training_channel_equalization(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int tries, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 training_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint8_t link_status[DP_LINK_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) training_pattern = cdn_dp_select_chaneq_pattern(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = cdn_dp_set_pattern(dp, training_pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = cdn_dp_set_link_train(dp, training_pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DRM_ERROR("failed to start channel equalization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) for (tries = 0; tries < 5; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) drm_dp_link_train_channel_eq_delay(dp->dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DP_LINK_STATUS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DRM_ERROR("failed to get link status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Make sure clock is still ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!drm_dp_clock_recovery_ok(link_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dp->link.num_lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DRM_DEBUG_KMS("Clock recovery check failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (drm_dp_channel_eq_ok(link_status, dp->link.num_lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DRM_DEBUG_KMS("Channel EQ done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Update training set as requested by target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cdn_dp_get_adjust_train(dp, link_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (cdn_dp_update_link_train(dp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DRM_ERROR("failed to update link training\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Try 5 times, else fail and try at lower BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (tries == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int cdn_dp_stop_link_train(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret = cdn_dp_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return cdn_dp_set_link_train(dp, DP_TRAINING_PATTERN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (dp->link.rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case DP_LINK_BW_1_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case DP_LINK_BW_2_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dp->link.rate = DP_LINK_BW_1_62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case DP_LINK_BW_5_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dp->link.rate = DP_LINK_BW_2_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dp->link.rate = DP_LINK_BW_5_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int cdn_dp_software_train_link(struct cdn_dp_device *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct cdn_dp_port *port = dp->port[dp->active_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret, stop_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 link_config[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 rate, sink_max, source_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bool ssc_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sizeof(dp->dpcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) source_max = dp->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sink_max = drm_dp_max_lane_count(dp->dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dp->link.num_lanes = min(source_max, sink_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sink_max = drm_dp_max_link_rate(dp->dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rate = min(source_max, sink_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ssc_on = !!(dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) link_config[0] = ssc_on ? DP_SPREAD_AMP_0_5 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) link_config[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) link_config[1] = DP_SET_ANSI_8B10B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = tcphy_dp_set_link_rate(port->phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drm_dp_bw_code_to_link_rate(dp->link.rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ssc_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DRM_ERROR("failed to set link rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = tcphy_dp_set_lane_count(port->phy, dp->link.num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DRM_ERROR("failed to set lane count: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Write the link configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) link_config[0] = dp->link.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) link_config[1] = dp->link.num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (drm_dp_enhanced_frame_cap(dp->dpcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = cdn_dp_link_training_clock_recovery(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!cdn_dp_get_lower_link_rate(dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DRM_ERROR("training clock recovery failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = cdn_dp_link_training_channel_equalization(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!cdn_dp_get_lower_link_rate(dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DRM_ERROR("training channel eq failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) stop_err = cdn_dp_stop_link_train(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (stop_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DRM_ERROR("stop training fail, error: %d\n", stop_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return stop_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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