^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2012 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef _TRINITYD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _TRINITYD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* pm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* cg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CG_CGTT_LOCAL_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CG_CGTT_LOCAL_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* smc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define STATE_VALID(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define STATE_VALID_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define STATE_VALID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define CLK_DIVIDER(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define CLK_DIVIDER_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define CLK_DIVIDER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define VID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define VID_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define VID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define LVRT(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define LVRT_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define LVRT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define DS_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define DS_DIV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) # define DS_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define DS_SH_DIV(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define DS_SH_DIV_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define DS_SH_DIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define DISPLAY_WM(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define DISPLAY_WM_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define DISPLAY_WM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define VCE_WM(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) # define VCE_WM_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define VCE_WM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define GNB_SLOW(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define GNB_SLOW_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define GNB_SLOW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define FORCE_NBPS1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define FORCE_NBPS1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define FORCE_NBPS1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMU_SCLK_DPM_STATE_0_AT 0x1f010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define AT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define AT_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define AT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define PD_SCLK_DIVIDER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define PD_SCLK_DIVIDER_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define PD_SCLK_DIVIDER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SMU_SCLK_DPM_CNTL 0x1f100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define SCLK_DPM_EN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define SCLK_DPM_EN_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define SCLK_DPM_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define SCLK_DPM_BOOT_STATE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define SCLK_DPM_BOOT_STATE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define VOLTAGE_CHG_EN(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define VOLTAGE_CHG_EN_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define VOLTAGE_CHG_EN_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SMU_SCLK_DPM_TT_CNTL 0x1f108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define SCLK_TT_EN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define SCLK_TT_EN_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define SCLK_TT_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SMU_SCLK_DPM_TTT 0x1f10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define LT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define LT_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define LT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define HT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define HT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define HT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SMU_UVD_DPM_STATES 0x1f1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMU_UVD_DPM_CNTL 0x1f1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMU_S_PG_CNTL 0x1f118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define DS_PG_EN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define DS_PG_EN_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define DS_PG_EN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GFX_POWER_GATING_CNTL 0x1f38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define PDS_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define PDS_DIV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define PDS_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define SSSD(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define SSSD_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define SSSD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PM_CONFIG 0x1f428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define SVI_Mode (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PM_I_CNTL_1 0x1f464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define SCLK_DPM(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define SCLK_DPM_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define SCLK_DPM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define DS_PG_CNTL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define DS_PG_CNTL_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define DS_PG_CNTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PM_TP 0x1f468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NB_PSTATE_CONFIG 0x1f5f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define Dpm0PgNbPsLo(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define Dpm0PgNbPsLo_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define Dpm0PgNbPsLo_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define Dpm0PgNbPsHi(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define Dpm0PgNbPsHi_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define Dpm0PgNbPsHi_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define DpmXNbPsLo(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define DpmXNbPsLo_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define DpmXNbPsLo_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define DpmXNbPsHi(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define DpmXNbPsHi_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define DpmXNbPsHi_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DC_CAC_VALUE 0x1f908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPU_CAC_AVRG_CNTL 0x1f920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define WINDOW_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define WINDOW_SIZE_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define WINDOW_SIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CC_SMU_MISC_FUSES 0xe0001004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define MinSClkDid(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define MinSClkDid_MASK (0x7f << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define MinSClkDid_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CC_SMU_TST_EFUSE1_MISC 0xe000101c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define RB_BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define RB_BACKEND_DISABLE_MASK (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define RB_BACKEND_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SMU_SCRATCH_A 0xe0003024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SMU_SCRATCH0 0xe0003040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* mmio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SMC_INT_REQ 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SMC_MESSAGE_0 0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SMC_RESP_0 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GENERAL_PWRMGT 0x670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SCLK_PWRMGT_CNTL 0x678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define DYN_PWR_DOWN_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define RESET_BUSY_CNT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) # define RESET_SCLK_CNT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) # define DYN_GFX_CLK_OFF_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define GFX_CLK_FORCE_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define DYNAMIC_PM_EN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) # define TARGET_STATE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) # define TARGET_STATE_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) # define TARGET_STATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define CURRENT_STATE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define CURRENT_STATE_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define CURRENT_STATE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CG_GIPOTS 0x6d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) # define CG_GIPOT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define CG_GIPOT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define CG_GIPOT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CG_PG_CTRL 0x6e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) # define SP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) # define SP_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) # define SP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define SU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define SU_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) # define SU_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CG_MISC_REG 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CG_THERMAL_INT_CTRL 0x738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) # define DIG_THERM_INTH(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # define DIG_THERM_INTH_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define DIG_THERM_INTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) # define DIG_THERM_INTL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define DIG_THERM_INTL_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) # define DIG_THERM_INTL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) # define THERM_INTH_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) # define THERM_INTL_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CG_CG_VOLTAGE_CNTL 0x770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) # define EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HW_REV 0x5564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) # define ATI_REV_ID_MASK (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) # define ATI_REV_ID_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CGTS_SM_CTRL_REG 0x9150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GB_ADDR_CONFIG 0x98f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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