Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright 2012 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #ifndef _SUMOD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define _SUMOD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* pm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* rcu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RCU_FW_VERSION                                  0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RCU_PWR_GATING_SEQ0                             0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RCU_PWR_GATING_SEQ1                             0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RCU_PWR_GATING_CNTL                             0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #       define PWR_GATING_EN                            (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #       define RSVD_MASK                                (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #       define PCV(x)                                   ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #       define PCV_MASK                                 (0x1f << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #       define PCV_SHIFT                                3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #       define PCP(x)                                   ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #       define PCP_MASK                                 (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #       define PCP_SHIFT                                8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #       define RPW(x)                                   ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #       define RPW_MASK                                 (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #       define RPW_SHIFT                                16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #       define ID(x)                                    ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #       define ID_MASK                                  (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #       define ID_SHIFT                                 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #       define PGS(x)                                   ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #       define PGS_MASK                                 (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #       define PGS_SHIFT                                28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RCU_ALTVDDNB_NOTIFY                             0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RCU_LCLK_SCALING_CNTL                           0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #       define LCLK_SCALING_EN                          (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #       define LCLK_SCALING_TYPE                        (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #       define LCLK_SCALING_TIMER_PRESCALER(x)          ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #       define LCLK_SCALING_TIMER_PRESCALER_MASK        (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #       define LCLK_SCALING_TIMER_PRESCALER_SHIFT       4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #       define LCLK_SCALING_TIMER_PERIOD(x)             ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #       define LCLK_SCALING_TIMER_PERIOD_MASK           (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #       define LCLK_SCALING_TIMER_PERIOD_SHIFT          16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RCU_PWR_GATING_CNTL_2                           0x4a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #       define MPPU(x)                                  ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #       define MPPU_MASK                                (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #       define MPPU_SHIFT                               0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #       define MPPD(x)                                  ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #       define MPPD_MASK                                (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #       define MPPD_SHIFT                               16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RCU_PWR_GATING_CNTL_3                           0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #       define DPPU(x)                                  ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #       define DPPU_MASK                                (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #       define DPPU_SHIFT                               0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #       define DPPD(x)                                  ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #       define DPPD_MASK                                (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #       define DPPD_SHIFT                               16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define RCU_PWR_GATING_CNTL_4                           0x4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #       define RT(x)                                    ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #       define RT_MASK                                  (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #       define RT_SHIFT                                 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #       define IT(x)                                    ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #       define IT_MASK                                  (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #       define IT_SHIFT                                 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* yes these two have the same address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define RCU_PWR_GATING_CNTL_5                           0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define RCU_GPU_BOOST_DISABLE                           0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MCU_M3ARB_INDEX                                 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MCU_M3ARB_PARAMS                                0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define RCU_GNB_PWR_REP_TIMER_CNTL                      0x50C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define RCU_SclkDpmTdpLimit01                           0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define RCU_SclkDpmTdpLimit23                           0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define RCU_SclkDpmTdpLimit47                           0x51C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define RCU_SclkDpmTdpLimitPG                           0x520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GNB_TDP_LIMIT                                   0x540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RCU_BOOST_MARGIN                                0x544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RCU_THROTTLE_MARGIN                             0x548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMU_PCIE_PG_ARGS                                0x58C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SMU_PCIE_PG_ARGS_2                              0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMU_PCIE_PG_ARGS_3                              0x59C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* mmio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RCU_STATUS                                      0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #       define GMC_PWR_GATER_BUSY                       (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #       define GFX_PWR_GATER_BUSY                       (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #       define UVD_PWR_GATER_BUSY                       (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #       define PCIE_PWR_GATER_BUSY                      (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #       define GMC_PWR_GATER_STATE                      (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #       define GFX_PWR_GATER_STATE                      (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #       define UVD_PWR_GATER_STATE                      (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #       define PCIE_PWR_GATER_STATE                     (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #       define GFX1_PWR_GATER_BUSY                      (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #       define GFX2_PWR_GATER_BUSY                      (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #       define GFX1_PWR_GATER_STATE                     (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #       define GFX2_PWR_GATER_STATE                     (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GFX_INT_REQ                                     0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #       define INT_REQ                                  (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #       define SERV_INDEX(x)                            ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #       define SERV_INDEX_MASK                          (0xff << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #       define SERV_INDEX_SHIFT                         1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GFX_INT_STATUS                                  0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #       define INT_ACK                                  (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #       define INT_DONE                                 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CG_SCLK_CNTL                                    0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #       define SCLK_DIVIDER(x)                          ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #       define SCLK_DIVIDER_MASK                        (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #       define SCLK_DIVIDER_SHIFT                       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CG_SCLK_STATUS                                  0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #       define SCLK_OVERCLK_DETECT                      (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CG_DCLK_CNTL                                    0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #       define DCLK_DIVIDER_MASK                        0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #       define DCLK_DIR_CNTL_EN                         (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CG_DCLK_STATUS                                  0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #       define DCLK_STATUS                              (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CG_VCLK_CNTL                                    0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #       define VCLK_DIVIDER_MASK                        0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #       define VCLK_DIR_CNTL_EN                         (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CG_VCLK_STATUS                                  0x61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GENERAL_PWRMGT                                  0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #       define STATIC_PM_EN                             (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SCLK_PWRMGT_CNTL                                0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #       define SCLK_PWRMGT_OFF                          (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #       define SCLK_LOW_D1                              (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #       define FIR_RESET                                (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #       define FIR_FORCE_TREND_SEL                      (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #       define FIR_TREND_MODE                           (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #       define DYN_GFX_CLK_OFF_EN                       (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #       define GFX_CLK_FORCE_ON                         (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #       define GFX_CLK_REQUEST_OFF                      (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #       define GFX_CLK_FORCE_OFF                        (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #       define GFX_CLK_OFF_ACPI_D1                      (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #       define GFX_CLK_OFF_ACPI_D2                      (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #       define GFX_CLK_OFF_ACPI_D3                      (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #       define GFX_VOLTAGE_CHANGE_EN                    (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #       define GFX_VOLTAGE_CHANGE_MODE                  (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TARGET_AND_CURRENT_PROFILE_INDEX                0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #       define TARG_SCLK_INDEX(x)                       ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #       define TARG_SCLK_INDEX_MASK                     (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #       define TARG_SCLK_INDEX_SHIFT                    6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #       define CURR_SCLK_INDEX(x)                       ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #       define CURR_SCLK_INDEX_MASK                     (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #       define CURR_SCLK_INDEX_SHIFT                    9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #       define TARG_INDEX(x)                            ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #       define TARG_INDEX_MASK                          (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #       define TARG_INDEX_SHIFT                         12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #       define CURR_INDEX(x)                            ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #       define CURR_INDEX_MASK                          (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #       define CURR_INDEX_SHIFT                         15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CG_SCLK_DPM_CTRL                                0x684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #       define SCLK_FSTATE_0_DIV(x)                     ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #       define SCLK_FSTATE_0_DIV_MASK                   (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #       define SCLK_FSTATE_0_DIV_SHIFT                  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #       define SCLK_FSTATE_0_VLD                        (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #       define SCLK_FSTATE_1_DIV(x)                     ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #       define SCLK_FSTATE_1_DIV_MASK                   (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #       define SCLK_FSTATE_1_DIV_SHIFT                  8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #       define SCLK_FSTATE_1_VLD                        (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #       define SCLK_FSTATE_2_DIV(x)                     ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #       define SCLK_FSTATE_2_DIV_MASK                   (0x7f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #       define SCLK_FSTATE_2_DIV_SHIFT                  16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #       define SCLK_FSTATE_2_VLD                        (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #       define SCLK_FSTATE_3_DIV(x)                     ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #       define SCLK_FSTATE_3_DIV_MASK                   (0x7f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #       define SCLK_FSTATE_3_DIV_SHIFT                  24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #       define SCLK_FSTATE_3_VLD                        (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CG_SCLK_DPM_CTRL_2                              0x688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CG_GCOOR                                        0x68c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #       define PHC(x)                                   ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #       define PHC_MASK                                 (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #       define PHC_SHIFT                                0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #       define SDC(x)                                   ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #       define SDC_MASK                                 (0x3ff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #       define SDC_SHIFT                                9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #       define SU(x)                                    ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #       define SU_MASK                                  (0xf << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #       define SU_SHIFT                                 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #       define DIV_ID(x)                                ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #       define DIV_ID_MASK                              (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #       define DIV_ID_SHIFT                             28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CG_FTV                                          0x690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CG_FFCT_0                                       0x694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #       define UTC_0(x)                                 ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #       define UTC_0_MASK                               (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #       define UTC_0_SHIFT                              0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #       define DTC_0(x)                                 ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #       define DTC_0_MASK                               (0x3ff << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #       define DTC_0_SHIFT                              10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CG_GIT                                          0x6d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #       define CG_GICST(x)                              ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #       define CG_GICST_MASK                            (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #       define CG_GICST_SHIFT                           0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #       define CG_GIPOT(x)                              ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #       define CG_GIPOT_MASK                            (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #       define CG_GIPOT_SHIFT                           16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CG_SCLK_DPM_CTRL_3                              0x6e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #       define FORCE_SCLK_STATE(x)                      ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #       define FORCE_SCLK_STATE_MASK                    (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #       define FORCE_SCLK_STATE_SHIFT                   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #       define FORCE_SCLK_STATE_EN                      (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #       define GNB_TT(x)                                ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #       define GNB_TT_MASK                              (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #       define GNB_TT_SHIFT                             8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #       define GNB_THERMTHRO_MASK                       (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #       define CNB_THERMTHRO_MASK_SCLK                  (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #       define DPM_SCLK_ENABLE                          (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #       define GNB_SLOW_FSTATE_0_MASK                   (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #       define GNB_SLOW_FSTATE_0_SHIFT                  23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #       define FORCE_NB_PSTATE_1                        (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CG_SSP                                          0x6e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #       define SST(x)                                   ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #       define SST_MASK                                 (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #       define SST_SHIFT                                0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #       define SSTU(x)                                  ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #       define SSTU_MASK                                (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #       define SSTU_SHIFT                               16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CG_ACPI_CNTL                                    0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #       define SCLK_ACPI_DIV(x)                         ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #       define SCLK_ACPI_DIV_MASK                       (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #       define SCLK_ACPI_DIV_SHIFT                      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CG_SCLK_DPM_CTRL_4                              0x71c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #       define DC_HDC(x)                                ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #       define DC_HDC_MASK                              (0x3fff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #       define DC_HDC_SHIFT                             14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #       define DC_HU(x)                                 ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #       define DC_HU_MASK                               (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #       define DC_HU_SHIFT                              28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CG_SCLK_DPM_CTRL_5                              0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #       define SCLK_FSTATE_BOOTUP(x)                    ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #       define SCLK_FSTATE_BOOTUP_MASK                  (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #       define SCLK_FSTATE_BOOTUP_SHIFT                 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #       define TT_TP(x)                                 ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #       define TT_TP_MASK                               (0xffff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #       define TT_TP_SHIFT                              3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #       define TT_TU(x)                                 ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #       define TT_TU_MASK                               (0xff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #       define TT_TU_SHIFT                              19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CG_SCLK_DPM_CTRL_6                              0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CG_AT_0                                         0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #       define CG_R(x)                                  ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #       define CG_R_MASK                                (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #       define CG_R_SHIFT                               0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #       define CG_L(x)                                  ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #       define CG_L_MASK                                (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #       define CG_L_SHIFT                               16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CG_AT_1                                         0x72c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CG_AT_2                                         0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define	CG_THERMAL_INT					0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define		DIG_THERM_INTH(x)			((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define		DIG_THERM_INTH_MASK			0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define		DIG_THERM_INTH_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define		DIG_THERM_INTL(x)			((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define		DIG_THERM_INTL_MASK			0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define		DIG_THERM_INTL_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define 	THERM_INT_MASK_HIGH			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define 	THERM_INT_MASK_LOW			(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CG_AT_3                                         0x738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CG_AT_4                                         0x73c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CG_AT_5                                         0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CG_AT_6                                         0x744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CG_AT_7                                         0x748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CG_BSP_0                                        0x750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #       define BSP(x)                                   ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #       define BSP_MASK                                 (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #       define BSP_SHIFT                                0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #       define BSU(x)                                   ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #       define BSU_MASK                                 (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #       define BSU_SHIFT                                16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CG_CG_VOLTAGE_CNTL                              0x770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #       define REQ                                      (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #       define LEVEL(x)                                 ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #       define LEVEL_MASK                               (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #       define LEVEL_SHIFT                              1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #       define CG_VOLTAGE_EN                            (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #       define FORCE                                    (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #       define PERIOD(x)                                ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #       define PERIOD_MASK                              (0xffff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #       define PERIOD_SHIFT                             8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #       define UNIT(x)                                  ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #       define UNIT_MASK                                (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #       define UNIT_SHIFT                               24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CG_ACPI_VOLTAGE_CNTL                            0x780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #       define ACPI_VOLTAGE_EN                          (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CG_DPM_VOLTAGE_CNTL                             0x788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #       define DPM_STATE0_LEVEL_MASK                    (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #       define DPM_STATE0_LEVEL_SHIFT                   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #       define DPM_VOLTAGE_EN                           (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CG_PWR_GATING_CNTL                              0x7ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #       define DYN_PWR_DOWN_EN                          (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #       define ACPI_PWR_DOWN_EN                         (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #       define GFX_CLK_OFF_PWR_DOWN_EN                  (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #       define IOC_DISGPU_PWR_DOWN_EN                   (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #       define FORCE_POWR_ON                            (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #       define PGP(x)                                   ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #       define PGP_MASK                                 (0xffff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #       define PGP_SHIFT                                8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #       define PGU(x)                                   ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #       define PGU_MASK                                 (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #       define PGU_SHIFT                                24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CG_CGTT_LOCAL_0                                 0x7d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CG_CGTT_LOCAL_1                                 0x7d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DEEP_SLEEP_CNTL                                 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #       define R_DIS                                    (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #       define HS(x)                                    ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #       define HS_MASK                                  (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #       define HS_SHIFT                                 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #       define ENABLE_DS                                (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DEEP_SLEEP_CNTL2                                0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #       define LB_UFP_EN                                (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #       define INOUT_C(x)                               ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #       define INOUT_C_MASK                             (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #       define INOUT_C_SHIFT                            4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CG_SCRATCH2                                     0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CG_SCLK_DPM_CTRL_11                             0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define HW_REV   					0x5564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #       define ATI_REV_ID_MASK                          (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #       define ATI_REV_ID_SHIFT                         28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DOUT_SCRATCH3   				0x611c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define GB_ADDR_CONFIG  				0x98f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #endif