^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2013 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef SMU7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMU7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #pragma pack(push, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMU7_CONTEXT_ID_SMC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMU7_CONTEXT_ID_VBIOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMU7_CONTEXT_ID_SMC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMU7_CONTEXT_ID_VBIOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SMU7_MAX_LEVELS_VDDC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SMU7_MAX_LEVELS_VDDCI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SMU7_MAX_LEVELS_MVDD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMU7_MAX_LEVELS_VDDNB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DPM_NO_LIMIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DPM_NO_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DPM_GO_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DPM_GO_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SMU7_FIRST_DPM_MEMORY_LEVEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_CLAMP_MODE_VRHOT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_CLAMP_MODE_THERM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_CLAMP_MODE_DC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct SMU7_PIDController
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uint32_t Ki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int32_t LFWindupUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int32_t LFWindupLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint32_t StatePrecision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint32_t LfPrecision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint32_t LfOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint32_t MaxState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) uint32_t MaxLfFraction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) uint32_t StateShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) typedef struct SMU7_PIDController SMU7_PIDController;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) // -------------------------------------------------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SMU7_SCLK_DPM_CONFIG_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMU7_MCLK_DPM_CONFIG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SMU7_UVD_DPM_CONFIG_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SMU7_VCE_DPM_CONFIG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SMU7_ACP_DPM_CONFIG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SMU7_SAMU_DPM_CONFIG_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct SMU7_Firmware_Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint32_t Digest[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint32_t Version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint32_t HeaderSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint32_t Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint32_t EntryPoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint32_t CodeSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t ImageSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint32_t Rtos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint32_t SoftRegisters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint32_t DpmTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint32_t FanTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t CacConfigTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint32_t CacStatusTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uint32_t mcRegisterTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint32_t mcArbDramTimingTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint32_t PmFuseTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint32_t Globals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t Reserved[42];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t Signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum DisplayConfig {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PowerDown = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DP54x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DP54x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DP54x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DP27x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DP27x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DP27x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) HDMI297,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) HDMI162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DP324x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DP324x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DP324x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #pragma pack(pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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