^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef SI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SI_MAX_SH_GPRS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SI_MAX_TEMP_GPRS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SI_MAX_SH_THREADS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SI_MAX_SH_STACK_ENTRIES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SI_MAX_FRC_EOV_CNT 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SI_MAX_BACKENDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SI_MAX_BACKENDS_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SI_MAX_SIMDS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SI_MAX_SIMDS_MASK 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SI_MAX_PIPES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SI_MAX_PIPES_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SI_MAX_LDS_NUM 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SI_MAX_TCC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SI_MAX_TCC_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SMC IND accessor regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SMC_IND_INDEX_0 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SMC_IND_DATA_0 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SMC_IND_ACCESS_CNTL 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define AUTO_INCREMENT_IND_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SMC_MESSAGE_0 0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SMC_RESP_0 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SMC_CG_IND_START 0xc0030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SMC_CG_IND_END 0xc0040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CG_CGTT_LOCAL_0 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CG_CGTT_LOCAL_1 0x401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* SMC IND registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMC_SYSCON_RESET_CNTL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define RST_REG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define CK_DISABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define CKEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VGA_HDP_CONTROL 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VGA_MEMORY_DISABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DCCG_DISP_SLOW_SELECT_REG 0x4fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DCCG_DISP2_SLOW_SELECT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPLL_PDIV_A(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPLL_PDIV_A_MASK (0x7f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPLL_PDIV_A_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CG_SPLL_FUNC_CNTL_2 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPLL_CTLREQ_CHG (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCLK_MUX_UPDATE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CG_SPLL_FUNC_CNTL_3 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPLL_FB_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CG_SPLL_FUNC_CNTL_4 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPLL_STATUS 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPLL_CHG_STATUS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPLL_CNTL_MODE 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPLL_SW_DIR_CONTROL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define SPLL_REFCLK_SEL(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define SPLL_REFCLK_SEL_MASK (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CG_SPLL_SPREAD_SPECTRUM 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_S(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_S_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_S_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CG_SPLL_SPREAD_SPECTRUM_2 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_V(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_V_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CG_SPLL_AUTOSCALE_CNTL 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* discrete uvd clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CG_UPLL_FUNC_CNTL 0x634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define UPLL_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define UPLL_SLEEP_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define UPLL_BYPASS_EN_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define UPLL_CTLREQ_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define UPLL_VCO_MODE_MASK 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define UPLL_REF_DIV_MASK 0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define UPLL_CTLACK_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define UPLL_CTLACK2_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CG_UPLL_FUNC_CNTL_2 0x638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define UPLL_PDIV_A(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define UPLL_PDIV_A_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define UPLL_PDIV_B(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define UPLL_PDIV_B_MASK 0x00007F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define VCLK_SRC_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define VCLK_SRC_SEL_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define DCLK_SRC_SEL(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define DCLK_SRC_SEL_MASK 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CG_UPLL_FUNC_CNTL_3 0x63C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define UPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define UPLL_FB_DIV_MASK 0x01FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CG_UPLL_FUNC_CNTL_4 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define UPLL_SPARE_ISPARE9 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CG_UPLL_FUNC_CNTL_5 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define RESET_ANTI_MUX_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CG_UPLL_SPREAD_SPECTRUM 0x650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define SSEN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MPLL_BYPASSCLK_SEL 0x65c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define MPLL_CLKOUT_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # define MPLL_CLKOUT_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CG_CLKPIN_CNTL 0x660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define XTALIN_DIVIDE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define BCLK_AS_XCLK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CG_CLKPIN_CNTL_2 0x664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define FORCE_BIF_REFCLK_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define MUX_TCLK_TO_XCLK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define THM_CLK_CNTL 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define CMON_CLK_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define CMON_CLK_SEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define TMON_CLK_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define TMON_CLK_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MISC_CLK_CNTL 0x670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define ZCLK_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define ZCLK_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CG_THERMAL_CTRL 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DPM_EVENT_SRC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DPM_EVENT_SRC_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DIG_THERM_DPM(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DIG_THERM_DPM_MASK 0x003FC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DIG_THERM_DPM_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CG_THERMAL_STATUS 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FDO_PWM_DUTY(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FDO_PWM_DUTY_MASK (0xff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FDO_PWM_DUTY_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CG_THERMAL_INT 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DIG_THERM_INTH(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DIG_THERM_INTH_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DIG_THERM_INTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DIG_THERM_INTL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DIG_THERM_INTL_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DIG_THERM_INTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define THERM_INT_MASK_HIGH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define THERM_INT_MASK_LOW (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CG_MULT_THERMAL_CTRL 0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEMP_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEMP_SEL_MASK (0xff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEMP_SEL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CG_MULT_THERMAL_STATUS 0x714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ASIC_MAX_TEMP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ASIC_MAX_TEMP_MASK 0x000001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ASIC_MAX_TEMP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CTF_TEMP(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CTF_TEMP_MASK 0x0003fe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CTF_TEMP_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CG_FDO_CTRL0 0x754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define FDO_STATIC_DUTY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FDO_STATIC_DUTY_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define FDO_STATIC_DUTY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CG_FDO_CTRL1 0x758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FMAX_DUTY100(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FMAX_DUTY100_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define FMAX_DUTY100_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CG_FDO_CTRL2 0x75C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TMIN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TMIN_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TMIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FDO_PWM_MODE(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FDO_PWM_MODE_MASK (7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define FDO_PWM_MODE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TACH_PWM_RESP_RATE(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TACH_PWM_RESP_RATE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CG_TACH_CTRL 0x770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) # define EDGE_PER_REV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) # define EDGE_PER_REV_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) # define EDGE_PER_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define TARGET_PERIOD(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define TARGET_PERIOD_MASK 0xfffffff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define TARGET_PERIOD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CG_TACH_STATUS 0x774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) # define TACH_PERIOD(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) # define TACH_PERIOD_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) # define TACH_PERIOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GENERAL_PWRMGT 0x780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define SW_SMIO_INDEX_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) # define SW_SMIO_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CG_TPC 0x784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SCLK_PWRMGT_CNTL 0x788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) # define SCLK_LOW_D1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) # define FIR_RESET (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) # define FIR_FORCE_TREND_SEL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define FIR_TREND_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) # define DYN_GFX_CLK_OFF_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) # define GFX_CLK_FORCE_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) # define GFX_CLK_REQUEST_OFF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) # define GFX_CLK_FORCE_OFF (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define DYN_LIGHT_SLEEP_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) # define CURRENT_STATE_INDEX_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) # define CURRENT_STATE_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CG_FTV 0x7bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CG_FFCT_0 0x7c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) # define UTC_0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) # define UTC_0_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) # define DTC_0(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) # define DTC_0_MASK (0x3ff << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CG_BSP 0x7fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define BSP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) # define BSP_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) # define BSU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define BSU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CG_AT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) # define CG_R(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) # define CG_R_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) # define CG_L(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) # define CG_L_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CG_GIT 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) # define CG_GICST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) # define CG_GICST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) # define CG_GIPOT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) # define CG_GIPOT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CG_SSP 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) # define SST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) # define SST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) # define SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) # define SSTU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CG_DISPLAY_GAP_CNTL 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) # define DISP1_GAP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) # define DISP1_GAP_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define DISP2_GAP(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # define DISP2_GAP_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) # define VBI_TIMER_COUNT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) # define VBI_TIMER_UNIT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) # define VBI_TIMER_UNIT_MASK (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # define DISP1_GAP_MCHG(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) # define DISP1_GAP_MCHG_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) # define DISP2_GAP_MCHG(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) # define DISP2_GAP_MCHG_MASK (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CG_ULV_CONTROL 0x878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CG_ULV_PARAMETER 0x87c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SMC_SCRATCH0 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CG_CAC_CTRL 0x8b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) # define CAC_WINDOW(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) # define CAC_WINDOW_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DMIF_ADDR_CONFIG 0xBD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DMIF_ADDR_CALC 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRBM_STATUS 0xE50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define VMC_BUSY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MCB_BUSY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MCB_NON_DISPLAY_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MCC_BUSY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MCD_BUSY (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SEM_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IH_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRBM_SOFT_RESET 0x0E60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SOFT_RESET_BIF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SOFT_RESET_DC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SOFT_RESET_DMA1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SOFT_RESET_GRBM (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SOFT_RESET_HDP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SOFT_RESET_IH (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SOFT_RESET_MC (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SOFT_RESET_ROM (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SOFT_RESET_SEM (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SOFT_RESET_VMC (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SOFT_RESET_DMA (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SOFT_RESET_TST (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SOFT_RESET_REGBB (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SOFT_RESET_ORB (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CC_SYS_RB_BACKEND_DISABLE 0xe80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRBM_READ_ERROR 0xE98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRBM_INT_CNTL 0xEA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRBM_INT_ACK 0xEA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRBM_STATUS2 0x0EC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DMA_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DMA1_BUSY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define VM_L2_CNTL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ENABLE_L2_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VM_L2_CNTL2 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define INVALIDATE_ALL_L1_TLBS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define INVALIDATE_L2_CACHE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define INVALIDATE_PTE_AND_PDE_CACHES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define INVALIDATE_ONLY_PTE_CACHES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define INVALIDATE_ONLY_PDE_CACHES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define VM_L2_CNTL3 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define BANK_SELECT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define VM_L2_STATUS 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define L2_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define VM_CONTEXT0_CNTL 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ENABLE_CONTEXT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define VM_CONTEXT1_CNTL 0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define VM_CONTEXT0_CNTL2 0x1430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define VM_CONTEXT1_CNTL2 0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PROTECTIONS_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PROTECTIONS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* bit 0: range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * bit 1: pde0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * bit 2: valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * bit 3: read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * bit 4: write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MEMORY_CLIENT_ID_MASK (0xff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MEMORY_CLIENT_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MEMORY_CLIENT_RW_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MEMORY_CLIENT_RW_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define FAULT_VMID_MASK (0xf << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define FAULT_VMID_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define VM_INVALIDATE_REQUEST 0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define VM_INVALIDATE_RESPONSE 0x147c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define VM_L2_CG 0x15c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MC_CG_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MC_LS_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MC_SHARED_CHMAP 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define NOOFCHAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define NOOFCHAN_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MC_SHARED_CHREMAP 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MC_VM_FB_LOCATION 0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MC_VM_AGP_TOP 0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MC_VM_AGP_BOT 0x202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MC_VM_AGP_BASE 0x2030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MC_VM_MX_L1_TLB_CNTL 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define ENABLE_L1_TLB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MC_SHARED_BLACKOUT_CNTL 0x20ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MC_HUB_MISC_HUB_CG 0x20b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MC_HUB_MISC_VM_CG 0x20bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MC_HUB_MISC_SIP_CG 0x20c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MC_XPB_CLK_GAT 0x2478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MC_CITF_MISC_RD_CG 0x2648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MC_CITF_MISC_WR_CG 0x264c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define MC_CITF_MISC_VM_CG 0x2650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MC_ARB_RAMCFG 0x2760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define NOOFBANK_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define NOOFRANK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define NOOFRANK_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define NOOFROWS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define NOOFROWS_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define NOOFCOLS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define NOOFCOLS_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CHANSIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define CHANSIZE_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CHANSIZE_OVERRIDE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define NOOFGROUPS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define NOOFGROUPS_MASK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MC_ARB_DRAM_TIMING 0x2774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MC_ARB_DRAM_TIMING2 0x2778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define MC_ARB_BURST_TIME 0x2808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define STATE0_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define STATE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define STATE1(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define STATE1_MASK (0x1f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define STATE1_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define STATE2(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define STATE2_MASK (0x1f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define STATE2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define STATE3(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define STATE3_MASK (0x1f << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define STATE3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define TRAIN_DONE_D0 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define TRAIN_DONE_D1 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MC_SEQ_SUP_CNTL 0x28c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define RUN_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MC_SEQ_SUP_PGM 0x28cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MC_PMG_AUTO_CMD 0x28d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define MC_IO_PAD_CNTL_D0 0x29d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MEM_FALL_OUT_CMD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define MC_SEQ_RAS_TIMING 0x28a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define MC_SEQ_CAS_TIMING 0x28a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define MC_SEQ_MISC_TIMING 0x28a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define MC_SEQ_MISC_TIMING2 0x28ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MC_SEQ_PMG_TIMING 0x28b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MC_SEQ_RD_CTL_D0 0x28b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MC_SEQ_RD_CTL_D1 0x28b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define MC_SEQ_WR_CTL_D0 0x28bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MC_SEQ_WR_CTL_D1 0x28c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MC_SEQ_MISC0_VEN_ID_VALUE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MC_SEQ_MISC0_REV_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MC_SEQ_MISC0_REV_ID_VALUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MC_SEQ_MISC1 0x2a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define MC_SEQ_RESERVE_M 0x2a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MC_PMG_CMD_EMRS 0x2a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MC_SEQ_IO_DEBUG_DATA 0x2a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MC_SEQ_MISC5 0x2a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MC_SEQ_MISC6 0x2a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MC_SEQ_MISC7 0x2a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MC_SEQ_RAS_TIMING_LP 0x2a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define MC_SEQ_CAS_TIMING_LP 0x2a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define MC_SEQ_MISC_TIMING_LP 0x2a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define MC_SEQ_MISC_TIMING2_LP 0x2a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MC_SEQ_WR_CTL_D1_LP 0x2a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define MC_PMG_CMD_MRS 0x2aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define MC_SEQ_RD_CTL_D1_LP 0x2b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define MC_PMG_CMD_MRS1 0x2b44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define MC_SEQ_PMG_TIMING_LP 0x2b4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define MC_SEQ_WR_CTL_2 0x2b54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define MC_SEQ_WR_CTL_2_LP 0x2b58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MC_PMG_CMD_MRS2 0x2b5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MCLK_PWRMGT_CNTL 0x2ba0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) # define DLL_SPEED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) # define DLL_SPEED_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) # define MRDCK0_PDNB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) # define MRDCK1_PDNB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) # define MRDCK0_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) # define MRDCK1_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DLL_CNTL 0x2ba4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) # define MRDCK0_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) # define MRDCK1_BYPASS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define MPLL_CNTL_MODE 0x2bb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) # define MPLL_MCLK_SEL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MPLL_FUNC_CNTL 0x2bb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define BWCTRL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define BWCTRL_MASK (0xff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MPLL_FUNC_CNTL_1 0x2bb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define VCO_MODE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define VCO_MODE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define CLKFRAC(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define CLKFRAC_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define CLKF(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define CLKF_MASK (0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define MPLL_FUNC_CNTL_2 0x2bbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define MPLL_AD_FUNC_CNTL 0x2bc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define YCLK_POST_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define YCLK_POST_DIV_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MPLL_DQ_FUNC_CNTL 0x2bc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define YCLK_SEL(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define YCLK_SEL_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MPLL_SS1 0x2bcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define CLKV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CLKV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define MPLL_SS2 0x2bd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define CLKS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define CLKS_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define HDP_HOST_PATH_CNTL 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define CLOCK_GATING_DIS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define HDP_NONSURFACE_BASE 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define HDP_NONSURFACE_INFO 0x2C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define HDP_NONSURFACE_SIZE 0x2C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define HDP_ADDR_CONFIG 0x2F48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define HDP_MISC_CNTL 0x2F4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define HDP_MEM_POWER_LS 0x2F50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define HDP_LS_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ATC_MISC_CG 0x3350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define IH_RB_CNTL 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) # define IH_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define IH_RB_BASE 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define IH_RB_RPTR 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define IH_RB_WPTR 0x3e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) # define RB_OVERFLOW (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) # define WPTR_OFFSET_MASK 0x3fffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define IH_RB_WPTR_ADDR_HI 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define IH_RB_WPTR_ADDR_LO 0x3e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define IH_CNTL 0x3e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) # define ENABLE_INTR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) # define IH_MC_SWAP(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) # define IH_MC_SWAP_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) # define IH_MC_SWAP_16BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) # define IH_MC_SWAP_32BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) # define IH_MC_SWAP_64BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) # define RPTR_REARM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) # define MC_WRREQ_CREDIT(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) # define MC_WR_CLEAN_CNT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) # define MC_VMID(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define CONFIG_MEMSIZE 0x5428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define INTERRUPT_CNTL 0x5468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) # define IH_DUMMY_RD_OVERRIDE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) # define IH_DUMMY_RD_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) # define IH_REQ_NONSNOOP_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) # define GEN_IH_INT_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define INTERRUPT_CNTL2 0x546c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define BIF_FB_EN 0x5490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define FB_READ_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define FB_WRITE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* DCE6 ELD audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define SPEAKER_ALLOCATION_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define SPEAKER_ALLOCATION_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define HDMI_CONNECTION (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define DP_CONNECTION (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* max channels minus one. 7 = 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * bit0 = 32 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * bit1 = 44.1 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * bit2 = 48 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * bit3 = 88.2 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * bit4 = 96 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * bit5 = 176.4 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * bit6 = 192 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* VIDEO_LIPSYNC, AUDIO_LIPSYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * 0 = invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * x = legal delay value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * 255 = sync not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) # define HBR_CAPABLE (1 << 0) /* enabled by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) # define PRODUCT_ID(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) # define PORT_ID0(x) (((x) & 0xffffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) # define PORT_ID1(x) (((x) & 0xffffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) # define DESCRIPTION0(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) # define DESCRIPTION1(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) # define DESCRIPTION2(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) # define DESCRIPTION3(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) # define DESCRIPTION4(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) # define DESCRIPTION5(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) # define DESCRIPTION6(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) # define DESCRIPTION7(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) # define DESCRIPTION8(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) # define DESCRIPTION9(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) # define DESCRIPTION10(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) # define DESCRIPTION11(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) # define DESCRIPTION12(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) # define DESCRIPTION13(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) # define DESCRIPTION14(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) # define DESCRIPTION15(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) # define DESCRIPTION16(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) # define DESCRIPTION17(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) # define AUDIO_ENABLED (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define PORT_CONNECTIVITY_MASK (3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define PORT_CONNECTIVITY_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define DC_LB_MEMORY_SPLIT 0x6b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define PRIORITY_A_CNT 0x6b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define PRIORITY_MARK_MASK 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define PRIORITY_OFF (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define PRIORITY_ALWAYS_ON (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define PRIORITY_B_CNT 0x6b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define VLINE_STATUS 0x6bb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) # define VLINE_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) # define VLINE_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) # define VLINE_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) # define VLINE_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) # define VLINE_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define VBLANK_STATUS 0x6bbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) # define VBLANK_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) # define VBLANK_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) # define VBLANK_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) # define VBLANK_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) # define VBLANK_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define INT_MASK 0x6b40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) # define VBLANK_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) # define VLINE_INT_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DISP_INTERRUPT_STATUS 0x60f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) # define LB_D1_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) # define LB_D1_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) # define DC_HPD1_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) # define DC_HPD1_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) # define DACA_AUTODETECT_INTERRUPT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) # define DACB_AUTODETECT_INTERRUPT (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) # define LB_D2_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) # define LB_D2_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) # define DC_HPD2_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) # define DC_HPD2_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) # define DISP_TIMER_INTERRUPT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) # define LB_D3_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) # define LB_D3_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) # define DC_HPD3_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) # define DC_HPD3_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) # define LB_D4_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) # define LB_D4_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) # define DC_HPD4_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) # define DC_HPD4_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) # define LB_D5_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) # define LB_D5_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) # define DC_HPD5_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) # define DC_HPD5_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) # define LB_D6_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) # define LB_D6_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) # define DC_HPD6_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) # define DC_HPD6_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define GRPH_INT_STATUS 0x6858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) # define GRPH_PFLIP_INT_CLEAR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define GRPH_INT_CONTROL 0x685c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) # define GRPH_PFLIP_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) # define GRPH_PFLIP_INT_TYPE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define DAC_AUTODETECT_INT_CONTROL 0x67c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DC_HPD1_INT_STATUS 0x601c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DC_HPD2_INT_STATUS 0x6028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define DC_HPD3_INT_STATUS 0x6034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DC_HPD4_INT_STATUS 0x6040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DC_HPD5_INT_STATUS 0x604c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DC_HPD6_INT_STATUS 0x6058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) # define DC_HPDx_INT_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) # define DC_HPDx_SENSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) # define DC_HPDx_RX_INT_STATUS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define DC_HPD1_INT_CONTROL 0x6020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define DC_HPD2_INT_CONTROL 0x602c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define DC_HPD3_INT_CONTROL 0x6038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DC_HPD4_INT_CONTROL 0x6044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DC_HPD5_INT_CONTROL 0x6050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define DC_HPD6_INT_CONTROL 0x605c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) # define DC_HPDx_INT_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) # define DC_HPDx_INT_POLARITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) # define DC_HPDx_INT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) # define DC_HPDx_RX_INT_ACK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) # define DC_HPDx_RX_INT_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define DC_HPD1_CONTROL 0x6024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define DC_HPD2_CONTROL 0x6030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DC_HPD3_CONTROL 0x603c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DC_HPD4_CONTROL 0x6048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define DC_HPD5_CONTROL 0x6054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define DC_HPD6_CONTROL 0x6060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) # define DC_HPDx_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) # define STUTTER_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define CRTC_STATUS_FRAME_COUNT 0x6e98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Audio clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define DCCG_AUDIO_DTO_SOURCE 0x05ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define DCCG_AUDIO_DTO0_PHASE 0x05b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define DCCG_AUDIO_DTO0_MODULE 0x05b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define DCCG_AUDIO_DTO1_PHASE 0x05c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define DCCG_AUDIO_DTO1_MODULE 0x05c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define DENTIST_DISPCLK_CNTL 0x0490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) # define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) # define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) # define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define AFMT_AUDIO_SRC_CONTROL 0x713c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* AFMT_AUDIO_SRC_SELECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * 0 = stream0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * 1 = stream1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * 2 = stream2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * 3 = stream3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * 4 = stream4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * 5 = stream5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define GRBM_CNTL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define GRBM_READ_TIMEOUT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define GRBM_STATUS2 0x8008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define RLC_RQ_PENDING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define RLC_BUSY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define TC_BUSY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define CMDFIFO_AVAIL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define RING2_RQ_PENDING (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define RING1_RQ_PENDING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define CF_RQ_PENDING (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define PF_RQ_PENDING (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define GDS_DMA_RQ_PENDING (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define GRBM_EE_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define DB_CLEAN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define CB_CLEAN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define TA_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define GDS_BUSY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define VGT_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define IA_BUSY_NO_DMA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define IA_BUSY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SX_BUSY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SPI_BUSY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define BCI_BUSY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SC_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define PA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define DB_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define CP_COHERENCY_BUSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define CP_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define CB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define GUI_ACTIVE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define GRBM_STATUS_SE0 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define GRBM_STATUS_SE1 0x8018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SE_DB_CLEAN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SE_CB_CLEAN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define SE_BCI_BUSY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define SE_VGT_BUSY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define SE_PA_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define SE_TA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define SE_SX_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define SE_SPI_BUSY (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define SE_SC_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define SE_DB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define SE_CB_BUSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define SOFT_RESET_CP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define SOFT_RESET_CB (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define SOFT_RESET_RLC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define SOFT_RESET_DB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define SOFT_RESET_GDS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define SOFT_RESET_PA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define SOFT_RESET_SC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define SOFT_RESET_BCI (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define SOFT_RESET_SPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define SOFT_RESET_SX (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define SOFT_RESET_TC (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define SOFT_RESET_TA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define SOFT_RESET_VGT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define SOFT_RESET_IA (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define GRBM_GFX_INDEX 0x802C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define INSTANCE_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define SH_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define SE_INDEX(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define SH_BROADCAST_WRITES (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define INSTANCE_BROADCAST_WRITES (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define SE_BROADCAST_WRITES (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define GRBM_INT_CNTL 0x8060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) # define RDERR_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) # define GUI_IDLE_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define CP_STRMOUT_CNTL 0x84FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define SCRATCH_REG0 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define SCRATCH_REG1 0x8504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define SCRATCH_REG2 0x8508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define SCRATCH_REG3 0x850C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define SCRATCH_REG4 0x8510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define SCRATCH_REG5 0x8514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define SCRATCH_REG6 0x8518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define SCRATCH_REG7 0x851C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define SCRATCH_UMSK 0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define SCRATCH_ADDR 0x8544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define CP_SEM_WAIT_TIMER 0x85BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define CP_ME_CNTL 0x86D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define CP_CE_HALT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define CP_PFP_HALT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define CP_ME_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define CP_COHER_CNTL2 0x85E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define CP_RB2_RPTR 0x86f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define CP_RB1_RPTR 0x86fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define CP_RB0_RPTR 0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define CP_RB_WPTR_DELAY 0x8704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define CP_QUEUE_THRESHOLDS 0x8760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define ROQ_IB1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define ROQ_IB2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define CP_MEQ_THRESHOLDS 0x8764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define MEQ1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define MEQ2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define CP_PERFMON_CNTL 0x87FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define VGT_VTX_VECT_EJECT_REG 0x88B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define VGT_CACHE_INVALIDATION 0x88C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define CACHE_INVALIDATION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define VC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define TC_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define VC_AND_TC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define AUTO_INVLD_EN(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define NO_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define ES_AUTO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define GS_AUTO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define ES_AND_GS_AUTO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define VGT_ESGS_RING_SIZE 0x88C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define VGT_GSVS_RING_SIZE 0x88CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define VGT_GS_VERTEX_REUSE 0x88D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define VGT_PRIMITIVE_TYPE 0x8958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define VGT_INDEX_TYPE 0x895C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define VGT_NUM_INDICES 0x8970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define VGT_NUM_INSTANCES 0x8974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define VGT_TF_RING_SIZE 0x8988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define VGT_HS_OFFCHIP_PARAM 0x89B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define VGT_TF_MEMORY_BASE 0x89B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define INACTIVE_CUS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define INACTIVE_CUS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define PA_CL_ENHANCE 0x8A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define CLIP_VTX_REORDER_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define NUM_CLIP_SEQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define PA_SC_LINE_STIPPLE_STATE 0x8B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define PA_SC_FIFO_SIZE 0x8BCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define PA_SC_ENHANCE 0x8BF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define SQ_CONFIG 0x8C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define SQC_CACHES 0x8C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define SQ_POWER_THROTTLE 0x8e58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define MIN_POWER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define MIN_POWER_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define MIN_POWER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define MAX_POWER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define MAX_POWER_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define MAX_POWER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define SQ_POWER_THROTTLE2 0x8e5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define MAX_POWER_DELTA(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define MAX_POWER_DELTA_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define MAX_POWER_DELTA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define STI_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define STI_SIZE_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define STI_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define LTI_RATIO(x) ((x) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define LTI_RATIO_MASK (0xf << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define LTI_RATIO_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define SX_DEBUG_1 0x9060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define SPI_STATIC_THREAD_MGMT_1 0x90E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define SPI_STATIC_THREAD_MGMT_2 0x90E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define SPI_STATIC_THREAD_MGMT_3 0x90E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define SPI_PS_MAX_WAVE_ID 0x90EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define SPI_CONFIG_CNTL 0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define SPI_CONFIG_CNTL_1 0x913C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define VTX_DONE_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define CGTS_TCC_DISABLE 0x9148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define CGTS_USER_TCC_DISABLE 0x914C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define TCC_DISABLE_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define TCC_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define CGTS_SM_CTRL_REG 0x9150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define OVERRIDE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define LS_OVERRIDE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define SPI_LB_CU_MASK 0x9354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define TA_CNTL_AUX 0x9508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define TA_CS_BC_BASE_ADDR 0x950C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define CC_RB_BACKEND_DISABLE 0x98F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define GB_ADDR_CONFIG 0x98F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define NUM_PIPES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define NUM_PIPES_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define NUM_PIPES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define PIPE_INTERLEAVE_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define NUM_SHADER_ENGINES(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define NUM_SHADER_ENGINES_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define NUM_SHADER_ENGINES_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define NUM_GPUS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define NUM_GPUS_MASK 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define NUM_GPUS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define MULTI_GPU_TILE_SIZE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define ROW_SIZE(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define ROW_SIZE_MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define ROW_SIZE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define GB_TILE_MODE0 0x9910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) # define MICRO_TILE_MODE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) # define ADDR_SURF_DISPLAY_MICRO_TILING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) # define ADDR_SURF_THIN_MICRO_TILING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) # define ADDR_SURF_DEPTH_MICRO_TILING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) # define ARRAY_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) # define ARRAY_LINEAR_GENERAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) # define ARRAY_LINEAR_ALIGNED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) # define ARRAY_1D_TILED_THIN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) # define ARRAY_2D_TILED_THIN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) # define PIPE_CONFIG(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) # define ADDR_SURF_P2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) # define ADDR_SURF_P4_8x16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) # define ADDR_SURF_P4_16x16 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) # define ADDR_SURF_P4_16x32 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) # define ADDR_SURF_P4_32x32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) # define ADDR_SURF_P8_16x16_8x16 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) # define ADDR_SURF_P8_16x32_8x16 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) # define ADDR_SURF_P8_32x32_8x16 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) # define ADDR_SURF_P8_16x32_16x16 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) # define ADDR_SURF_P8_32x32_16x16 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) # define ADDR_SURF_P8_32x32_16x32 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) # define ADDR_SURF_P8_32x64_32x32 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) # define TILE_SPLIT(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) # define ADDR_SURF_TILE_SPLIT_64B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) # define ADDR_SURF_TILE_SPLIT_128B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) # define ADDR_SURF_TILE_SPLIT_256B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) # define ADDR_SURF_TILE_SPLIT_512B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) # define ADDR_SURF_TILE_SPLIT_1KB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) # define ADDR_SURF_TILE_SPLIT_2KB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) # define ADDR_SURF_TILE_SPLIT_4KB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) # define BANK_WIDTH(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) # define ADDR_SURF_BANK_WIDTH_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) # define ADDR_SURF_BANK_WIDTH_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) # define ADDR_SURF_BANK_WIDTH_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) # define ADDR_SURF_BANK_WIDTH_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) # define BANK_HEIGHT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) # define ADDR_SURF_BANK_HEIGHT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) # define ADDR_SURF_BANK_HEIGHT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) # define ADDR_SURF_BANK_HEIGHT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) # define ADDR_SURF_BANK_HEIGHT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) # define MACRO_TILE_ASPECT(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) # define ADDR_SURF_MACRO_ASPECT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) # define ADDR_SURF_MACRO_ASPECT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) # define ADDR_SURF_MACRO_ASPECT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) # define ADDR_SURF_MACRO_ASPECT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) # define NUM_BANKS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) # define ADDR_SURF_2_BANK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) # define ADDR_SURF_4_BANK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) # define ADDR_SURF_8_BANK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) # define ADDR_SURF_16_BANK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define CB_PERFCOUNTER0_SELECT0 0x9a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define CB_PERFCOUNTER0_SELECT1 0x9a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define CB_PERFCOUNTER1_SELECT0 0x9a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define CB_PERFCOUNTER1_SELECT1 0x9a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define CB_PERFCOUNTER2_SELECT0 0x9a30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define CB_PERFCOUNTER2_SELECT1 0x9a34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define CB_PERFCOUNTER3_SELECT0 0x9a38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define CB_PERFCOUNTER3_SELECT1 0x9a3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define CB_CGTT_SCLK_CTRL 0x9a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define BACKEND_DISABLE_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define BACKEND_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define TCP_CHAN_STEER_LO 0xac0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define TCP_CHAN_STEER_HI 0xac10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define CP_RB0_BASE 0xC100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define CP_RB0_CNTL 0xC104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define RB_BUFSZ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define RB_BLKSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define BUF_SWAP_32BIT (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define RB_NO_UPDATE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define RB_RPTR_WR_ENA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define CP_RB0_RPTR_ADDR 0xC10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define CP_RB0_RPTR_ADDR_HI 0xC110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define CP_RB0_WPTR 0xC114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define CP_PFP_UCODE_ADDR 0xC150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define CP_PFP_UCODE_DATA 0xC154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define CP_ME_RAM_RADDR 0xC158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define CP_ME_RAM_WADDR 0xC15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define CP_ME_RAM_DATA 0xC160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define CP_CE_UCODE_ADDR 0xC168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define CP_CE_UCODE_DATA 0xC16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define CP_RB1_BASE 0xC180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define CP_RB1_CNTL 0xC184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define CP_RB1_RPTR_ADDR 0xC188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define CP_RB1_RPTR_ADDR_HI 0xC18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define CP_RB1_WPTR 0xC190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define CP_RB2_BASE 0xC194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define CP_RB2_CNTL 0xC198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define CP_RB2_RPTR_ADDR 0xC19C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define CP_RB2_RPTR_ADDR_HI 0xC1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define CP_RB2_WPTR 0xC1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define CP_INT_CNTL_RING0 0xC1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define CP_INT_CNTL_RING1 0xC1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define CP_INT_CNTL_RING2 0xC1B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) # define CNTX_BUSY_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) # define CNTX_EMPTY_INT_ENABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) # define TIME_STAMP_INT_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) # define CP_RINGID2_INT_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) # define CP_RINGID1_INT_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) # define CP_RINGID0_INT_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define CP_INT_STATUS_RING0 0xC1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define CP_INT_STATUS_RING1 0xC1B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define CP_INT_STATUS_RING2 0xC1BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) # define WAIT_MEM_SEM_INT_STAT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) # define TIME_STAMP_INT_STAT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) # define CP_RINGID2_INT_STAT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) # define CP_RINGID1_INT_STAT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) # define CP_RINGID0_INT_STAT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define CP_MEM_SLP_CNTL 0xC1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) # define CP_MEM_LS_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define CP_DEBUG 0xC1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define RLC_CNTL 0xC300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) # define RLC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define RLC_RL_BASE 0xC304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define RLC_RL_SIZE 0xC308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define RLC_LB_CNTL 0xC30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) # define LOAD_BALANCE_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define RLC_SAVE_AND_RESTORE_BASE 0xC310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define RLC_LB_CNTR_MAX 0xC314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define RLC_LB_CNTR_INIT 0xC318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define RLC_UCODE_ADDR 0xC32C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define RLC_UCODE_DATA 0xC330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define RLC_MC_CNTL 0xC344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define RLC_UCODE_CNTL 0xC348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define RLC_STAT 0xC34C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) # define RLC_BUSY_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) # define GFX_POWER_STATUS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) # define GFX_CLOCK_STATUS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) # define GFX_LS_STATUS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define RLC_PG_CNTL 0xC35C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) # define GFX_PG_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) # define GFX_PG_SRC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define RLC_CGTT_MGCG_OVERRIDE 0xC400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define RLC_CGCG_CGLS_CTRL 0xC404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) # define CGCG_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) # define CGLS_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define RLC_TTOP_D 0xC414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) # define RLC_PUD(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) # define RLC_PUD_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) # define RLC_PDD(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) # define RLC_PDD_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) # define RLC_TTPD(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) # define RLC_TTPD_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) # define RLC_MSD(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) # define RLC_MSD_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define RLC_LB_INIT_CU_MASK 0xC41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define RLC_PG_AO_CU_MASK 0xC42C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define RLC_MAX_PG_CU 0xC430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) # define MAX_PU_CU(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) # define MAX_PU_CU_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define RLC_AUTO_PG_CTRL 0xC434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) # define AUTO_PG_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) # define GRBM_REG_SGIT(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) # define GRBM_REG_SGIT_MASK (0xffff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define RLC_SERDES_WR_MASTER_MASK_0 0xC454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define RLC_SERDES_WR_MASTER_MASK_1 0xC458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define RLC_SERDES_WR_CTRL 0xC45C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define RLC_SERDES_MASTER_BUSY_0 0xC464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define RLC_SERDES_MASTER_BUSY_1 0xC468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define RLC_GCPM_GENERAL_3 0xC478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define DB_RENDER_CONTROL 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define DB_DEPTH_INFO 0x2803c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define PA_SC_RASTER_CONFIG 0x28350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) # define RASTER_CONFIG_RB_MAP_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) # define RASTER_CONFIG_RB_MAP_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) # define RASTER_CONFIG_RB_MAP_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) # define RASTER_CONFIG_RB_MAP_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define VGT_EVENT_INITIATOR 0x28a90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) # define CACHE_FLUSH_TS (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) # define CACHE_FLUSH (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) # define CS_PARTIAL_FLUSH (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) # define VGT_STREAMOUT_RESET (10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) # define END_OF_PIPE_INCR_DE (11 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) # define END_OF_PIPE_IB_END (12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) # define RST_PIX_CNT (13 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) # define VS_PARTIAL_FLUSH (15 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) # define PS_PARTIAL_FLUSH (16 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) # define ZPASS_DONE (21 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) # define PERFCOUNTER_START (23 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) # define PERFCOUNTER_STOP (24 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) # define PIPELINESTAT_START (25 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) # define PIPELINESTAT_STOP (26 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) # define PERFCOUNTER_SAMPLE (27 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) # define SAMPLE_PIPELINESTAT (30 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) # define SAMPLE_STREAMOUTSTATS (32 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) # define RESET_VTX_CNT (33 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) # define VGT_FLUSH (36 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) # define BOTTOM_OF_PIPE_TS (40 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) # define DB_CACHE_FLUSH_AND_INV (42 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) # define FLUSH_AND_INV_DB_META (44 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) # define FLUSH_AND_INV_CB_META (46 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) # define CS_DONE (47 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) # define PS_DONE (48 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) # define THREAD_TRACE_START (51 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) # define THREAD_TRACE_STOP (52 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) # define THREAD_TRACE_FLUSH (54 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) # define THREAD_TRACE_FINISH (55 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* PIF PHY0 registers idx/data 0x8/0xc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define PB0_PIF_CNTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) # define LS2_EXIT_TIME(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) # define LS2_EXIT_TIME_MASK (0x7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) # define LS2_EXIT_TIME_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define PB0_PIF_PAIRING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) # define MULTI_PIF (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define PB0_PIF_PWRDOWN_0 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) # define PLL_RAMP_UP_TIME_0_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define PB0_PIF_PWRDOWN_1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) # define PLL_RAMP_UP_TIME_1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define PB0_PIF_PWRDOWN_2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) # define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) # define PLL_RAMP_UP_TIME_2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define PB0_PIF_PWRDOWN_3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) # define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) # define PLL_RAMP_UP_TIME_3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* PIF PHY1 registers idx/data 0x10/0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define PB1_PIF_CNTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define PB1_PIF_PAIRING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define PB1_PIF_PWRDOWN_0 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define PB1_PIF_PWRDOWN_1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define PB1_PIF_PWRDOWN_2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define PB1_PIF_PWRDOWN_3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* PCIE registers idx/data 0x30/0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define PCIE_CNTL2 0x1c /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) # define SLV_MEM_LS_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) # define MST_MEM_LS_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) # define REPLAY_MEM_LS_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define PCIE_LC_STATUS1 0x28 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) # define LC_REVERSE_RCVR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) # define LC_REVERSE_XMIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) # define LC_OPERATING_LINK_WIDTH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) # define LC_DETECTED_LINK_WIDTH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define PCIE_P_CNTL 0x40 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) # define P_IGNORE_EDB_ERR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* PCIE PORT registers idx/data 0x38/0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define PCIE_LC_CNTL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) # define LC_L0S_INACTIVITY(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) # define LC_L0S_INACTIVITY_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) # define LC_L0S_INACTIVITY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) # define LC_L1_INACTIVITY(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) # define LC_L1_INACTIVITY_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) # define LC_L1_INACTIVITY_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) # define LC_PMI_TO_L1_DIS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) # define LC_ASPM_TO_L1_DIS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) # define LC_LINK_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) # define LC_LINK_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) # define LC_LINK_WIDTH_X0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) # define LC_LINK_WIDTH_X1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) # define LC_LINK_WIDTH_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) # define LC_LINK_WIDTH_X4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) # define LC_LINK_WIDTH_X8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) # define LC_LINK_WIDTH_X16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) # define LC_LINK_WIDTH_RD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) # define LC_LINK_WIDTH_RD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) # define LC_RECONFIG_NOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) # define LC_RENEGOTIATION_SUPPORT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) # define LC_RENEGOTIATE_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) # define LC_SHORT_RECONFIG_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) # define LC_UPCONFIGURE_SUPPORT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) # define LC_UPCONFIGURE_DIS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) # define LC_DYN_LANES_PWR_STATE_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) # define LC_XMIT_N_FTS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) # define LC_XMIT_N_FTS_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) # define LC_XMIT_N_FTS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) # define LC_N_FTS_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) # define LC_GEN3_EN_STRAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) # define LC_CURRENT_DATA_RATE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define PCIE_LC_CNTL2 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) # define LC_GO_TO_RECOVERY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) # define LC_REDO_EQ (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) # define LC_SET_QUIESCE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * UVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define UVD_UDEC_ADDR_CONFIG 0xEF4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define UVD_NO_OP 0xEFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define UVD_RBC_RB_RPTR 0xF690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define UVD_RBC_RB_WPTR 0xF694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define UVD_STATUS 0xf6bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define UVD_CGC_CTRL 0xF4B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) # define DCM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) # define CG_DT(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) # define CG_DT_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) # define CLK_OD(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) # define CLK_OD_MASK (0x1f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* UVD CTX indirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define UVD_CGC_MEM_CTRL 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define UVD_CGC_CTRL2 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) # define DYN_OR_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) # define DYN_RR_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) # define G_DIV_ID(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) # define G_DIV_ID_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * PM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) (((reg) >> 2) & 0xFFFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) (((op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* Packet 3 types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define PACKET3_SET_BASE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define PACKET3_BASE_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define GDS_PARTITION_BASE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define CE_PARTITION_BASE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define PACKET3_CLEAR_STATE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define PACKET3_INDEX_BUFFER_SIZE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define PACKET3_DISPATCH_DIRECT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define PACKET3_DISPATCH_INDIRECT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define PACKET3_ALLOC_GDS 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define PACKET3_WRITE_GDS_RAM 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define PACKET3_ATOMIC_GDS 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define PACKET3_ATOMIC 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define PACKET3_OCCLUSION_QUERY 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define PACKET3_SET_PREDICATION 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define PACKET3_REG_RMW 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define PACKET3_COND_EXEC 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define PACKET3_PRED_EXEC 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define PACKET3_DRAW_INDIRECT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define PACKET3_DRAW_INDEX_INDIRECT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define PACKET3_INDEX_BASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define PACKET3_DRAW_INDEX_2 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define PACKET3_CONTEXT_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define PACKET3_INDEX_TYPE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define PACKET3_DRAW_INDEX_AUTO 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define PACKET3_DRAW_INDEX_IMMD 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define PACKET3_NUM_INSTANCES 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define PACKET3_INDIRECT_BUFFER_CONST 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define PACKET3_INDIRECT_BUFFER 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define PACKET3_WRITE_DATA 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define WRITE_DATA_DST_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* 0 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * 1 - memory (sync - via GRBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * 2 - tc/l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * 3 - gds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * 4 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * 5 - memory (async - direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define WR_ONE_ADDR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define WR_CONFIRM (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* 0 - me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * 1 - pfp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * 2 - ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define PACKET3_MEM_SEMAPHORE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define PACKET3_MPEG_INDEX 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define PACKET3_COPY_DW 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define PACKET3_WAIT_REG_MEM 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* 0 - always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * 1 - <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * 2 - <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * 3 - ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * 4 - !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * 5 - >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * 6 - >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* 0 - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * 1 - mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* 0 - me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * 1 - pfp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define PACKET3_MEM_WRITE 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define PACKET3_COPY_DATA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define PACKET3_CP_DMA 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* 1. header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * 2. SRC_ADDR_LO or DATA [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * SRC_ADDR_HI [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * 4. DST_ADDR_LO [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * 5. DST_ADDR_HI [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* 0 - DST_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * 1 - GDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* 0 - ME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * 1 - PFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* 0 - SRC_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * 1 - GDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * 2 - DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) # define PACKET3_CP_DMA_DIS_WC (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define PACKET3_PFP_SYNC_ME 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define PACKET3_SURFACE_SYNC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) # define PACKET3_DEST_BASE_0_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) # define PACKET3_DEST_BASE_1_ENA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) # define PACKET3_DEST_BASE_2_ENA (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) # define PACKET3_DEST_BASE_3_ENA (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) # define PACKET3_TCL1_ACTION_ENA (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) # define PACKET3_TC_ACTION_ENA (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) # define PACKET3_CB_ACTION_ENA (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) # define PACKET3_DB_ACTION_ENA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define PACKET3_ME_INITIALIZE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define PACKET3_COND_WRITE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define PACKET3_EVENT_WRITE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define EVENT_TYPE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define EVENT_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* 0 - any non-TS event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * 1 - ZPASS_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * 2 - SAMPLE_PIPELINESTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * 3 - SAMPLE_STREAMOUTSTAT*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * 4 - *S_PARTIAL_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * 5 - EOP events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * 6 - EOS events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define INV_L2 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* INV TC L2 cache when EVENT_INDEX = 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define PACKET3_EVENT_WRITE_EOP 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define DATA_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* 0 - discard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * 1 - send low 32bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * 2 - send 64bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * 3 - send 64bit counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define INT_SEL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * 1 - interrupt only (DATA_SEL = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * 2 - interrupt when data write is confirmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define PACKET3_EVENT_WRITE_EOS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define PACKET3_PREAMBLE_CNTL 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define PACKET3_ONE_REG_WRITE 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define PACKET3_LOAD_CONFIG_REG 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define PACKET3_LOAD_CONTEXT_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define PACKET3_LOAD_SH_REG 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define PACKET3_SET_CONFIG_REG 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define PACKET3_SET_CONFIG_REG_START 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define PACKET3_SET_CONFIG_REG_END 0x0000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define PACKET3_SET_CONTEXT_REG 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define PACKET3_SET_CONTEXT_REG_START 0x00028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define PACKET3_SET_CONTEXT_REG_END 0x00029000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define PACKET3_SET_RESOURCE_INDIRECT 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define PACKET3_SET_SH_REG 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define PACKET3_SET_SH_REG_START 0x0000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define PACKET3_SET_SH_REG_END 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define PACKET3_SET_SH_REG_OFFSET 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define PACKET3_ME_WRITE 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define PACKET3_SCRATCH_RAM_WRITE 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define PACKET3_SCRATCH_RAM_READ 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define PACKET3_CE_WRITE 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define PACKET3_LOAD_CONST_RAM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define PACKET3_WRITE_CONST_RAM 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define PACKET3_DUMP_CONST_RAM 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define PACKET3_INCREMENT_CE_COUNTER 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define PACKET3_INCREMENT_DE_COUNTER 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define PACKET3_WAIT_ON_CE_COUNTER 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define PACKET3_WAIT_ON_DE_COUNTER 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define PACKET3_SET_CE_DE_COUNTERS 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define PACKET3_SWITCH_BUFFER 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define DMA_RB_CNTL 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) # define DMA_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define DMA_RB_BASE 0xd004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define DMA_RB_RPTR 0xd008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define DMA_RB_WPTR 0xd00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define DMA_RB_RPTR_ADDR_HI 0xd01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define DMA_RB_RPTR_ADDR_LO 0xd020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define DMA_IB_CNTL 0xd024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) # define DMA_IB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) # define DMA_IB_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define DMA_IB_RPTR 0xd028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define DMA_CNTL 0xd02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) # define TRAP_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) # define SEM_WAIT_INT_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) # define DATA_SWAP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) # define FENCE_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) # define CTXEMPTY_INT_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define DMA_STATUS_REG 0xd034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) # define DMA_IDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define DMA_TILING_CONFIG 0xd0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define DMA_POWER_CNTL 0xd0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) # define MEM_POWER_OVERRIDE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define DMA_CLK_CTRL 0xd0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define DMA_PG 0xd0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) # define PG_CNTL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define DMA_PGFSM_CONFIG 0xd0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define DMA_PGFSM_WRITE 0xd0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) (((b) & 0x1) << 26) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) (((t) & 0x1) << 23) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) (((s) & 0x1) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) (((vmid) & 0xF) << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) (1 << 26) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) (1 << 21) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* async DMA Packet types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define DMA_PACKET_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define DMA_PACKET_COPY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define DMA_PACKET_INDIRECT_BUFFER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define DMA_PACKET_SEMAPHORE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define DMA_PACKET_FENCE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define DMA_PACKET_TRAP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define DMA_PACKET_SRBM_WRITE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define DMA_PACKET_CONSTANT_FILL 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define DMA_PACKET_POLL_REG_MEM 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define DMA_PACKET_NOP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define VCE_STATUS 0x20004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define VCE_VCPU_CNTL 0x20014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define VCE_CLK_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define VCE_VCPU_CACHE_OFFSET0 0x20024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define VCE_VCPU_CACHE_SIZE0 0x20028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define VCE_VCPU_CACHE_OFFSET1 0x2002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define VCE_VCPU_CACHE_SIZE1 0x20030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define VCE_VCPU_CACHE_OFFSET2 0x20034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define VCE_VCPU_CACHE_SIZE2 0x20038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define VCE_VCPU_SCRATCH7 0x200dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define VCE_SOFT_RESET 0x20120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define VCE_ECPU_SOFT_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define VCE_FME_SOFT_RESET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define VCE_RB_BASE_LO2 0x2016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define VCE_RB_BASE_HI2 0x20170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define VCE_RB_SIZE2 0x20174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define VCE_RB_RPTR2 0x20178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define VCE_RB_WPTR2 0x2017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define VCE_RB_BASE_LO 0x20180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define VCE_RB_BASE_HI 0x20184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define VCE_RB_SIZE 0x20188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define VCE_RB_RPTR 0x2018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define VCE_RB_WPTR 0x20190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define VCE_CLOCK_GATING_A 0x202f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) # define CGC_DYN_CLOCK_MODE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define VCE_CLOCK_GATING_B 0x202fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define VCE_UENC_CLOCK_GATING 0x205bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define VCE_UENC_REG_CLOCK_GATING 0x205c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define VCE_FW_REG_STATUS 0x20e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) # define VCE_FW_REG_STATUS_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) # define VCE_FW_REG_STATUS_PASS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) # define VCE_FW_REG_STATUS_DONE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define VCE_LMI_FW_START_KEYSEL 0x20e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define VCE_LMI_CTRL2 0x20e74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define VCE_LMI_CTRL 0x20e98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define VCE_LMI_VM_CTRL 0x20ea0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define VCE_LMI_SWAP_CNTL 0x20eb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define VCE_LMI_SWAP_CNTL1 0x20eb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define VCE_LMI_CACHE_CTRL 0x20ef4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define VCE_CMD_NO_OP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define VCE_CMD_END 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define VCE_CMD_IB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define VCE_CMD_FENCE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define VCE_CMD_TRAP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define VCE_CMD_IB_AUTO 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define VCE_CMD_SEMAPHORE 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* discrete vce clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define CG_VCEPLL_FUNC_CNTL 0xc0030600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) # define VCEPLL_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) # define VCEPLL_SLEEP_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) # define VCEPLL_BYPASS_EN_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) # define VCEPLL_CTLREQ_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) # define VCEPLL_VCO_MODE_MASK 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) # define VCEPLL_REF_DIV_MASK 0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) # define VCEPLL_CTLACK_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) # define VCEPLL_CTLACK2_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) # define VCEPLL_PDIV_A(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) # define VCEPLL_PDIV_A_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) # define VCEPLL_PDIV_B(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) # define VCEPLL_PDIV_B_MASK 0x00007F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) # define EVCLK_SRC_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) # define EVCLK_SRC_SEL_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) # define ECCLK_SRC_SEL(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) # define ECCLK_SRC_SEL_MASK 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) # define VCEPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) # define VCEPLL_FB_DIV_MASK 0x01FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) # define VCEPLL_SSEN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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