^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2009 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2009 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef RV770_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RV770_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R7XX_MAX_SH_GPRS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R7XX_MAX_TEMP_GPRS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R7XX_MAX_SH_THREADS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R7XX_MAX_SH_STACK_ENTRIES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R7XX_MAX_BACKENDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R7XX_MAX_BACKENDS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R7XX_MAX_SIMDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R7XX_MAX_SIMDS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R7XX_MAX_PIPES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R7XX_MAX_PIPES_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* discrete uvd clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CG_UPLL_FUNC_CNTL 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define UPLL_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define UPLL_SLEEP_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define UPLL_BYPASS_EN_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define UPLL_CTLREQ_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # define UPLL_REF_DIV(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define UPLL_REF_DIV_MASK 0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define UPLL_CTLACK_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) # define UPLL_CTLACK2_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CG_UPLL_FUNC_CNTL_2 0x71c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define UPLL_SW_HILEN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define UPLL_SW_LOLEN(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define UPLL_SW_HILEN2(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define UPLL_SW_LOLEN2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define UPLL_SW_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define VCLK_SRC_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) # define VCLK_SRC_SEL_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define DCLK_SRC_SEL(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define DCLK_SRC_SEL_MASK 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CG_UPLL_FUNC_CNTL_3 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define UPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define UPLL_FB_DIV_MASK 0x01FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* pm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SMC_SRAM_ADDR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SMC_SRAM_AUTO_INC_DIS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMC_SRAM_DATA 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SMC_IO 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SMC_RST_N (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SMC_STOP_MODE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SMC_CLK_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMC_MSG 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HOST_SMC_MSG(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HOST_SMC_MSG_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HOST_SMC_MSG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HOST_SMC_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HOST_SMC_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HOST_SMC_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SMC_HOST_MSG(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SMC_HOST_MSG_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SMC_HOST_MSG_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SMC_HOST_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SMC_HOST_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SMC_HOST_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SMC_ISR_FFD8_FFDB 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPLL_DIVEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPLL_HILEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPLL_HILEN_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPLL_LOLEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPLL_LOLEN_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CG_SPLL_FUNC_CNTL_2 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCLK_MUX_UPDATE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CG_SPLL_FUNC_CNTL_3 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CG_SPLL_STATUS 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPLL_CHG_STATUS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPLL_CNTL_MODE 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPLL_DIV_SYNC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MPLL_CNTL_MODE 0x61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define MPLL_MCLK_SEL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define RV730_MPLL_MCLK_SEL (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MPLL_AD_FUNC_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLKF(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKF_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLKR(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLKR_MASK (0x1f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLKFRAC(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLKFRAC_MASK (0x1f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define YCLK_POST_DIV(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define YCLK_POST_DIV_MASK (3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IBIAS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IBIAS_MASK (0x3ff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PDNB (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MPLL_AD_FUNC_CNTL_2 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BYPASS (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BIAS_GEN_PDNB (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RESET_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VCO_MODE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MPLL_DQ_FUNC_CNTL 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MPLL_DQ_FUNC_CNTL_2 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GENERAL_PWRMGT 0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define ENABLE_GEN2PCIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define ENABLE_GEN2XSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define SW_SMIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define SW_SMIO_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define BACKBIAS_PAD_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define BACKBIAS_VALUE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define AC_DC_SW (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CG_TPC 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SCLK_PWRMGT_CNTL 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define SCLK_LOW_D1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define FIR_RESET (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define FIR_FORCE_TREND_SEL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define FIR_TREND_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define DYN_GFX_CLK_OFF_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) # define GFX_CLK_FORCE_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define GFX_CLK_REQUEST_OFF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define GFX_CLK_FORCE_OFF (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCLK_PWRMGT_CNTL 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) # define DLL_SPEED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define DLL_SPEED_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define MPLL_PWRMGT_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define MRDCKA0_SLEEP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) # define MRDCKA1_SLEEP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) # define MRDCKB0_SLEEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define MRDCKB1_SLEEP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define MRDCKC0_SLEEP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define MRDCKC1_SLEEP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define MRDCKD0_SLEEP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) # define MRDCKD1_SLEEP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) # define MRDCKA0_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) # define MRDCKA1_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define MRDCKB0_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define MRDCKB1_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define MRDCKC0_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # define MRDCKC1_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) # define MRDCKD0_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) # define MRDCKD1_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DLL_CNTL 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) # define MRDCKA0_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) # define MRDCKA1_BYPASS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define MRDCKB0_BYPASS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define MRDCKB1_BYPASS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) # define MRDCKC0_BYPASS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) # define MRDCKC1_BYPASS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) # define MRDCKD0_BYPASS (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) # define MRDCKD1_BYPASS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MPLL_TIME 0x654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # define MPLL_LOCK_TIME(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define MPLL_LOCK_TIME_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) # define MPLL_RESET_TIME(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define MPLL_RESET_TIME_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CG_CLKPIN_CNTL 0x660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) # define MUX_TCLK_TO_XCLK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) # define XTALIN_DIVIDE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) # define CURRENT_PROFILE_INDEX_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) # define CURRENT_PROFILE_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define S0_VID_LOWER_SMIO_CNTL 0x678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define S1_VID_LOWER_SMIO_CNTL 0x67c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define S2_VID_LOWER_SMIO_CNTL 0x680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define S3_VID_LOWER_SMIO_CNTL 0x684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CG_FTV 0x690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CG_FFCT_0 0x694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) # define UTC_0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) # define UTC_0_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) # define DTC_0(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) # define DTC_0_MASK (0x3ff << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CG_BSP 0x6d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define BSP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define BSP_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) # define BSU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) # define BSU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CG_AT 0x6d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) # define CG_R(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define CG_R_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define CG_L(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define CG_L_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CG_GIT 0x6d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define CG_GICST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define CG_GICST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define CG_GIPOT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) # define CG_GIPOT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CG_SSP 0x6e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) # define SST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) # define SST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) # define SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) # define SSTU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CG_DISPLAY_GAP_CNTL 0x714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define DISP1_GAP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) # define DISP1_GAP_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) # define DISP2_GAP(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) # define DISP2_GAP_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) # define VBI_TIMER_COUNT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) # define VBI_TIMER_UNIT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # define VBI_TIMER_UNIT_MASK (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define DISP1_GAP_MCHG(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) # define DISP1_GAP_MCHG_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) # define DISP2_GAP_MCHG(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) # define DISP2_GAP_MCHG_MASK (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CG_SPLL_SPREAD_SPECTRUM 0x790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLKS(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLKS_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLKV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLKV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CG_MPLL_SPREAD_SPECTRUM 0x798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CG_UPLL_SPREAD_SPECTRUM 0x79c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) # define SSEN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CG_CGTT_LOCAL_0 0x7d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CG_CGTT_LOCAL_1 0x7d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BIOS_SCRATCH_4 0x1734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MC_ARB_SQM_RATIO 0x2770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define STATE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define STATE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define STATE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define STATE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define STATE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define STATE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define STATE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MC_ARB_RFSH_RATE 0x27b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define POWERMODE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define POWERMODE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define POWERMODE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define POWERMODE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define POWERMODE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define POWERMODE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define POWERMODE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define POWERMODE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CGTS_SM_CTRL_REG 0x9150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CB_COLOR0_BASE 0x28040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CB_COLOR1_BASE 0x28044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CB_COLOR2_BASE 0x28048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CB_COLOR3_BASE 0x2804C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CB_COLOR4_BASE 0x28050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CB_COLOR5_BASE 0x28054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CB_COLOR6_BASE 0x28058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CB_COLOR7_BASE 0x2805C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CB_COLOR7_FRAG 0x280FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CC_GC_SHADER_PIPE_CONFIG 0x8950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CC_RB_BACKEND_DISABLE 0x98F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CGTS_SYS_TCC_DISABLE 0x3F90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CGTS_TCC_DISABLE 0x9148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CGTS_USER_TCC_DISABLE 0x914C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CONFIG_MEMSIZE 0x5428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CP_ME_CNTL 0x86D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CP_ME_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CP_PFP_HALT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CP_ME_RAM_DATA 0xC160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CP_ME_RAM_RADDR 0xC158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CP_ME_RAM_WADDR 0xC15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CP_MEQ_THRESHOLDS 0x8764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define STQ_SPLIT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CP_PERFMON_CNTL 0x87FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CP_PFP_UCODE_ADDR 0xC150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CP_PFP_UCODE_DATA 0xC154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CP_QUEUE_THRESHOLDS 0x8760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ROQ_IB1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ROQ_IB2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CP_RB_CNTL 0xC104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define RB_BUFSZ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define RB_BLKSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RB_NO_UPDATE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RB_RPTR_WR_ENA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BUF_SWAP_32BIT (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CP_RB_RPTR 0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CP_RB_RPTR_ADDR 0xC10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CP_RB_RPTR_ADDR_HI 0xC110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CP_RB_RPTR_WR 0xC108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CP_RB_WPTR 0xC114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CP_RB_WPTR_ADDR 0xC118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CP_RB_WPTR_ADDR_HI 0xC11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CP_RB_WPTR_DELAY 0x8704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CP_SEM_WAIT_TIMER 0x85BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DB_DEBUG3 0x98B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DB_CLK_OFF_DELAY(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DB_DEBUG4 0x9B8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DCP_TILING_CONFIG 0x6CA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PIPE_TILING(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BANK_TILING(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define GROUP_SIZE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ROW_TILING(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BANK_SWAPS(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SAMPLE_SPLIT(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BACKEND_MAP(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define GB_TILING_CONFIG 0x98F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PIPE_TILING__SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PIPE_TILING__MASK 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DMA_TILING_CONFIG 0x3ec8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DMA_TILING_CONFIG2 0xd0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* RV730 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define UVD_UDEC_TILING_CONFIG 0xef40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define UVD_UDEC_DB_TILING_CONFIG 0xef44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define UVD_UDEC_DBW_TILING_CONFIG 0xef48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define UVD_NO_OP 0xeffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define GC_USER_SHADER_PIPE_CONFIG 0x8954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define INACTIVE_QD_PIPES(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define INACTIVE_QD_PIPES_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define INACTIVE_QD_PIPES_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define INACTIVE_SIMDS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define INACTIVE_SIMDS_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define GRBM_CNTL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define GRBM_READ_TIMEOUT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SOFT_RESET_CP (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CMDFIFO_AVAIL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define GUI_ACTIVE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define GRBM_STATUS2 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CG_THERMAL_CTRL 0x72C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DPM_EVENT_SRC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DPM_EVENT_SRC_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DIG_THERM_DPM(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DIG_THERM_DPM_MASK 0x003FC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DIG_THERM_DPM_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CG_THERMAL_INT 0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DIG_THERM_INTH(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DIG_THERM_INTH_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DIG_THERM_INTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DIG_THERM_INTL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DIG_THERM_INTL_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DIG_THERM_INTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define THERM_INT_MASK_HIGH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define THERM_INT_MASK_LOW (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CG_MULT_THERMAL_STATUS 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define ASIC_T(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define ASIC_T_MASK 0x3FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define ASIC_T_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define HDP_HOST_PATH_CNTL 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HDP_NONSURFACE_BASE 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define HDP_NONSURFACE_INFO 0x2C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HDP_NONSURFACE_SIZE 0x2C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define HDP_TILING_CONFIG 0x2F3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define HDP_DEBUG1 0x2F34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MC_SHARED_CHMAP 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define NOOFCHAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define NOOFCHAN_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MC_SHARED_CHREMAP 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MC_ARB_RAMCFG 0x2760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define NOOFBANK_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define NOOFRANK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define NOOFRANK_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define NOOFROWS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define NOOFROWS_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define NOOFCOLS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define NOOFCOLS_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CHANSIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CHANSIZE_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define BURSTLENGTH_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define BURSTLENGTH_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CHANSIZE_OVERRIDE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MC_VM_AGP_TOP 0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MC_VM_AGP_BOT 0x202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MC_VM_AGP_BASE 0x2030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MC_VM_FB_LOCATION 0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MC_VM_MB_L1_TLB0_CNTL 0x2234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MC_VM_MB_L1_TLB1_CNTL 0x2238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MC_VM_MB_L1_TLB2_CNTL 0x223C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MC_VM_MB_L1_TLB3_CNTL 0x2240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define ENABLE_L1_TLB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MC_VM_MD_L1_TLB0_CNTL 0x2654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define MC_VM_MD_L1_TLB1_CNTL 0x2658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define MC_VM_MD_L1_TLB2_CNTL 0x265C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define MC_VM_MD_L1_TLB3_CNTL 0x2698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PA_CL_ENHANCE 0x8A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CLIP_VTX_REORDER_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define NUM_CLIP_SEQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PA_SC_AA_CONFIG 0x28C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PA_SC_CLIPRECT_RULE 0x2820C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PA_SC_EDGERULE 0x28230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define PA_SC_FIFO_SIZE 0x8BCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define PA_SC_LINE_STIPPLE 0x28A0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define PA_SC_LINE_STIPPLE_STATE 0x8B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define PA_SC_MODE_CNTL 0x28A4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PA_SC_MULTI_CHIP_CNTL 0x8B20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SCRATCH_REG0 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SCRATCH_REG1 0x8504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SCRATCH_REG2 0x8508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SCRATCH_REG3 0x850C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SCRATCH_REG4 0x8510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SCRATCH_REG5 0x8514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SCRATCH_REG6 0x8518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SCRATCH_REG7 0x851C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SCRATCH_UMSK 0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SCRATCH_ADDR 0x8544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SMX_SAR_CTL0 0xA008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SMX_DC_CTL0 0xA020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define USE_HASH_FUNCTION (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CACHE_DEPTH(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define FLUSH_ALL_ON_EVENT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define STALL_ON_EVENT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SMX_EVENT_CTL 0xA02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define ES_FLUSH_CTL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define GS_FLUSH_CTL(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define ACK_FLUSH_CTL(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SYNC_FLUSH_CTL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SPI_CONFIG_CNTL 0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define GPR_WRITE_PRIORITY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DISABLE_INTERP_1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SPI_CONFIG_CNTL_1 0x913C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define VTX_DONE_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SPI_INPUT_Z 0x286D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SPI_PS_IN_CONTROL_0 0x286CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define NUM_INTERP(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define POSITION_ENA (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define POSITION_CENTROID (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define POSITION_ADDR(x) ((x)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PARAM_GEN(x) ((x)<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PARAM_GEN_ADDR(x) ((x)<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PERSP_GRADIENT_ENA (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define LINEAR_GRADIENT_ENA (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define POSITION_SAMPLE (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define BARYC_AT_SAMPLE_ENA (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SQ_CONFIG 0x8C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define VC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define EXPORT_SRC_C (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DX9_CONSTS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define ALU_INST_PREFER_VECTOR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define DX10_CLAMP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define CLAUSE_SEQ_PRIO(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PS_PRIO(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define VS_PRIO(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define GS_PRIO(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SIMDA_RING0(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SIMDA_RING1(x) ((x)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SIMDB_RING0(x) ((x)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SIMDB_RING1(x) ((x)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define ES_PRIO(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define NUM_PS_GPRS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define NUM_VS_GPRS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DYN_GPR_ENABLE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define NUM_GS_GPRS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define NUM_ES_GPRS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SQ_MS_FIFO_SIZES 0x8CF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define CACHE_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define FETCH_FIFO_HIWATER(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define DONE_FIFO_HIWATER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SQ_STACK_RESOURCE_MGMT_1 0x8C10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SQ_STACK_RESOURCE_MGMT_2 0x8C14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SQ_THREAD_RESOURCE_MGMT 0x8C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define NUM_PS_THREADS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define NUM_VS_THREADS(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define NUM_GS_THREADS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define NUM_ES_THREADS(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SX_DEBUG_1 0x9058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SX_EXPORT_BUFFER_SIZES 0x900C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define COLOR_BUFFER_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define POSITION_BUFFER_SIZE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SMX_BUFFER_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SX_MISC 0x28350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define TA_CNTL_AUX 0x9508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define DISABLE_CUBE_WRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define DISABLE_CUBE_ANISO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SYNC_GRADIENT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SYNC_WALKER (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SYNC_ALIGNER (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define BILINEAR_PRECISION_6_BIT (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define BILINEAR_PRECISION_8_BIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define TCP_CNTL 0x9610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define TCP_CHAN_STEER 0x9614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define VC_ENHANCE 0x9714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define VGT_CACHE_INVALIDATION 0x88C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define CACHE_INVALIDATION(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define VC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define TC_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define VC_AND_TC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define AUTO_INVLD_EN(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define NO_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ES_AUTO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define GS_AUTO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ES_AND_GS_AUTO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define VGT_ES_PER_GS 0x88CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define VGT_GS_PER_ES 0x88C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define VGT_GS_PER_VS 0x88E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define VGT_GS_VERTEX_REUSE 0x88D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define VGT_NUM_INSTANCES 0x8974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define VGT_OUT_DEALLOC_CNTL 0x28C5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define DEALLOC_DIST_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define VGT_STRMOUT_EN 0x28AB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define VTX_REUSE_DEPTH_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define VM_CONTEXT0_CNTL 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define ENABLE_CONTEXT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define VM_L2_CNTL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ENABLE_L2_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define VM_L2_CNTL2 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define INVALIDATE_ALL_L1_TLBS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define INVALIDATE_L2_CACHE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define VM_L2_CNTL3 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define BANK_SELECT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define CACHE_UPDATE_MODE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define VM_L2_STATUS 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define L2_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define WAIT_UNTIL 0x8040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* async DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define DMA_RB_RPTR 0xd008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DMA_RB_WPTR 0xd00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* async DMA packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) (((t) & 0x1) << 23) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) (((s) & 0x1) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (((n) & 0xFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* async DMA Packet types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DMA_PACKET_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define DMA_PACKET_COPY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DMA_PACKET_INDIRECT_BUFFER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define DMA_PACKET_SEMAPHORE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DMA_PACKET_FENCE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define DMA_PACKET_TRAP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define DMA_PACKET_CONSTANT_FILL 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DMA_PACKET_NOP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SRBM_STATUS 0x0E50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* DCE 3.2 HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define HDMI_CONTROL 0x7400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) # define HDMI_KEEPOUT_MODE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) # define HDMI_ERROR_ACK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) # define HDMI_ERROR_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define HDMI_STATUS 0x7404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) # define HDMI_ACTIVE_AVMUTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) # define HDMI_AUDIO_PACKET_ERROR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) # define HDMI_VBI_PACKET_ERROR (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define HDMI_AUDIO_PACKET_CONTROL 0x7408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define HDMI_ACR_PACKET_CONTROL 0x740c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) # define HDMI_ACR_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) # define HDMI_ACR_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) # define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) # define HDMI_ACR_HW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) # define HDMI_ACR_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) # define HDMI_ACR_44 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) # define HDMI_ACR_48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) # define HDMI_ACR_AUTO_SEND (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define HDMI_VBI_PACKET_CONTROL 0x7410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) # define HDMI_NULL_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) # define HDMI_GC_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define HDMI_INFOFRAME_CONTROL0 0x7414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) # define HDMI_AVI_INFO_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) # define HDMI_AVI_INFO_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) # define HDMI_AUDIO_INFO_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) # define HDMI_AUDIO_INFO_CONT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) # define HDMI_MPEG_INFO_SEND (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) # define HDMI_MPEG_INFO_CONT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define HDMI_INFOFRAME_CONTROL1 0x7418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define HDMI_GENERIC_PACKET_CONTROL 0x741c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) # define HDMI_GENERIC0_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) # define HDMI_GENERIC0_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) # define HDMI_GENERIC1_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) # define HDMI_GENERIC1_CONT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define HDMI_GC 0x7428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) # define HDMI_GC_AVMUTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define AFMT_AUDIO_PACKET_CONTROL2 0x742c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) # define AFMT_60958_CS_SOURCE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define AFMT_AVI_INFO0 0x7454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) # define AFMT_AVI_INFO_Y_RGB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) # define AFMT_AVI_INFO_Y_YCBCR422 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) # define AFMT_AVI_INFO_Y_YCBCR444 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define AFMT_AVI_INFO1 0x7458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define AFMT_AVI_INFO2 0x745c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define AFMT_AVI_INFO3 0x7460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define AFMT_MPEG_INFO0 0x7464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define AFMT_MPEG_INFO1 0x7468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define AFMT_GENERIC0_HDR 0x746c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define AFMT_GENERIC0_0 0x7470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define AFMT_GENERIC0_1 0x7474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define AFMT_GENERIC0_2 0x7478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define AFMT_GENERIC0_3 0x747c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define AFMT_GENERIC0_4 0x7480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define AFMT_GENERIC0_5 0x7484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define AFMT_GENERIC0_6 0x7488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define AFMT_GENERIC1_HDR 0x748c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define AFMT_GENERIC1_0 0x7490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define AFMT_GENERIC1_1 0x7494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define AFMT_GENERIC1_2 0x7498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define AFMT_GENERIC1_3 0x749c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define AFMT_GENERIC1_4 0x74a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define AFMT_GENERIC1_5 0x74a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define AFMT_GENERIC1_6 0x74a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define HDMI_ACR_32_0 0x74ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define HDMI_ACR_32_1 0x74b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define HDMI_ACR_44_0 0x74b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define HDMI_ACR_44_1 0x74b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define HDMI_ACR_48_0 0x74bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define HDMI_ACR_48_1 0x74c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define HDMI_ACR_STATUS_0 0x74c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define HDMI_ACR_STATUS_1 0x74c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define AFMT_AUDIO_INFO0 0x74cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AFMT_AUDIO_INFO1 0x74d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define AFMT_60958_0 0x74d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) # define AFMT_60958_CS_A(x) (((x) & 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) # define AFMT_60958_CS_B(x) (((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) # define AFMT_60958_CS_C(x) (((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) # define AFMT_60958_CS_D(x) (((x) & 3) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define AFMT_60958_1 0x74d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define AFMT_AUDIO_CRC_CONTROL 0x74dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) # define AFMT_AUDIO_CRC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define AFMT_RAMP_CONTROL0 0x74e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) # define AFMT_RAMP_DATA_SIGN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define AFMT_RAMP_CONTROL1 0x74e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define AFMT_RAMP_CONTROL2 0x74e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define AFMT_RAMP_CONTROL3 0x74ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define AFMT_60958_2 0x74f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define AFMT_STATUS 0x7600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) # define AFMT_AUDIO_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define AFMT_AUDIO_PACKET_CONTROL 0x7604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) # define AFMT_AUDIO_TEST_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) # define AFMT_60958_CS_UPDATE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define AFMT_VBI_PACKET_CONTROL 0x7608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) # define AFMT_GENERIC0_UPDATE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define AFMT_INFOFRAME_CONTROL0 0x760c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) # define AFMT_AUDIO_INFO_UPDATE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) # define AFMT_MPEG_INFO_UPDATE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define AFMT_GENERIC0_7 0x7610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* second instance starts at 0x7800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define HDMI_OFFSET0 (0x7400 - 0x7400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define HDMI_OFFSET1 (0x7800 - 0x7400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* DCE3.2 ELD audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* max channels minus one. 7 = 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * bit0 = 32 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * bit1 = 44.1 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * bit2 = 48 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * bit3 = 88.2 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * bit4 = 96 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * bit5 = 176.4 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * bit6 = 192 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define AZ_HOT_PLUG_CONTROL 0x7300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) # define AZ_FORCE_CODEC_WAKE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) # define CODEC_HOT_PLUG_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) # define PIN0_AUDIO_ENABLED (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) # define PIN1_AUDIO_ENABLED (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) # define PIN2_AUDIO_ENABLED (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) # define PIN3_AUDIO_ENABLED (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) # define AUDIO_ENABLED (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* PCIE indirect regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define PCIE_P_CNTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) # define P_PLL_PWRDN_IN_L1L23 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) # define P_PLL_BUF_PDNB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) # define P_PLL_PDNB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* PCIE PORT regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define PCIE_LC_CNTL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) # define LC_L0S_INACTIVITY(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) # define LC_L0S_INACTIVITY_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) # define LC_L0S_INACTIVITY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) # define LC_L1_INACTIVITY(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) # define LC_L1_INACTIVITY_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) # define LC_L1_INACTIVITY_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) # define LC_PMI_TO_L1_DIS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) # define LC_ASPM_TO_L1_DIS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) # define LC_LINK_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) # define LC_LINK_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) # define LC_LINK_WIDTH_X0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) # define LC_LINK_WIDTH_X1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) # define LC_LINK_WIDTH_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) # define LC_LINK_WIDTH_X4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) # define LC_LINK_WIDTH_X8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) # define LC_LINK_WIDTH_X16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) # define LC_LINK_WIDTH_RD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) # define LC_LINK_WIDTH_RD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) # define LC_RECONFIG_NOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) # define LC_RENEGOTIATION_SUPPORT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) # define LC_RENEGOTIATE_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) # define LC_SHORT_RECONFIG_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) # define LC_UPCONFIGURE_SUPPORT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) # define LC_UPCONFIGURE_DIS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) # define LC_CURRENT_DATA_RATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define MM_CFGREGS_CNTL 0x544c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) # define MM_WR_TO_CFG_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define LINK_CNTL2 0x88 /* F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) # define TARGET_LINK_SPEED_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) # define SELECTABLE_DEEMPHASIS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * PM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) (((reg) >> 2) & 0xFFFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) (((op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* UVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define UVD_SEMA_ADDR_LOW 0xef00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define UVD_SEMA_ADDR_HIGH 0xef04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define UVD_SEMA_CMD 0xef08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define UVD_GPCOM_VCPU_CMD 0xef0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define UVD_GPCOM_VCPU_DATA0 0xef10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define UVD_GPCOM_VCPU_DATA1 0xef14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define UVD_LMI_EXT40_ADDR 0xf498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define UVD_VCPU_CHIP_ID 0xf4d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define UVD_VCPU_CACHE_OFFSET0 0xf4d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define UVD_VCPU_CACHE_SIZE0 0xf4dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define UVD_VCPU_CACHE_OFFSET1 0xf4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define UVD_VCPU_CACHE_SIZE1 0xf4e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define UVD_VCPU_CACHE_OFFSET2 0xf4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define UVD_VCPU_CACHE_SIZE2 0xf4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define UVD_LMI_ADDR_EXT 0xf594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define UVD_RBC_RB_RPTR 0xf690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define UVD_RBC_RB_WPTR 0xf694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define UVD_CONTEXT_ID 0xf6f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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