^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/radeon_drm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "avivod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "radeon_audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "rv770d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R700_PFP_UCODE_SIZE 848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R700_PM4_UCODE_SIZE 1360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void rv770_gpu_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void rv770_fini(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* RV740 uses evergreen uvd clk programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (rdev->family == CHIP_RV740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return evergreen_set_uvd_clocks(rdev, vclk, dclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* bypass vclk and dclk with bclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) WREG32_P(CG_UPLL_FUNC_CNTL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!vclk || !dclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* keep the Bypass mode, put PLL to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 43663, 0x03FFFFFE, 1, 30, ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &fb_div, &vclk_div, &dclk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) fb_div |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) vclk_div -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dclk_div -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* set UPLL_FB_DIV to 0x50000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* deassert UPLL_RESET and UPLL_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* assert PLL_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* set the required FB_DIV, REF_DIV, Post divder values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) WREG32_P(CG_UPLL_FUNC_CNTL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) UPLL_SW_HILEN(vclk_div >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) UPLL_SW_HILEN2(dclk_div >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ~UPLL_SW_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ~UPLL_FB_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* give the PLL some time to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mdelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* deassert PLL_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mdelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* switch VCLK and DCLK selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) WREG32_P(CG_UPLL_FUNC_CNTL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const u32 r7xx_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x8d00, 0xffffffff, 0x0e0e0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x8d04, 0xffffffff, 0x013a2b34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x9508, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x8b20, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x88c4, 0xffffffff, 0x000000c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x28350, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x9058, 0xffffffff, 0x0fffc40f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x240c, 0xffffffff, 0x00000380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x733c, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x2650, 0x00040000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x20bc, 0x00040000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x7300, 0xffffffff, 0x001000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const u32 r7xx_golden_dyn_gpr_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x8db0, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x8db4, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x8db8, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x8dbc, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x8dc0, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x8dc4, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x8dc8, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x8dcc, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x88c4, 0xffffffff, 0x00000082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const u32 rv770_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x562c, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x3f90, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x9148, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x3f94, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x914c, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x9698, 0x18000000, 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const u32 rv770ce_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x562c, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x3f90, 0xffffffff, 0x00cc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x9148, 0xffffffff, 0x00cc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x3f94, 0xffffffff, 0x00cc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x914c, 0xffffffff, 0x00cc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x9b7c, 0xffffffff, 0x00fa0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x3f8c, 0xffffffff, 0x00fa0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x9698, 0x18000000, 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const u32 rv770_mgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0x8bcc, 0xffffffff, 0x130300f9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x5448, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x55e4, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0x160c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x5644, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0xc164, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x8a18, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x897c, 0xffffffff, 0x8000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x8b28, 0xffffffff, 0x3c000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x9144, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x9a1c, 0xffffffff, 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x9a1c, 0xffffffff, 0x10001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0x9a1c, 0xffffffff, 0x10002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x9a1c, 0xffffffff, 0x10003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x9a1c, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x9870, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x8d58, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x9500, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x9500, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x9500, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x9500, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0x9500, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x9500, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0x9500, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x9500, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x9500, 0xffffffff, 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x9500, 0xffffffff, 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x9500, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x9490, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x9490, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0x9490, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x9490, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x9490, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x9490, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0x9490, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x9490, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0x9490, 0xffffffff, 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0x9490, 0xffffffff, 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x9490, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x9604, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x9604, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x9604, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x9604, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x9604, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x9604, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x9604, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x9604, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x9604, 0xffffffff, 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x9604, 0xffffffff, 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x9604, 0xffffffff, 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x9030, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x9034, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x9038, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x903c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x9040, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0xa200, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0xa204, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0xa208, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0xa20c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x971c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x915c, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x9160, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x916c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x9170, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x9174, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x9178, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x917c, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x9180, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x918c, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x9190, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x9194, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x9198, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x919c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x91a8, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x91ac, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x91b0, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x91b4, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x91b8, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x91c4, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x91c8, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x91cc, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x91d0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x91d4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x91e0, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x91e4, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x91e8, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x91ec, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x91f0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x91f4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x9200, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x9204, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x9208, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x920c, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x9210, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x921c, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x9220, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x9224, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x9228, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x922c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x9238, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x923c, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x9240, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x9244, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x9248, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x9254, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x9258, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x925c, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x9260, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x9264, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x9270, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x9274, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x9278, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x927c, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x9280, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x928c, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x9290, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x9294, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x929c, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x92a0, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x92a4, 0xffffffff, 0x00080007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const u32 rv710_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x3f90, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x9148, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x3f94, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x914c, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0xb4c, 0x00000020, 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0xa180, 0xffffffff, 0x00003f3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const u32 rv710_mgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x8bcc, 0xffffffff, 0x13030040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x5448, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x55e4, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x160c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x5644, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0xc164, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x8a18, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x897c, 0xffffffff, 0x8000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x8b28, 0xffffffff, 0x3c000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x9144, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x9a1c, 0xffffffff, 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x9a1c, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x9870, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x8d58, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x9500, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x9500, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x9500, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x9490, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x9490, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x9490, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x9604, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x9604, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x9604, 0xffffffff, 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x9030, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x9034, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x9038, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x903c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x9040, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0xa200, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0xa204, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0xa208, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0xa20c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x971c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x915c, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x9174, 0xffffffff, 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x9178, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x917c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x918c, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x9190, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x9194, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x9198, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x91a8, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x91ac, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x91e8, 0xffffffff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0x9294, 0xffffffff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x929c, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x92a0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x9150, 0xffffffff, 0x4d940000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const u32 rv730_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x3f90, 0x00ff0000, 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x9148, 0x00ff0000, 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x3f94, 0x00ff0000, 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x914c, 0x00ff0000, 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x900c, 0xffffffff, 0x003b033f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0xb4c, 0x00000020, 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0xa180, 0xffffffff, 0x00003f3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const u32 rv730_mgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x8bcc, 0xffffffff, 0x130300f9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x5448, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x55e4, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x160c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x5644, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0xc164, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x8a18, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x897c, 0xffffffff, 0x8000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x8b28, 0xffffffff, 0x3c000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0x9144, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x9a1c, 0xffffffff, 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x9a1c, 0xffffffff, 0x10001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x9a1c, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0x9870, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x8d58, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x9500, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x9500, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0x9500, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0x9500, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x9500, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0x9500, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x9500, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0x9500, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x9500, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x9490, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0x9490, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0x9490, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x9490, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0x9490, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x9490, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x9490, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x9490, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x9490, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x9604, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x9604, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x9604, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x9604, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 0x9604, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x9604, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x9604, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0x9604, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 0x9604, 0xffffffff, 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x9030, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 0x9034, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0x9038, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0x903c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x9040, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 0xa200, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0xa204, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 0xa208, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0xa20c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0x971c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0x915c, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 0x916c, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x9170, 0xffffffff, 0x00000005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0x9178, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 0x917c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x918c, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0x9190, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x9194, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0x9198, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x91a8, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x91ac, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0x91b0, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0x91b4, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x91c4, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x91c8, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x91cc, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x91d0, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x91e0, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x91e4, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x91e8, 0xffffffff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x91ec, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x91f0, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x9200, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x9204, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0x9208, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x920c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x921c, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x9220, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x9224, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x9228, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x9238, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x923c, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x9240, 0xffffffff, 0x00050001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x9244, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x9254, 0xffffffff, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x9258, 0xffffffff, 0x00070006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x9294, 0xffffffff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x929c, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x92a0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x92a4, 0xffffffff, 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const u32 rv740_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x88c4, 0xffffffff, 0x00000082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x28a50, 0xfffffffc, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x2650, 0x00040000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x20bc, 0x00040000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x733c, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x7300, 0xffffffff, 0x001000f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x3f90, 0x00ff0000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x9148, 0x00ff0000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x3f94, 0x00ff0000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x914c, 0x00ff0000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x240c, 0xffffffff, 0x00000380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x8a14, 0x00000007, 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x8b24, 0xffffffff, 0x00ff0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x28a4c, 0xffffffff, 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0xa180, 0xffffffff, 0x00003f3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x8d00, 0xffffffff, 0x0e0e003a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x8d04, 0xffffffff, 0x013a0e2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x8c00, 0xffffffff, 0xe400000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x8db0, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x8db4, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0x8db8, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x8dbc, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x8dc0, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x8dc4, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x8dc8, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x8dcc, 0xffffffff, 0x98989898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0x9058, 0xffffffff, 0x0fffc40f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x900c, 0xffffffff, 0x003b033f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x28350, 0xffffffff, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x8cf0, 0x1fffffff, 0x08e00420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x9508, 0xffffffff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x88c4, 0xffffffff, 0x000000c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x9698, 0x18000000, 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const u32 rv740_mgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x8bcc, 0xffffffff, 0x13030100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0x5448, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x55e4, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0x160c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0x5644, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0xc164, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0x8a18, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x897c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0x8b28, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x9144, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0x9a1c, 0xffffffff, 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x9a1c, 0xffffffff, 0x10001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0x9a1c, 0xffffffff, 0x10002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0x9a1c, 0xffffffff, 0x10003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x9a50, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0x9a1c, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x9870, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x8d58, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x9500, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0x9500, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 0x9500, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x9500, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0x9500, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0x9500, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 0x9500, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0x9500, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0x9510, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 0x9500, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0x9490, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0x9490, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 0x9490, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 0x9490, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 0x9490, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x9490, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0x9490, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0x9490, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 0x949c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x9490, 0xffffffff, 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0x9604, 0xffffffff, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0x9604, 0xffffffff, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 0x9604, 0xffffffff, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x9604, 0xffffffff, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x9604, 0xffffffff, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x9604, 0xffffffff, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x9604, 0xffffffff, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0x9604, 0xffffffff, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 0x9654, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x9604, 0xffffffff, 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 0x9030, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0x9034, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 0x9038, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0x903c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 0x9040, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0xa200, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 0xa204, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0xa208, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0xa20c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 0x971c, 0xffffffff, 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x915c, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 0x9160, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0x916c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0x9170, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0x9174, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 0x9178, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0x917c, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0x9180, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x918c, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0x9190, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x9194, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0x9198, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0x919c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 0x91a8, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 0x91ac, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 0x91b0, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 0x91b4, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0x91b8, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 0x91c4, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x91c8, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 0x91cc, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0x91d0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 0x91d4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0x91e0, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 0x91e4, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 0x91e8, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 0x91ec, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0x91f0, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0x91f4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0x9200, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 0x9204, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x9208, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 0x920c, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 0x9210, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0x921c, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0x9220, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 0x9224, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0x9228, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0x922c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0x9238, 0xffffffff, 0x00080007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0x923c, 0xffffffff, 0x000a0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 0x9240, 0xffffffff, 0x000c000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 0x9244, 0xffffffff, 0x000e000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 0x9248, 0xffffffff, 0x0010000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 0x9254, 0xffffffff, 0x00120011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 0x9258, 0xffffffff, 0x00140013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0x9294, 0xffffffff, 0x00020001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 0x929c, 0xffffffff, 0x00040003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0x92a0, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0x92a4, 0xffffffff, 0x00080007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void rv770_init_golden_registers(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case CHIP_RV770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) r7xx_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (const u32)ARRAY_SIZE(r7xx_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) r7xx_golden_dyn_gpr_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (rdev->pdev->device == 0x994e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) rv770ce_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) (const u32)ARRAY_SIZE(rv770ce_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) rv770_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (const u32)ARRAY_SIZE(rv770_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) rv770_mgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (const u32)ARRAY_SIZE(rv770_mgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case CHIP_RV730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) r7xx_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) (const u32)ARRAY_SIZE(r7xx_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) r7xx_golden_dyn_gpr_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rv730_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) (const u32)ARRAY_SIZE(rv730_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) rv730_mgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (const u32)ARRAY_SIZE(rv730_mgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case CHIP_RV710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) r7xx_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (const u32)ARRAY_SIZE(r7xx_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) r7xx_golden_dyn_gpr_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rv710_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) (const u32)ARRAY_SIZE(rv710_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rv710_mgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (const u32)ARRAY_SIZE(rv710_mgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case CHIP_RV740:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rv740_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) (const u32)ARRAY_SIZE(rv740_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rv740_mgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (const u32)ARRAY_SIZE(rv740_mgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define PCIE_BUS_CLK 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TCLK (PCIE_BUS_CLK / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * rv770_get_xclk - get the xclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Returns the reference clock used by the gfx engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * (r7xx-cayman).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 rv770_get_xclk(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 reference_clock = rdev->clock.spll.reference_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 tmp = RREG32(CG_CLKPIN_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (tmp & MUX_TCLK_TO_XCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return TCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (tmp & XTALIN_DIVIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return reference_clock / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return reference_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Lock the graphics update lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* update the scanout addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (radeon_crtc->crtc_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (u32)crtc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) (u32)crtc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Wait for update_pending to go high. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Unlock the lock, so double-buffering can take place inside vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Return current update_pending status: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* get temperature in millidegrees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int rv770_get_temp(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ASIC_T_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int actual_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (temp & 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) actual_temp = -256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) else if (temp & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) actual_temp = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else if (temp & 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) actual_temp = temp & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) actual_temp |= ~0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) actual_temp = temp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return (actual_temp * 1000) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) void rv770_pm_misc(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int req_ps_idx = rdev->pm.requested_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int req_cm_idx = rdev->pm.requested_clock_mode_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* 0xff01 is a flag rather then an actual voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (voltage->voltage == 0xff01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (voltage->voltage != rdev->pm.current_vddc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rdev->pm.current_vddc = voltage->voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * GART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int rv770_pcie_gart_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (rdev->gart.robj == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) r = radeon_gart_table_vram_pin(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Setup L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) EFFECTIVE_L2_QUEUE_SIZE(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) WREG32(VM_L2_CNTL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Setup TLB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SYSTEM_ACCESS_MODE_NOT_IN_SYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (rdev->family == CHIP_RV740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (u32)(rdev->dummy_page.addr >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) for (i = 1; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) r600_pcie_gart_tlb_flush(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) (unsigned)(rdev->mc.gtt_size >> 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) (unsigned long long)rdev->gart.table_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) rdev->gart.ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void rv770_pcie_gart_disable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Disable all tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Setup L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) EFFECTIVE_L2_QUEUE_SIZE(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) WREG32(VM_L2_CNTL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Setup TLB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) radeon_gart_table_vram_unpin(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static void rv770_pcie_gart_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) radeon_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rv770_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) radeon_gart_table_vram_free(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void rv770_agp_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Setup L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) EFFECTIVE_L2_QUEUE_SIZE(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) WREG32(VM_L2_CNTL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Setup TLB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SYSTEM_ACCESS_MODE_NOT_IN_SYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static void rv770_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct rv515_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Initialize HDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) for (i = 0, j = 0; i < 32; i++, j += 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) WREG32((0x2c14 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) WREG32((0x2c18 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) WREG32((0x2c1c + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) WREG32((0x2c20 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) WREG32((0x2c24 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* r7xx hw bug. Read from HDP_DEBUG1 rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) tmp = RREG32(HDP_DEBUG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) rv515_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (r600_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Lockout access through VGA aperture*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Update configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (rdev->mc.vram_start < rdev->mc.gtt_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* VRAM before AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) rdev->mc.vram_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) rdev->mc.gtt_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* VRAM after AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rdev->mc.gtt_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) rdev->mc.vram_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) rdev->mc.vram_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rdev->mc.vram_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) WREG32(MC_VM_FB_LOCATION, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) WREG32(HDP_NONSURFACE_INFO, (2 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) WREG32(MC_VM_AGP_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (r600_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rv515_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* we need to own VRAM, so turn off the VGA renderer here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * to stop it overwriting our objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rv515_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * CP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) void r700_cp_stop(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) WREG32(SCRATCH_UMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static int rv770_cp_load_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) const __be32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!rdev->me_fw || !rdev->pfp_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) r700_cp_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) WREG32(CP_RB_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) BUF_SWAP_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Reset cp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) RREG32(GRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) mdelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) WREG32(GRBM_SOFT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fw_data = (const __be32 *)rdev->pfp_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) fw_data = (const __be32 *)rdev->me_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) WREG32(CP_ME_RAM_WADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) WREG32(CP_ME_RAM_WADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) WREG32(CP_ME_RAM_RADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) void r700_cp_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) r700_cp_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) radeon_ring_fini(rdev, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) radeon_scratch_free(rdev, ring->rptr_save_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) u32 tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) tmp &= SCLK_MUX_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) tmp &= ~SCLK_MUX_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) tmp = RREG32(MPLL_CNTL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) tmp &= ~RV730_MPLL_MCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) tmp &= ~MPLL_MCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) WREG32(MPLL_CNTL_MODE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * Core functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static void rv770_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) int i, j, num_qd_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) u32 ta_aux_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u32 sx_debug_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 smx_dc_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 db_debug3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u32 num_gs_verts_per_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u32 vgt_gs_per_es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 gs_prim_buffer_depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) u32 sq_ms_fifo_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u32 sq_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u32 sq_thread_resource_mgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u32 hdp_host_path_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u32 sq_dyn_gpr_size_simd_ab_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) u32 gb_tiling_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u32 cc_gc_shader_pipe_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u32 mc_arb_ramcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u32 db_debug4, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) u32 inactive_pipes, shader_pipe_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 disabled_rb_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned active_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* setup chip specs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) rdev->config.rv770.tiling_group_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case CHIP_RV770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) rdev->config.rv770.max_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) rdev->config.rv770.max_tile_pipes = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) rdev->config.rv770.max_simds = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) rdev->config.rv770.max_backends = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) rdev->config.rv770.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) rdev->config.rv770.max_threads = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) rdev->config.rv770.max_stack_entries = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) rdev->config.rv770.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rdev->config.rv770.max_gs_threads = 16 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) rdev->config.rv770.sx_max_export_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) rdev->config.rv770.sx_max_export_pos_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) rdev->config.rv770.sx_max_export_smx_size = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rdev->config.rv770.sq_num_cf_insts = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) rdev->config.rv770.sx_num_of_sets = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rdev->config.rv770.sc_prim_fifo_size = 0xF9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case CHIP_RV730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) rdev->config.rv770.max_pipes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) rdev->config.rv770.max_tile_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) rdev->config.rv770.max_simds = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) rdev->config.rv770.max_backends = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) rdev->config.rv770.max_gprs = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) rdev->config.rv770.max_threads = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) rdev->config.rv770.max_stack_entries = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rdev->config.rv770.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) rdev->config.rv770.max_gs_threads = 16 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) rdev->config.rv770.sx_max_export_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) rdev->config.rv770.sx_max_export_pos_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) rdev->config.rv770.sx_max_export_smx_size = 224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) rdev->config.rv770.sq_num_cf_insts = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) rdev->config.rv770.sx_num_of_sets = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) rdev->config.rv770.sc_prim_fifo_size = 0xf9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (rdev->config.rv770.sx_max_export_pos_size > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) rdev->config.rv770.sx_max_export_pos_size -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rdev->config.rv770.sx_max_export_smx_size += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case CHIP_RV710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) rdev->config.rv770.max_pipes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) rdev->config.rv770.max_tile_pipes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) rdev->config.rv770.max_simds = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) rdev->config.rv770.max_backends = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) rdev->config.rv770.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rdev->config.rv770.max_threads = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) rdev->config.rv770.max_stack_entries = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) rdev->config.rv770.max_hw_contexts = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rdev->config.rv770.max_gs_threads = 8 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) rdev->config.rv770.sx_max_export_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rdev->config.rv770.sx_max_export_pos_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) rdev->config.rv770.sx_max_export_smx_size = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) rdev->config.rv770.sq_num_cf_insts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) rdev->config.rv770.sx_num_of_sets = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) rdev->config.rv770.sc_prim_fifo_size = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case CHIP_RV740:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rdev->config.rv770.max_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) rdev->config.rv770.max_tile_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) rdev->config.rv770.max_simds = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) rdev->config.rv770.max_backends = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) rdev->config.rv770.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rdev->config.rv770.max_threads = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) rdev->config.rv770.max_stack_entries = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) rdev->config.rv770.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) rdev->config.rv770.max_gs_threads = 16 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) rdev->config.rv770.sx_max_export_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) rdev->config.rv770.sx_max_export_pos_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) rdev->config.rv770.sx_max_export_smx_size = 224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) rdev->config.rv770.sq_num_cf_insts = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) rdev->config.rv770.sx_num_of_sets = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) rdev->config.rv770.sc_prim_fifo_size = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (rdev->config.rv770.sx_max_export_pos_size > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) rdev->config.rv770.sx_max_export_pos_size -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) rdev->config.rv770.sx_max_export_smx_size += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Initialize HDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) WREG32((0x2c14 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) WREG32((0x2c18 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) WREG32((0x2c1c + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) WREG32((0x2c20 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) WREG32((0x2c24 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) j += 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* setup tiling, simd, pipe config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (!(inactive_pipes & tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) active_number++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) tmp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (active_number == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) WREG32(SPI_CONFIG_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) tmp = rdev->config.rv770.max_simds -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) rdev->config.rv770.active_simds = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) switch (rdev->config.rv770.max_tile_pipes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) gb_tiling_config = PIPE_TILING(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) gb_tiling_config = PIPE_TILING(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) gb_tiling_config = PIPE_TILING(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) gb_tiling_config = PIPE_TILING(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) for (i = 0; i < rdev->config.rv770.max_backends; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) tmp |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* if all the backends are disabled, fix it up here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if ((disabled_rb_mask & tmp) == tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) for (i = 0; i < rdev->config.rv770.max_backends; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) disabled_rb_mask &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) R7XX_MAX_BACKENDS, disabled_rb_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) gb_tiling_config |= tmp << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) rdev->config.rv770.backend_map = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (rdev->family == CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) gb_tiling_config |= BANK_TILING(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) gb_tiling_config |= BANK_TILING(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) gb_tiling_config |= BANK_TILING(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) gb_tiling_config |= ROW_TILING(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) gb_tiling_config |= SAMPLE_SPLIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) gb_tiling_config |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) gb_tiling_config |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) gb_tiling_config |= BANK_SWAPS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) rdev->config.rv770.tile_config = gb_tiling_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) WREG32(GB_TILING_CONFIG, gb_tiling_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (rdev->family == CHIP_RV730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) WREG32(CGTS_SYS_TCC_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) WREG32(CGTS_TCC_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) WREG32(CGTS_USER_TCC_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* set HW defaults for 3D engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ROQ_IB2_START(0x2b)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ta_aux_cntl = RREG32(TA_CNTL_AUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) sx_debug_1 = RREG32(SX_DEBUG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) WREG32(SX_DEBUG_1, sx_debug_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) WREG32(SMX_DC_CTL0, smx_dc_ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (rdev->family != CHIP_RV740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) GS_FLUSH_CTL(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ACK_FLUSH_CTL(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SYNC_FLUSH_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (rdev->family != CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) WREG32(SMX_SAR_CTL0, 0x00003f3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) db_debug3 = RREG32(DB_DEBUG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case CHIP_RV770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case CHIP_RV740:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case CHIP_RV710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case CHIP_RV730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) db_debug3 |= DB_CLK_OFF_DELAY(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) WREG32(DB_DEBUG3, db_debug3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (rdev->family != CHIP_RV770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) db_debug4 = RREG32(DB_DEBUG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) WREG32(DB_DEBUG4, db_debug4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) WREG32(VGT_NUM_INSTANCES, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) WREG32(CP_PERFMON_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) DONE_FIFO_HIWATER(0xe0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ALU_UPDATE_FIFO_HIWATER(0x8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case CHIP_RV770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) case CHIP_RV730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) case CHIP_RV710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case CHIP_RV740:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * should be adjusted as needed by the 2D/3D drivers. This just sets default values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) sq_config = RREG32(SQ_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sq_config &= ~(PS_PRIO(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) VS_PRIO(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) GS_PRIO(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ES_PRIO(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) sq_config |= (DX9_CONSTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) VC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) EXPORT_SRC_C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PS_PRIO(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) VS_PRIO(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) GS_PRIO(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ES_PRIO(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (rdev->family == CHIP_RV710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* no vertex cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) sq_config &= ~VC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) WREG32(SQ_CONFIG, sq_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) FORCE_EOV_MAX_REZ_CNT(255)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (rdev->family == CHIP_RV710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) AUTO_INVLD_EN(ES_AND_GS_AUTO)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) AUTO_INVLD_EN(ES_AND_GS_AUTO)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) case CHIP_RV770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) case CHIP_RV730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) case CHIP_RV740:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) gs_prim_buffer_depth = 384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) case CHIP_RV710:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) gs_prim_buffer_depth = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Max value for this is 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (vgt_gs_per_es > 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) vgt_gs_per_es = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) WREG32(VGT_ES_PER_GS, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) WREG32(VGT_GS_PER_VS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* more default values. 2D/3D driver should adjust as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) WREG32(VGT_GS_VERTEX_REUSE, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) WREG32(VGT_STRMOUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) WREG32(SX_MISC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) WREG32(PA_SC_MODE_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) WREG32(PA_SC_AA_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) WREG32(PA_SC_LINE_STIPPLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) WREG32(SPI_INPUT_Z, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) WREG32(CB_COLOR7_FRAG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* clear render buffer base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) WREG32(CB_COLOR0_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) WREG32(CB_COLOR1_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) WREG32(CB_COLOR2_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) WREG32(CB_COLOR3_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) WREG32(CB_COLOR4_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) WREG32(CB_COLOR5_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) WREG32(CB_COLOR6_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) WREG32(CB_COLOR7_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) WREG32(TCP_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) NUM_CLIP_SEQ(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) WREG32(VC_ENHANCE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) u64 size_bf, size_af;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (mc->mc_vram_size > 0xE0000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* leave room for at least 512M GTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) dev_warn(rdev->dev, "limiting VRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) mc->real_vram_size = 0xE0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) mc->mc_vram_size = 0xE0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) size_bf = mc->gtt_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) size_af = mc->mc_mask - mc->gtt_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (size_bf > size_af) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (mc->mc_vram_size > size_bf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_warn(rdev->dev, "limiting VRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) mc->real_vram_size = size_bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) mc->mc_vram_size = size_bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) mc->vram_start = mc->gtt_start - mc->mc_vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (mc->mc_vram_size > size_af) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dev_warn(rdev->dev, "limiting VRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) mc->real_vram_size = size_af;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mc->mc_vram_size = size_af;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) mc->vram_start = mc->gtt_end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mc->mc_vram_size >> 20, mc->vram_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) mc->vram_end, mc->real_vram_size >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) radeon_vram_location(rdev, &rdev->mc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) rdev->mc.gtt_base_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) radeon_gtt_location(rdev, mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int rv770_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) int chansize, numchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Get VRAM informations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) tmp = RREG32(MC_ARB_RAMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (tmp & CHANSIZE_OVERRIDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) chansize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) } else if (tmp & CHANSIZE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) chansize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) chansize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) tmp = RREG32(MC_SHARED_CHMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) numchan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) numchan = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) numchan = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) numchan = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) rdev->mc.vram_width = numchan * chansize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* Could aper size report 0 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* Setup GPU memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) rdev->mc.visible_vram_size = rdev->mc.aper_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) r700_vram_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static void rv770_uvd_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (!rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) r = radeon_uvd_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * At this point rdev->uvd.vcpu_bo is NULL which trickles down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * to early fails uvd_v2_2_resume() and thus nothing happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * there. So it is pointless to try to go through that code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * hence why we disable uvd here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) rdev->has_uvd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static void rv770_uvd_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (!rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) r = uvd_v2_2_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static void rv770_uvd_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) r = uvd_v1_0_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static int rv770_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* enable pcie gen2 link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) rv770_pcie_gen2_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* scratch needs to be initialized before MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) r = r600_vram_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) rv770_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) rv770_agp_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) r = rv770_pcie_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) rv770_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) rv770_uvd_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) r = r600_irq_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) DRM_ERROR("radeon: IH init failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) r600_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) RADEON_CP_PACKET2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) r = rv770_cp_load_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) r = r600_cp_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) r = r600_dma_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) rv770_uvd_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) r = radeon_audio_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) DRM_ERROR("radeon: audio init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) int rv770_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * posting will perform necessary task to bring back GPU into good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * shape.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* post card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* init golden registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) rv770_init_golden_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (rdev->pm.pm_method == PM_METHOD_DPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) radeon_pm_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) r = rv770_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) DRM_ERROR("r600 startup failed on resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) int rv770_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) radeon_audio_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (rdev->has_uvd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) uvd_v1_0_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) radeon_uvd_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) r700_cp_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) r600_dma_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) r600_irq_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) rv770_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* Plan is to move initialization in that function and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * helper function so that radeon_device_init pretty much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * do nothing more than calling asic specific function. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * should also allow to remove a bunch of callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * like vram_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int rv770_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* Read BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* Must be an ATOMBIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (!rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* Post card if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (!radeon_card_posted(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (!rdev->bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) DRM_INFO("GPU not posted. posting now...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* init golden registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) rv770_init_golden_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) r600_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* initialize AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) r = radeon_agp_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) radeon_agp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) r = rv770_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) r = r600_init_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) DRM_ERROR("Failed to load firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) rv770_uvd_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) rdev->ih.ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) r600_ih_ring_init(rdev, 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) r = r600_pcie_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) r = rv770_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_err(rdev->dev, "disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) r700_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) r600_dma_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) r600_irq_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) rv770_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) void rv770_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) r700_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) r600_dma_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) r600_irq_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) uvd_v1_0_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) radeon_uvd_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) rv770_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) r600_vram_scratch_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) u32 link_width_cntl, lanes, speed_cntl, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) u16 link_cntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (radeon_pcie_gen2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (!(rdev->flags & RADEON_IS_PCIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) /* x2 cards have a special sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (ASIC_IS_X2(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) /* advertise upconfig capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) link_width_cntl &= ~LC_UPCONFIGURE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) LC_RECONFIG_ARC_MISSING_ESCAPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) link_width_cntl |= lanes | LC_RECONFIG_NOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) link_width_cntl |= LC_UPCONFIGURE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) tmp = RREG32(0x541c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) WREG32(0x541c, tmp | 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) link_cntl2 = RREG16(0x4088);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) link_cntl2 |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) WREG16(0x4088, link_cntl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) WREG32(MM_CFGREGS_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) speed_cntl |= LC_GEN2_EN_STRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) link_width_cntl |= LC_UPCONFIGURE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) link_width_cntl &= ~LC_UPCONFIGURE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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