^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef RV740_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RV740_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPLL_PDIV_A(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPLL_PDIV_A_MASK (0x7f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CG_SPLL_FUNC_CNTL_2 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CG_SPLL_FUNC_CNTL_3 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPLL_CNTL_MODE 0x61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SS_SSEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPLL_AD_FUNC_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKF(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKF_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKR(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKR_MASK (0x1f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKFRAC(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKFRAC_MASK (0x1f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define YCLK_POST_DIV(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define YCLK_POST_DIV_MASK (3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IBIAS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IBIAS_MASK (0x3ff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PDNB (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPLL_AD_FUNC_CNTL_2 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BYPASS (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BIAS_GEN_PDNB (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VCO_MODE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MPLL_DQ_FUNC_CNTL 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MPLL_DQ_FUNC_CNTL_2 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCLK_PWRMGT_CNTL 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DLL_SPEED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DLL_SPEED_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define MPLL_PWRMGT_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define MRDCKA0_SLEEP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define MRDCKA1_SLEEP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define MRDCKB0_SLEEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define MRDCKB1_SLEEP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define MRDCKC0_SLEEP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define MRDCKC1_SLEEP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define MRDCKD0_SLEEP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define MRDCKD1_SLEEP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define MRDCKA0_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define MRDCKA1_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define MRDCKB0_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define MRDCKB1_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define MRDCKC0_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define MRDCKC1_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define MRDCKD0_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define MRDCKD1_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DLL_CNTL 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define MRDCKA0_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define MRDCKA1_BYPASS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define MRDCKB0_BYPASS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define MRDCKB1_BYPASS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define MRDCKC0_BYPASS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define MRDCKC1_BYPASS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define MRDCKD0_BYPASS (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define MRDCKD1_BYPASS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CG_SPLL_SPREAD_SPECTRUM 0x790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_S(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_S_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_V(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_V_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MPLL_SS1 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLKV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLKV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MPLL_SS2 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLKS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLKS_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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