^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef RV730_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RV730_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPLL_DIVEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPLL_HILEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPLL_HILEN_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPLL_LOLEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPLL_LOLEN_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CG_SPLL_FUNC_CNTL_2 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CG_SPLL_FUNC_CNTL_3 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CG_MPLL_FUNC_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPLL_DIVEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPLL_HILEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPLL_HILEN_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPLL_LOLEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPLL_LOLEN_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CG_MPLL_FUNC_CNTL_2 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CG_MPLL_FUNC_CNTL_3 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GENERAL_PWRMGT 0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define ENABLE_GEN2PCIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define ENABLE_GEN2XSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define SW_SMIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define BACKBIAS_PAD_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define BACKBIAS_VALUE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define AC_DC_SW (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCLK_PWRMGT_CNTL 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define SCLK_LOW_D1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define FIR_RESET (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define FIR_FORCE_TREND_SEL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define FIR_TREND_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define DYN_GFX_CLK_OFF_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define GFX_CLK_FORCE_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define GFX_CLK_REQUEST_OFF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define GFX_CLK_FORCE_OFF (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TCI_MCLK_PWRMGT_CNTL 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define MPLL_PWRMGT_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define MRDCKA_SLEEP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define MRDCKB_SLEEP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define MRDCKC_SLEEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define MRDCKD_SLEEP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # define MRDCKE_SLEEP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define MRDCKF_SLEEP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define MRDCKG_SLEEP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define MRDCKH_SLEEP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define MRDCKA_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define MRDCKB_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define MRDCKC_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define MRDCKD_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define MRDCKE_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define MRDCKF_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define MRDCKG_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define MRDCKH_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TCI_DLL_CNTL 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CG_PG_CNTL 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define PWRGATE_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CG_AT 0x6d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CG_R(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CG_R_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CG_L(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CG_L_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CG_SPLL_SPREAD_SPECTRUM 0x790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_S(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_S_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_V(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_V_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MC_ARB_DRAM_TIMING 0x2774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MC_ARB_DRAM_TIMING2 0x2778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MC_ARB_RFSH_RATE 0x27b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define POWERMODE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define POWERMODE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define POWERMODE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define POWERMODE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define POWERMODE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define POWERMODE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define POWERMODE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define POWERMODE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MC_ARB_DRAM_TIMING_1 0x27f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MC_ARB_DRAM_TIMING_2 0x27f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MC_ARB_DRAM_TIMING_3 0x27f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MC_ARB_DRAM_TIMING2_1 0x27fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MC_ARB_DRAM_TIMING2_2 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MC_ARB_DRAM_TIMING2_3 0x2804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags