^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef RV6XXD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RV6XXD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* RV6xx power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPLL_CNTL_MODE 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define SPLL_DIV_SYNC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GENERAL_PWRMGT 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define MOBILE_SU (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define THERMAL_PROTECTION_DIS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define THERMAL_PROTECTION_TYPE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define ENABLE_GEN2PCIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define SW_GPIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define SW_GPIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define BACKBIAS_PAD_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define BACKBIAS_VALUE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define BACKBIAS_DPM_CNTL (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define DYN_SPREAD_SPECTRUM_EN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCLK_PWRMGT_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define MPLL_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define YCLK_TURNOFF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) # define MPLL_TURNOFF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define SU_MCLK_USE_BCLK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define DLL_READY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define MC_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define MRDCKA_SLEEP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define MRDCKB_SLEEP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define MRDCKC_SLEEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) # define MRDCKD_SLEEP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define MRDCKE_SLEEP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define MRDCKF_SLEEP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define MRDCKG_SLEEP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define MRDCKH_SLEEP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define MRDCKA_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define MRDCKB_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define MRDCKC_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define MRDCKD_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define MRDCKE_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define MRDCKF_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define MRDCKG_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define MRDCKH_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define USE_DISPLAY_GAP_CTXSW (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define USE_DISPLAY_URGENT_CTXSW (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPLL_FREQ_LEVEL_0 0x6e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define LEVEL0_MPLL_DIV_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define LEVEL0_DLL_BYPASS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define LEVEL0_DLL_RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VID_RT 0x6f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define VID_CRT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define VID_CRT_MASK (0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define VID_CRTU(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define VID_CRTU_MASK (7 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define SSTU_MASK (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define VID_SWT(x) ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define VID_SWT_MASK (0x1f << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define BRT(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define BRT_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define TARGET_PROFILE_INDEX_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define TARGET_PROFILE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define CURRENT_PROFILE_INDEX_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # define CURRENT_PROFILE_INDEX_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define DYN_PWR_ENTER_INDEX(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define DYN_PWR_ENTER_INDEX_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define DYN_PWR_ENTER_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define CURR_MCLK_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define CURR_MCLK_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define CURR_SCLK_INDEX_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define CURR_SCLK_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define CURR_VID_INDEX_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define CURR_VID_INDEX_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VID_UPPER_GPIO_CNTL 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define LOW_UPPER_GPIO_VALUES(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define LOW_UPPER_GPIO_VALUES_MASK (7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define CTXSW_BACKBIAS_VALUE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define HIGH_BACKBIAS_VALUE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define MEDIUM_BACKBIAS_VALUE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define LOW_BACKBIAS_VALUE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CG_DISPLAY_GAP_CNTL 0x7dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define DISP1_GAP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define DISP1_GAP_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define DISP2_GAP(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define DISP2_GAP_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define VBI_TIMER_COUNT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define VBI_TIMER_UNIT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define VBI_TIMER_UNIT_MASK (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define DISP1_GAP_MCHG(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define DISP1_GAP_MCHG_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define DISP2_GAP_MCHG(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define DISP2_GAP_MCHG_MASK (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CG_THERMAL_CTRL 0x7f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define DPM_EVENT_SRC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define DPM_EVENT_SRC_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define THERM_INC_CLK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define TOFFSET(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define TOFFSET_MASK (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define DIG_THERM_DPM(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define DIG_THERM_DPM_MASK (0xff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define CTF_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define CTF_SEL_MASK (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define CTF_PAD_POLARITY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define CTF_PAD_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define CLKS(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define CLKS_MASK (0xff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define CLKS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define CLKV(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define CLKV_MASK (0x7ff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define CLKV_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CG_MPLL_SPREAD_SPECTRUM 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CITF_CNTL 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define BLACKOUT_RD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define BLACKOUT_WR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RAMCFG 0x2408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define NOOFBANK_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define NOOFRANK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NOOFRANK_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NOOFROWS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define NOOFROWS_MASK 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NOOFCOLS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define NOOFCOLS_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CHANSIZE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CHANSIZE_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BURSTLENGTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BURSTLENGTH_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CHANSIZE_OVERRIDE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SQM_RATIO 0x2424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define STATE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define STATE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # define STATE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) # define STATE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) # define STATE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define STATE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define STATE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ARB_RFSH_CNTL 0x2460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) # define ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ARB_RFSH_RATE 0x2464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) # define POWERMODE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define POWERMODE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define POWERMODE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) # define POWERMODE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) # define POWERMODE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) # define POWERMODE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) # define POWERMODE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) # define POWERMODE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MC_SEQ_DRAM 0x2608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define CKE_DYN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MC_SEQ_CMD 0x26c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MC_SEQ_RESERVE_S 0x2890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MC_SEQ_RESERVE_M 0x2894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LVTMA_DATA_SYNCHRONIZATION 0x7adc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) # define LVTMA_PFREQCHG (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* PCIE indirect regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PCIE_P_CNTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) # define P_PLL_PWRDN_IN_L1L23 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) # define P_PLL_BUF_PDNB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) # define P_PLL_PDNB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* PCIE PORT indirect regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PCIE_LC_CNTL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) # define LC_L0S_INACTIVITY(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) # define LC_L0S_INACTIVITY_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) # define LC_L0S_INACTIVITY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) # define LC_L1_INACTIVITY(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define LC_L1_INACTIVITY_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define LC_L1_INACTIVITY_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define LC_PMI_TO_L1_DIS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define LC_ASPM_TO_L1_DIS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCIE_LC_SPEED_CNTL 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) # define LC_GEN2_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) # define LC_CURRENT_DATA_RATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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