^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef __RV515D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __RV515D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * RV515 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_INDEX 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_DATA 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MC_IND_INDEX 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MC_IND_WR_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC_IND_DATA 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RBBM_SOFT_RESET 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONFIG_MEMSIZE 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HDP_FB_LOCATION 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CP_CSQ_CNTL 0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CP_CSQ_MODE 0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CP_CSQ_ADDR 0x07F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CP_CSQ_DATA 0x07F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CP_CSQ_STAT 0x07F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CP_CSQ2_STAT 0x07FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RBBM_STATUS 0x0E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DST_PIPE_CONFIG 0x170C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WAIT_UNTIL 0x1720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WAIT_2D_IDLE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WAIT_3D_IDLE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WAIT_2D_IDLECLEAN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WAIT_3D_IDLECLEAN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ISYNC_CNTL 0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ISYNC_ANY2D_IDLE3D (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ISYNC_ANY3D_IDLE2D (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISYNC_TRIG2D_IDLE3D (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ISYNC_TRIG3D_IDLE2D (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ISYNC_WAIT_IDLEGUI (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VAP_INDEX_OFFSET 0x208C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VAP_PVS_STATE_FLUSH_REG 0x2284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GB_ENABLE 0x4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GB_MSPOS0 0x4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MS_X0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MS_Y0_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MS_X1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MS_Y1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MS_X2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MS_Y2_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSBD0_Y_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSBD0_X_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GB_MSPOS1 0x4014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MS_X3_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MS_Y3_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MS_X4_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MS_Y4_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MS_X5_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MS_Y5_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSBD1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GB_TILE_CONFIG 0x4018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ENABLE_TILING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PIPE_COUNT_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PIPE_COUNT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TILE_SIZE_8 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TILE_SIZE_16 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TILE_SIZE_32 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SUBPIXEL_1_12 (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SUBPIXEL_1_16 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GB_SELECT 0x401C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GB_AA_CONFIG 0x4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GB_PIPE_SELECT 0x402C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GA_ENHANCE 0x4274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GA_DEADLOCK_CNTL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GA_FASTSYNC_CNTL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GA_POLY_MODE 0x4288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FRONT_PTYPE_POINT (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FRONT_PTYPE_LINE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FRONT_PTYPE_TRIANGE (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BACK_PTYPE_POINT (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BACK_PTYPE_LINE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BACK_PTYPE_TRIANGE (2 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GA_ROUND_MODE 0x428C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GEOMETRY_ROUND_TRUNC (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GEOMETRY_ROUND_NEAREST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define COLOR_ROUND_TRUNC (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define COLOR_ROUND_NEAREST (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SU_REG_DEST 0x42C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RB3D_DSTCACHE_CTLSTAT 0x4E4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RB3D_DC_FLUSH (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RB3D_DC_FREE (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RB3D_DC_FINISH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ZB_ZCACHE_CTLSTAT 0x4F18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ZC_FLUSH (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ZC_FREE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DC_LB_MEMORY_SPLIT 0x6520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DC_LB_MEMORY_SPLIT_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DC_LB_MEMORY_SPLIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DC_LB_MEMORY_SPLIT_D1_ONLY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DC_LB_DISP1_END_ADR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define D1MODE_PRIORITY_A_CNT 0x6548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MODE_PRIORITY_MARK_MASK 0x00007FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MODE_PRIORITY_OFF (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MODE_PRIORITY_ALWAYS_ON (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MODE_PRIORITY_FORCE_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define D1MODE_PRIORITY_B_CNT 0x654C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LB_MAX_REQ_OUTSTANDING 0x6D58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define D2MODE_PRIORITY_A_CNT 0x6D48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define D2MODE_PRIORITY_B_CNT 0x6D4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* ix[MC] registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MC_FB_LOCATION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MC_FB_START_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MC_FB_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MC_FB_TOP_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MC_FB_TOP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MC_AGP_LOCATION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MC_AGP_START_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MC_AGP_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MC_AGP_TOP_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MC_AGP_TOP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MC_AGP_BASE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MC_AGP_BASE_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MC_CNTL 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MEM_NUM_CHANNELS_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MC_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MC_STATUS_IDLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MC_MISC_LAT_TIMER 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MC_CPR_INIT_LAT_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MC_VF_INIT_LAT_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MC_DISP0R_INIT_LAT_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MC_DISP0R_INIT_LAT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MC_DISP1R_INIT_LAT_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MC_DISP1R_INIT_LAT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MC_FIXED_INIT_LAT_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MC_E2R_INIT_LAT_MASK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SAME_PAGE_PRIO_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MC_GLOBW_INIT_LAT_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * PM4 packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CP_PACKET0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PACKET0_BASE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PACKET0_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PACKET0_COUNT_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CP_PACKET1 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CP_PACKET3 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PACKET3_IT_OPCODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PACKET3_IT_OPCODE_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PACKET3_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PACKET3_COUNT_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* PACKET3 op code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PACKET3_3D_DRAW_VBUF 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PACKET3_3D_DRAW_IMMD 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PACKET3_3D_DRAW_INDX 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PACKET3_3D_LOAD_VBPNTR 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PACKET3_INDX_BUFFER 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PACKET3_3D_DRAW_VBUF_2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PACKET3_3D_DRAW_IMMD_2 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PACKET3_3D_DRAW_INDX_2 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PACKET3_BITBLT_MULTI 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PACKET0(reg, n) (CP_PACKET0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) REG_SET(PACKET0_COUNT, (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PACKET3(op, n) (CP_PACKET3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) REG_SET(PACKET3_IT_OPCODE, (op)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) REG_SET(PACKET3_COUNT, (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define R_0000F0_RBBM_SOFT_RESET 0x0000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define R_0000F8_CONFIG_MEMSIZE 0x0000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define C_0000F8_CONFIG_MEMSIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define R_000134_HDP_FB_LOCATION 0x000134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define C_000134_HDP_FB_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define R_000300_VGA_RENDER_CONTROL 0x000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define R_000328_VGA_HDP_CONTROL 0x000328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define R_000330_D1VGA_CONTROL 0x000330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define C_000330_D1VGA_ROTATE 0xFCFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define R_000338_D2VGA_CONTROL 0x000338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define C_000338_D2VGA_ROTATE 0xFCFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define R_0007C0_CP_STAT 0x0007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define C_0007C0_MRU_BUSY 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define C_0007C0_MWU_BUSY 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define C_0007C0_CSI_BUSY 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define C_0007C0_CP_BUSY 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define R_000E40_RBBM_STATUS 0x000E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define C_000E40_E2_BUSY 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define C_000E40_RB2D_BUSY 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define C_000E40_RB3D_BUSY 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define C_000E40_VAP_BUSY 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define C_000E40_RE_BUSY 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define C_000E40_TAM_BUSY 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define C_000E40_TDM_BUSY 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define C_000E40_PB_BUSY 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define C_000E40_TIM_BUSY 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define C_000E40_GA_BUSY 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define C_000E40_CBA2D_BUSY 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define C_000E40_SKID_CFBUSY 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define R_006080_D1CRTC_CONTROL 0x006080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define R_006880_D2CRTC_CONTROL 0x006880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define R_000001_MC_FB_LOCATION 0x000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define C_000001_MC_FB_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define C_000001_MC_FB_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define R_000002_MC_AGP_LOCATION 0x000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define C_000002_MC_AGP_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define C_000002_MC_AGP_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define R_000003_MC_AGP_BASE 0x000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define C_000003_AGP_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define R_000004_MC_AGP_BASE_2 0x000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define R_00000F_CP_DYN_CNTL 0x00000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define C_00000F_CP_FORCEON 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define S_00000F_SPARE(x) (((x) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define G_00000F_SPARE(x) (((x) >> 22) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define C_00000F_SPARE 0xFF3FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define R_000011_E2_DYN_CNTL 0x000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define C_000011_E2_FORCEON 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define S_000011_SPARE(x) (((x) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define G_000011_SPARE(x) (((x) >> 22) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define C_000011_SPARE 0xFF3FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define R_000013_IDCT_DYN_CNTL 0x000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define C_000013_IDCT_FORCEON 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define S_000013_SPARE(x) (((x) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define G_000013_SPARE(x) (((x) >> 22) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define C_000013_SPARE 0xFF3FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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