^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "rv515_reg_safe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "rv515d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* This files gather functions specifics to: rv515 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void rv515_gpu_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int rv515_mc_wait_for_idle(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const u32 crtc_offsets[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void rv515_debugfs(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (r100_debugfs_rbbm_init(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DRM_ERROR("Failed to register debugfs file for RBBM !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (rv515_debugfs_pipes_info_init(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DRM_ERROR("Failed to register debugfs file for pipes !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (rv515_debugfs_ga_info_init(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DRM_ERROR("Failed to register debugfs file for pipes !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) r = radeon_ring_lock(rdev, ring, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) radeon_ring_write(ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ISYNC_ANY2D_IDLE3D |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ISYNC_ANY3D_IDLE2D |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ISYNC_WAIT_IDLEGUI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ISYNC_CPSCRATCH_IDLEGUI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) radeon_ring_write(ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ((6 << MS_X0_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (6 << MS_Y0_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (6 << MS_X1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (6 << MS_Y1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (6 << MS_X2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (6 << MS_Y2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (6 << MSBD0_Y_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (6 << MSBD0_X_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) radeon_ring_write(ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ((6 << MS_X3_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (6 << MS_Y3_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (6 << MS_X4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (6 << MS_Y4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (6 << MS_X5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (6 << MS_Y5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (6 << MSBD1_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) radeon_ring_write(ring, PACKET0(0x20C8, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int rv515_mc_wait_for_idle(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* read MC_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tmp = RREG32_MC(MC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (tmp & MC_STATUS_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void rv515_vga_render_disable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) WREG32(R_000300_VGA_RENDER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void rv515_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned pipe_select_current, gb_pipe_select, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (r100_gui_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rv515_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) r420_pipes_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tmp = RREG32(R300_DST_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pipe_select_current = (tmp >> 2) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp = (1 << pipe_select_current) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (((gb_pipe_select >> 8) & 0xF) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WREG32_PLL(0x000D, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (r100_gui_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (rv515_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void rv515_vram_get_type(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rdev->mc.vram_width = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void rv515_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rv515_vram_get_type(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) r100_vram_init_sizes(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) radeon_vram_location(rdev, &rdev->mc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rdev->mc.gtt_base_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!(rdev->flags & RADEON_IS_AGP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) radeon_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint32_t r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) r = RREG32(MC_IND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) WREG32(MC_IND_INDEX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) WREG32(MC_IND_DATA, (v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) WREG32(MC_IND_INDEX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct drm_info_node *node = (struct drm_info_node *) m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct drm_device *dev = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct radeon_device *rdev = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tmp = RREG32(GB_PIPE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp = RREG32(SU_REG_DEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tmp = RREG32(GB_TILE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tmp = RREG32(DST_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct drm_info_node *node = (struct drm_info_node *) m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct drm_device *dev = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct radeon_device *rdev = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tmp = RREG32(0x2140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) radeon_asic_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tmp = RREG32(0x425C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct drm_info_list rv515_pipes_info_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct drm_info_list rv515_ga_info_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 crtc_enabled, tmp, frame_count, blackout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* disable VGA render */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) WREG32(R_000300_VGA_RENDER_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* blank the display controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (crtc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) save->crtc_enabled[i] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) radeon_wait_for_vblank(rdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* wait for the next frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) frame_count = radeon_get_vblank_counter(rdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (j = 0; j < rdev->usec_timeout; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (radeon_get_vblank_counter(rdev, i) != frame_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tmp &= ~AVIVO_CRTC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) save->crtc_enabled[i] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* ***** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) save->crtc_enabled[i] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) radeon_mc_wait_for_idle(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rdev->family >= CHIP_R600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (rdev->family >= CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) blackout = RREG32(R700_MC_CITF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) blackout = RREG32(R600_CITF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Block CPU access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) WREG32(R600_BIF_FB_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* blackout the MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) blackout |= R600_BLACKOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (rdev->family >= CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) WREG32(R700_MC_CITF_CNTL, blackout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) WREG32(R600_CITF_CNTL, blackout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* wait for the MC to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* lock double buffered regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (save->crtc_enabled[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!(tmp & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tmp |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 tmp, frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* update crtc base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (rdev->family >= CHIP_RV770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) upper_32_bits(rdev->mc.vram_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) upper_32_bits(rdev->mc.vram_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) upper_32_bits(rdev->mc.vram_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) upper_32_bits(rdev->mc.vram_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) (u32)rdev->mc.vram_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (u32)rdev->mc.vram_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* unlock regs and wait for update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (save->crtc_enabled[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((tmp & 0x7) != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tmp &= ~0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) tmp |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (tmp & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tmp &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (j = 0; j < rdev->usec_timeout; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (rdev->family >= CHIP_R600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* unblackout the MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (rdev->family >= CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tmp = RREG32(R700_MC_CITF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tmp = RREG32(R600_CITF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp &= ~R600_BLACKOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (rdev->family >= CHIP_RV770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) WREG32(R700_MC_CITF_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) WREG32(R600_CITF_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* allow CPU access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (save->crtc_enabled[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* wait for the next frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) frame_count = radeon_get_vblank_counter(rdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (j = 0; j < rdev->usec_timeout; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (radeon_get_vblank_counter(rdev, i) != frame_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Unlock vga access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void rv515_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct rv515_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Stops all mc clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rv515_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Wait for mc idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (rv515_mc_wait_for_idle(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Write VRAM size in case we are limiting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Program MC, should be a 32bits limited address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) WREG32_MC(R_000001_MC_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WREG32(R_000134_HDP_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) WREG32_MC(R_000002_MC_AGP_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) WREG32_MC(R_000004_MC_AGP_BASE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) WREG32_MC(R_000003_MC_AGP_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rv515_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) void rv515_clock_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (radeon_dynclks != -1 && radeon_dynclks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) radeon_atom_set_clock_gating(rdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* We need to force on some of the block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) WREG32_PLL(R_00000F_CP_DYN_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) WREG32_PLL(R_000011_E2_DYN_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) WREG32_PLL(R_000013_IDCT_DYN_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int rv515_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rv515_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Resume clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Initialize GPU configuration (# pipes, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rv515_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Initialize GART (initialize after TTM so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * memory through TTM but finalize after TTM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (rdev->flags & RADEON_IS_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) r = rv370_pcie_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rs600_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* 1M ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) r = r100_cp_init(rdev, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int rv515_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Make sur GART are not working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rv370_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Resume clock before doing reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Resume clock after posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) r = rv515_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int rv515_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) r100_cp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) rs600_irq_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rv370_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void rv515_set_safe_registers(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) void rv515_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rv370_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int rv515_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) radeon_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* TODO: disable VGA need to use VGA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* restore some register to sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) r100_restore_sanity(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* BIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_warn(rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (radeon_boot_test_post_card(rdev) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* initialize AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) r = radeon_agp_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) radeon_agp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rv515_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rv515_debugfs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) r = rv370_pcie_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) rv515_set_safe_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) r = rv515_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Somethings want wront with the accel init stop accel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(rdev->dev, "Disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) rv370_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int index_reg = 0x6578 + crtc->crtc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int data_reg = 0x657c + crtc->crtc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) WREG32(0x659C + crtc->crtc_offset, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) WREG32(0x6594 + crtc->crtc_offset, 0x705);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) WREG32(0x65D8 + crtc->crtc_offset, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) WREG32(0x65B0 + crtc->crtc_offset, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) WREG32(0x65C0 + crtc->crtc_offset, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) WREG32(0x65D4 + crtc->crtc_offset, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) WREG32(index_reg, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) WREG32(data_reg, 0x841880A8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) WREG32(index_reg, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) WREG32(data_reg, 0x84208680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) WREG32(index_reg, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) WREG32(data_reg, 0xBFF880B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) WREG32(index_reg, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) WREG32(data_reg, 0x83D88088);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) WREG32(index_reg, 0x101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) WREG32(data_reg, 0x84608680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) WREG32(index_reg, 0x102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) WREG32(data_reg, 0xBFF080D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) WREG32(index_reg, 0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) WREG32(data_reg, 0x83988068);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) WREG32(index_reg, 0x201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) WREG32(data_reg, 0x84A08680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) WREG32(index_reg, 0x202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) WREG32(data_reg, 0xBFF080F8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) WREG32(index_reg, 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) WREG32(data_reg, 0x83588058);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) WREG32(index_reg, 0x301);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) WREG32(data_reg, 0x84E08660);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) WREG32(index_reg, 0x302);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) WREG32(data_reg, 0xBFF88120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) WREG32(index_reg, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) WREG32(data_reg, 0x83188040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) WREG32(index_reg, 0x401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) WREG32(data_reg, 0x85008660);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) WREG32(index_reg, 0x402);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) WREG32(data_reg, 0xBFF88150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) WREG32(index_reg, 0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) WREG32(data_reg, 0x82D88030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) WREG32(index_reg, 0x501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) WREG32(data_reg, 0x85408640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) WREG32(index_reg, 0x502);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) WREG32(data_reg, 0xBFF88180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) WREG32(index_reg, 0x600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) WREG32(data_reg, 0x82A08018);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) WREG32(index_reg, 0x601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) WREG32(data_reg, 0x85808620);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) WREG32(index_reg, 0x602);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) WREG32(data_reg, 0xBFF081B8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) WREG32(index_reg, 0x700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) WREG32(data_reg, 0x82608010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) WREG32(index_reg, 0x701);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) WREG32(data_reg, 0x85A08600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) WREG32(index_reg, 0x702);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) WREG32(data_reg, 0x800081F0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) WREG32(index_reg, 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) WREG32(data_reg, 0x8228BFF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) WREG32(index_reg, 0x801);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) WREG32(data_reg, 0x85E085E0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) WREG32(index_reg, 0x802);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) WREG32(data_reg, 0xBFF88228);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) WREG32(index_reg, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) WREG32(data_reg, 0x82A8BF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) WREG32(index_reg, 0x10001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) WREG32(data_reg, 0x82A08CC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) WREG32(index_reg, 0x10002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) WREG32(data_reg, 0x8008BEF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) WREG32(index_reg, 0x10100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) WREG32(data_reg, 0x81F0BF28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) WREG32(index_reg, 0x10101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) WREG32(data_reg, 0x83608CA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) WREG32(index_reg, 0x10102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) WREG32(data_reg, 0x8018BED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) WREG32(index_reg, 0x10200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) WREG32(data_reg, 0x8148BF38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) WREG32(index_reg, 0x10201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) WREG32(data_reg, 0x84408C80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) WREG32(index_reg, 0x10202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) WREG32(data_reg, 0x8008BEB8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) WREG32(index_reg, 0x10300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) WREG32(data_reg, 0x80B0BF78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) WREG32(index_reg, 0x10301);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) WREG32(data_reg, 0x85008C20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) WREG32(index_reg, 0x10302);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) WREG32(data_reg, 0x8020BEA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) WREG32(index_reg, 0x10400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) WREG32(data_reg, 0x8028BF90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) WREG32(index_reg, 0x10401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) WREG32(data_reg, 0x85E08BC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) WREG32(index_reg, 0x10402);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) WREG32(data_reg, 0x8018BE90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) WREG32(index_reg, 0x10500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) WREG32(data_reg, 0xBFB8BFB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) WREG32(index_reg, 0x10501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) WREG32(data_reg, 0x86C08B40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) WREG32(index_reg, 0x10502);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) WREG32(data_reg, 0x8010BE90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) WREG32(index_reg, 0x10600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) WREG32(data_reg, 0xBF58BFC8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) WREG32(index_reg, 0x10601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) WREG32(data_reg, 0x87A08AA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) WREG32(index_reg, 0x10602);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) WREG32(data_reg, 0x8010BE98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) WREG32(index_reg, 0x10700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) WREG32(data_reg, 0xBF10BFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) WREG32(index_reg, 0x10701);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) WREG32(data_reg, 0x886089E0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) WREG32(index_reg, 0x10702);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) WREG32(data_reg, 0x8018BEB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) WREG32(index_reg, 0x10800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) WREG32(data_reg, 0xBED8BFE8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) WREG32(index_reg, 0x10801);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) WREG32(data_reg, 0x89408940);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) WREG32(index_reg, 0x10802);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) WREG32(data_reg, 0xBFE8BED8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) WREG32(index_reg, 0x20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) WREG32(index_reg, 0x20001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) WREG32(data_reg, 0x90008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) WREG32(index_reg, 0x20002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) WREG32(index_reg, 0x20003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) WREG32(index_reg, 0x20100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) WREG32(data_reg, 0x80108000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) WREG32(index_reg, 0x20101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) WREG32(data_reg, 0x8FE0BF70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) WREG32(index_reg, 0x20102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) WREG32(data_reg, 0xBFE880C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) WREG32(index_reg, 0x20103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) WREG32(index_reg, 0x20200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) WREG32(data_reg, 0x8018BFF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) WREG32(index_reg, 0x20201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) WREG32(data_reg, 0x8F80BF08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) WREG32(index_reg, 0x20202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) WREG32(data_reg, 0xBFD081A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) WREG32(index_reg, 0x20203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) WREG32(data_reg, 0xBFF88000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) WREG32(index_reg, 0x20300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) WREG32(data_reg, 0x80188000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) WREG32(index_reg, 0x20301);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) WREG32(data_reg, 0x8EE0BEC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) WREG32(index_reg, 0x20302);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) WREG32(data_reg, 0xBFB082A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) WREG32(index_reg, 0x20303);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) WREG32(index_reg, 0x20400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) WREG32(data_reg, 0x80188000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) WREG32(index_reg, 0x20401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) WREG32(data_reg, 0x8E00BEA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) WREG32(index_reg, 0x20402);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) WREG32(data_reg, 0xBF8883C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) WREG32(index_reg, 0x20403);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) WREG32(index_reg, 0x20500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) WREG32(data_reg, 0x80188000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) WREG32(index_reg, 0x20501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) WREG32(data_reg, 0x8D00BE90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) WREG32(index_reg, 0x20502);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) WREG32(data_reg, 0xBF588500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) WREG32(index_reg, 0x20503);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) WREG32(data_reg, 0x80008008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) WREG32(index_reg, 0x20600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) WREG32(data_reg, 0x80188000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) WREG32(index_reg, 0x20601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) WREG32(data_reg, 0x8BC0BE98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) WREG32(index_reg, 0x20602);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) WREG32(data_reg, 0xBF308660);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) WREG32(index_reg, 0x20603);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) WREG32(data_reg, 0x80008008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) WREG32(index_reg, 0x20700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) WREG32(data_reg, 0x80108000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) WREG32(index_reg, 0x20701);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) WREG32(data_reg, 0x8A80BEB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) WREG32(index_reg, 0x20702);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) WREG32(data_reg, 0xBF0087C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) WREG32(index_reg, 0x20703);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) WREG32(data_reg, 0x80008008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) WREG32(index_reg, 0x20800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) WREG32(data_reg, 0x80108000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) WREG32(index_reg, 0x20801);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) WREG32(data_reg, 0x8920BED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) WREG32(index_reg, 0x20802);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) WREG32(data_reg, 0xBED08920);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) WREG32(index_reg, 0x20803);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) WREG32(data_reg, 0x80008010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) WREG32(index_reg, 0x30000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) WREG32(data_reg, 0x90008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) WREG32(index_reg, 0x30001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) WREG32(data_reg, 0x80008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) WREG32(index_reg, 0x30100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) WREG32(data_reg, 0x8FE0BF90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) WREG32(index_reg, 0x30101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) WREG32(data_reg, 0xBFF880A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) WREG32(index_reg, 0x30200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) WREG32(data_reg, 0x8F60BF40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) WREG32(index_reg, 0x30201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) WREG32(data_reg, 0xBFE88180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) WREG32(index_reg, 0x30300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) WREG32(data_reg, 0x8EC0BF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) WREG32(index_reg, 0x30301);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) WREG32(data_reg, 0xBFC88280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) WREG32(index_reg, 0x30400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) WREG32(data_reg, 0x8DE0BEE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) WREG32(index_reg, 0x30401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) WREG32(data_reg, 0xBFA083A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) WREG32(index_reg, 0x30500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) WREG32(data_reg, 0x8CE0BED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) WREG32(index_reg, 0x30501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) WREG32(data_reg, 0xBF7884E0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) WREG32(index_reg, 0x30600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) WREG32(data_reg, 0x8BA0BED8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) WREG32(index_reg, 0x30601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) WREG32(data_reg, 0xBF508640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) WREG32(index_reg, 0x30700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) WREG32(data_reg, 0x8A60BEE8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) WREG32(index_reg, 0x30701);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) WREG32(data_reg, 0xBF2087A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) WREG32(index_reg, 0x30800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) WREG32(data_reg, 0x8900BF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) WREG32(index_reg, 0x30801);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) WREG32(data_reg, 0xBF008900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct rv515_watermark {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 lb_request_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) fixed20_12 num_line_pair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) fixed20_12 estimated_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fixed20_12 worst_case_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) fixed20_12 consumption_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) fixed20_12 active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) fixed20_12 dbpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fixed20_12 priority_mark_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fixed20_12 priority_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fixed20_12 sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct radeon_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct rv515_watermark *wm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) bool low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct drm_display_mode *mode = &crtc->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fixed20_12 a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fixed20_12 sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 selected_sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (!crtc->base.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* FIXME: wouldn't it better to set priority mark to maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) wm->lb_request_fifo_depth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* rv6xx, rv7xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if ((rdev->family >= CHIP_RV610) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) selected_sclk = radeon_dpm_get_sclk(rdev, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) selected_sclk = rdev->pm.current_sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* sclk in Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) a.full = dfixed_const(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sclk.full = dfixed_const(selected_sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) sclk.full = dfixed_div(sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (crtc->vsc.full > dfixed_const(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) wm->num_line_pair.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) wm->num_line_pair.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) b.full = dfixed_const(mode->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) c.full = dfixed_const(256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) a.full = dfixed_div(b, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (a.full < dfixed_const(4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) wm->lb_request_fifo_depth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Determine consumption rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * vtaps = number of vertical taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * vsc = vertical scaling ratio, defined as source/destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * hsc = horizontal scaling ration, defined as source/destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) a.full = dfixed_const(mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) b.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) a.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pclk.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (crtc->rmx_type != RMX_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) b.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (crtc->vsc.full > b.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) b.full = crtc->vsc.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) b.full = dfixed_mul(b, crtc->hsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) c.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) b.full = dfixed_div(b, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) consumption_time.full = dfixed_div(pclk, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) consumption_time.full = pclk.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) a.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) wm->consumption_rate.full = dfixed_div(a, consumption_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Determine line time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * LineTime = total time for one line of displayhtotal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * LineTime = total number of horizontal pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * pclk = pixel clock period(ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) a.full = dfixed_const(crtc->base.mode.crtc_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) line_time.full = dfixed_mul(a, pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Determine active time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * ActiveTime = time of active region of display within one line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * hactive = total number of horizontal active pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * htotal = total number of horizontal pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) a.full = dfixed_const(crtc->base.mode.crtc_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) wm->active_time.full = dfixed_mul(line_time, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) wm->active_time.full = dfixed_div(wm->active_time, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Determine chunk time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * ChunkTime = the time it takes the DCP to send one chunk of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * to the LB which consists of pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * sclk = system clock(Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) a.full = dfixed_const(600 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) chunk_time.full = dfixed_div(a, sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) read_delay_latency.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Determine the worst case latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * WorstCaseLatency = worst case time from urgent to when the MC starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * to return data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * READ_DELAY_IDLE_MAX = constant of 1us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * ChunkTime = time it takes the DCP to send one chunk of data to the LB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * which consists of pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (dfixed_trunc(wm->num_line_pair) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) a.full = dfixed_const(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) wm->worst_case_latency.full += read_delay_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Determine the tolerable latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * TolerableLatency = Any given request has only 1 line time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * for the data to be returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * LBRequestFifoDepth = Number of chunk requests the LB can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * put into the request FIFO for a display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * LineTime = total time for one line of display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * ChunkTime = the time it takes the DCP to send one chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * of data to the LB which consists of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) tolerable_latency.full = line_time.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) tolerable_latency.full = line_time.full - tolerable_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* We assume worst case 32bits (4 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) wm->dbpp.full = dfixed_const(2 * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Determine the maximum priority mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * width = viewport width in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Determine estimated width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) estimated_width.full = dfixed_div(estimated_width, consumption_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) wm->priority_mark.full = wm->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) wm->priority_mark.full = dfixed_div(estimated_width, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static void rv515_compute_mode_priority(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct rv515_watermark *wm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct rv515_watermark *wm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct drm_display_mode *mode0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u32 *d1mode_priority_a_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u32 *d2mode_priority_a_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) fixed20_12 priority_mark02, priority_mark12, fill_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fixed20_12 a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (mode0 && mode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (dfixed_trunc(wm0->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) a.full = wm0->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (dfixed_trunc(wm1->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) b.full = wm1->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) a.full += b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) fill_rate.full = dfixed_div(wm0->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (wm0->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) b.full = wm0->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) b.full = dfixed_mul(b, wm0->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) b.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) priority_mark02.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (wm1->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) b.full = wm1->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) b.full = dfixed_mul(b, wm1->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) b.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) priority_mark12.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (wm0->priority_mark.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) priority_mark02.full = wm0->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (wm0->priority_mark_max.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) priority_mark02.full = wm0->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (wm1->priority_mark.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) priority_mark12.full = wm1->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (wm1->priority_mark_max.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) priority_mark12.full = wm1->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (rdev->disp_priority == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else if (mode0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (dfixed_trunc(wm0->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) a.full = wm0->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) fill_rate.full = dfixed_div(wm0->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (wm0->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) b.full = wm0->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) b.full = dfixed_mul(b, wm0->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) b.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) priority_mark02.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) b.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (wm0->priority_mark.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) priority_mark02.full = wm0->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (wm0->priority_mark_max.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) priority_mark02.full = wm0->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (rdev->disp_priority == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) } else if (mode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (dfixed_trunc(wm1->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) a.full = wm1->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) fill_rate.full = dfixed_div(wm1->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (wm1->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) b.full = wm1->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) b.full = dfixed_mul(b, wm1->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) b.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) priority_mark12.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (wm1->priority_mark.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) priority_mark12.full = wm1->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (wm1->priority_mark_max.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) priority_mark12.full = wm1->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (rdev->disp_priority == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct drm_display_mode *mode0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct drm_display_mode *mode1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct rv515_watermark wm0_high, wm0_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct rv515_watermark wm1_high, wm1_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (rdev->mode_info.crtcs[0]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) mode0 = &rdev->mode_info.crtcs[0]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (rdev->mode_info.crtcs[1]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mode1 = &rdev->mode_info.crtcs[1]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rs690_line_buffer_adjust(rdev, mode0, mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) tmp = wm0_high.lb_request_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) tmp |= wm1_high.lb_request_fifo_depth << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rv515_compute_mode_priority(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) &wm0_high, &wm1_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mode0, mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) rv515_compute_mode_priority(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &wm0_low, &wm1_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mode0, mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) void rv515_bandwidth_update(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct drm_display_mode *mode0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct drm_display_mode *mode1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!rdev->mode_info.mode_config_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) radeon_update_display_priority(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (rdev->mode_info.crtcs[0]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mode0 = &rdev->mode_info.crtcs[0]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (rdev->mode_info.crtcs[1]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) mode1 = &rdev->mode_info.crtcs[1]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * Set display0/1 priority up in the memory controller for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * modes if the user specifies HIGH for displaypriority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if ((rdev->disp_priority == 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) (rdev->family == CHIP_RV515)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) tmp = RREG32_MC(MC_MISC_LAT_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) tmp &= ~MC_DISP1R_INIT_LAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) tmp &= ~MC_DISP0R_INIT_LAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (mode1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (mode0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) WREG32_MC(MC_MISC_LAT_TIMER, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) rv515_bandwidth_avivo_update(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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