^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef __RS780D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __RS780D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) # define SPLL_REF_DIV(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # define SPLL_REF_DIV_MASK (7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define SPLL_REF_DIV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define SPLL_FB_DIV(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define SPLL_FB_DIV_MASK (0xff << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define SPLL_FB_DIV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define SPLL_PULSEEN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define SPLL_PULSENUM(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define SPLL_PULSENUM_MASK (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define SPLL_SW_HILEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define SPLL_SW_HILEN_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define SPLL_SW_HILEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define SPLL_SW_LOLEN(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define SPLL_SW_LOLEN_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define SPLL_SW_LOLEN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define SPLL_DIVEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define SPLL_BYPASS_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define SPLL_CHG_STATUS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # define SPLL_CTLREQ (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define SPLL_CTLACK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* RS780/RS880 PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FVTHROT_CNTRL_REG 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MINIMUM_CIP(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MINIMUM_CIP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MINIMUM_CIP_MASK 0x1fffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REFRESH_RATE_DIVISOR(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REFRESH_RATE_DIVISOR_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ENABLE_FV_THROT (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ENABLE_FV_UPDATE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TREND_SEL_MODE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FORCE_TREND_SEL (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ENABLE_FV_THROT_IO (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FVTHROT_TARGET_REG 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TARGET_IDLE_COUNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TARGET_IDLE_COUNT_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TARGET_IDLE_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FVTHROT_CB1 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FVTHROT_CB2 0x300c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FVTHROT_CB3 0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FVTHROT_CB4 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FVTHROT_UTC0 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FVTHROT_UTC1 0x301c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FVTHROT_UTC2 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FVTHROT_UTC3 0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FVTHROT_UTC4 0x3028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FVTHROT_DTC0 0x302c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FVTHROT_DTC1 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FVTHROT_DTC2 0x3034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FVTHROT_DTC3 0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FVTHROT_DTC4 0x303c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FVTHROT_FBDIV_REG0 0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MIN_FEEDBACK_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MIN_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MIN_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAX_FEEDBACK_DIV(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAX_FEEDBACK_DIV_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX_FEEDBACK_DIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FVTHROT_FBDIV_REG1 0x3044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX_FEEDBACK_STEP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX_FEEDBACK_STEP_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAX_FEEDBACK_STEP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STARTING_FEEDBACK_DIV(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STARTING_FEEDBACK_DIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FORCE_FEEDBACK_DIV (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FVTHROT_FBDIV_REG2 0x3048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FORCED_FEEDBACK_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FORCED_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FORCED_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FB_DIV_TIMER_VAL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FB_DIV_TIMER_VAL_MASK (0xffff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FB_DIV_TIMER_VAL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FVTHROT_FB_US_REG0 0x304c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FVTHROT_FB_US_REG1 0x3050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FVTHROT_FB_DS_REG0 0x3054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FVTHROT_FB_DS_REG1 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FVTHROT_PWM_CTRL_REG0 0x305c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STARTING_PWM_HIGHTIME(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STARTING_PWM_HIGHTIME_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STARTING_PWM_HIGHTIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FORCE_STARTING_PWM_HIGHTIME (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INVERT_PWM_WAVEFORM (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FVTHROT_PWM_CTRL_REG1 0x3060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MIN_PWM_HIGHTIME(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MIN_PWM_HIGHTIME_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MIN_PWM_HIGHTIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MAX_PWM_HIGHTIME(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAX_PWM_HIGHTIME_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAX_PWM_HIGHTIME_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FVTHROT_PWM_US_REG0 0x3064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FVTHROT_PWM_US_REG1 0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FVTHROT_PWM_DS_REG0 0x306c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FVTHROT_PWM_DS_REG1 0x3070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FVTHROT_STATUS_REG0 0x3074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CURRENT_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CURRENT_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FVTHROT_STATUS_REG1 0x3078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FVTHROT_STATUS_REG2 0x307c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CG_INTGFX_MISC 0x3080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FVTHROT_VBLANK_SEL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RANGE0_PWM(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RANGE0_PWM_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RANGE0_PWM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RANGE1_PWM(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RANGE1_PWM_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RANGE1_PWM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RANGE2_PWM(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RANGE2_PWM_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RANGE2_PWM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RANGE3_PWM(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RANGE3_PWM_MASK (0xfff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RANGE3_PWM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GFX_MACRO_BYPASS_CNTL 0x30c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SPLL_BYPASS_CNTL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define UPLL_BYPASS_CNTL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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