^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "radeon_audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "rs690d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int rs690_mc_wait_for_idle(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* read MC_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (G_000090_MC_SYSTEM_IDLE(tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void rs690_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* FIXME: is this correct ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) r420_pipes_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (rs690_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) union igp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct _ATOM_INTEGRATED_SYSTEM_INFO info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void rs690_pm_info(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) union igp_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) uint16_t data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint8_t frev, crev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) fixed20_12 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &frev, &crev, &data_offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Get various system informations from bios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (crev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp.full = dfixed_const(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (le16_to_cpu(info->info.usK8MemoryClock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else if (rdev->clock.default_mclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rdev->pm.igp_system_mclk.full = dfixed_const(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmp.full = dfixed_const(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else if (rdev->clock.default_mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rdev->pm.igp_system_mclk.full = dfixed_const(66700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* We assume the slower possible clock ie worst case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rdev->pm.igp_system_mclk.full = dfixed_const(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rdev->pm.igp_ht_link_width.full = dfixed_const(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DRM_ERROR("No integrated system info for your GPU, using safe default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* We assume the slower possible clock ie worst case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) rdev->pm.igp_system_mclk.full = dfixed_const(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rdev->pm.igp_ht_link_width.full = dfixed_const(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DRM_ERROR("No integrated system info for your GPU, using safe default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Compute various bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tmp.full = dfixed_const(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * = ht_clk * ht_width / 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tmp.full = dfixed_const(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rdev->pm.igp_ht_link_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (tmp.full < rdev->pm.max_bandwidth.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* HT link is a limiting factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rdev->pm.max_bandwidth.full = tmp.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * = (sideport_clk * 14) / 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tmp.full = dfixed_const(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tmp.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void rs690_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint32_t h_addr, l_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long long k8_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rs400_gart_adjust_size(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rdev->mc.visible_vram_size = rdev->mc.aper_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) base = G_000100_MC_FB_START(base) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Some boards seem to be configured for 128MB of sideport memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * but really only have 64MB. Just skip the sideport and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * UMA memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (rdev->mc.igp_sideport_enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) base += 128 * 1024 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rdev->mc.real_vram_size -= 128 * 1024 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Use K8 direct mapping for fast fb access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rdev->fastfb_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * memory is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (unsigned long long)rdev->mc.aper_base, k8_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rdev->mc.aper_base = (resource_size_t)k8_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rdev->fastfb_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rs690_pm_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) radeon_vram_location(rdev, &rdev->mc, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) radeon_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void rs690_line_buffer_adjust(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Guess line buffer size to be 8192 pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 lb_size = 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Line Buffer Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * There is a single line buffer shared by both display controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * the display controllers. The paritioning can either be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * manually or via one of four preset allocations specified in bits 1:0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * 0 - line buffer is divided in half and shared between crtc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 2 - D1 gets the whole buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * allocation mode. In manual allocation mode, D1 always starts at 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (mode1 && mode2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (mode1->hdisplay > mode2->hdisplay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (mode1->hdisplay > 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else if (mode2->hdisplay > mode1->hdisplay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (mode2->hdisplay > 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else if (mode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else if (mode2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Save number of lines the linebuffer leads before the scanout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (mode1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct rs690_watermark {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 lb_request_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) fixed20_12 num_line_pair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fixed20_12 estimated_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) fixed20_12 worst_case_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) fixed20_12 consumption_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) fixed20_12 active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fixed20_12 dbpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) fixed20_12 priority_mark_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) fixed20_12 priority_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) fixed20_12 sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct radeon_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct rs690_watermark *wm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bool low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct drm_display_mode *mode = &crtc->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) fixed20_12 a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) fixed20_12 sclk, core_bandwidth, max_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 selected_sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!crtc->base.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* FIXME: wouldn't it better to set priority mark to maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) wm->lb_request_fifo_depth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) selected_sclk = radeon_dpm_get_sclk(rdev, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) selected_sclk = rdev->pm.current_sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* sclk in Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) a.full = dfixed_const(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sclk.full = dfixed_const(selected_sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sclk.full = dfixed_div(sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* core_bandwidth = sclk(Mhz) * 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (crtc->vsc.full > dfixed_const(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) wm->num_line_pair.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) wm->num_line_pair.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) b.full = dfixed_const(mode->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) c.full = dfixed_const(256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) a.full = dfixed_div(b, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (a.full < dfixed_const(4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) wm->lb_request_fifo_depth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Determine consumption rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * vtaps = number of vertical taps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * vsc = vertical scaling ratio, defined as source/destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * hsc = horizontal scaling ration, defined as source/destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) a.full = dfixed_const(mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) b.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) a.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pclk.full = dfixed_div(b, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (crtc->rmx_type != RMX_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) b.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (crtc->vsc.full > b.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) b.full = crtc->vsc.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) b.full = dfixed_mul(b, crtc->hsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) c.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) b.full = dfixed_div(b, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) consumption_time.full = dfixed_div(pclk, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) consumption_time.full = pclk.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) a.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) wm->consumption_rate.full = dfixed_div(a, consumption_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Determine line time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * LineTime = total time for one line of displayhtotal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * LineTime = total number of horizontal pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * pclk = pixel clock period(ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) a.full = dfixed_const(crtc->base.mode.crtc_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) line_time.full = dfixed_mul(a, pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Determine active time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * ActiveTime = time of active region of display within one line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * hactive = total number of horizontal active pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * htotal = total number of horizontal pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) a.full = dfixed_const(crtc->base.mode.crtc_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) wm->active_time.full = dfixed_mul(line_time, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) wm->active_time.full = dfixed_div(wm->active_time, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Maximun bandwidth is the minimun bandwidth of all component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) max_bandwidth = core_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (rdev->mc.igp_sideport_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rdev->pm.sideport_bandwidth.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) max_bandwidth = rdev->pm.sideport_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) read_delay_latency.full = dfixed_const(370 * 800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) read_delay_latency.full = dfixed_div(read_delay_latency, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) read_delay_latency.full = dfixed_mul(read_delay_latency, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rdev->pm.k8_bandwidth.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) max_bandwidth = rdev->pm.k8_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rdev->pm.ht_bandwidth.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) max_bandwidth = rdev->pm.ht_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) read_delay_latency.full = dfixed_const(5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sclk.full = dfixed_mul(max_bandwidth, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sclk.full = dfixed_div(a, sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Determine chunk time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * ChunkTime = the time it takes the DCP to send one chunk of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * to the LB which consists of pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * sclk = system clock(ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) a.full = dfixed_const(256 * 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) chunk_time.full = dfixed_mul(sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) a.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) chunk_time.full = dfixed_div(chunk_time, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Determine the worst case latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * WorstCaseLatency = worst case time from urgent to when the MC starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * to return data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * READ_DELAY_IDLE_MAX = constant of 1us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * ChunkTime = time it takes the DCP to send one chunk of data to the LB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * which consists of pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (dfixed_trunc(wm->num_line_pair) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) a.full = dfixed_const(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) wm->worst_case_latency.full += read_delay_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) a.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) wm->worst_case_latency.full += read_delay_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Determine the tolerable latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * TolerableLatency = Any given request has only 1 line time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * for the data to be returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * LBRequestFifoDepth = Number of chunk requests the LB can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * put into the request FIFO for a display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * LineTime = total time for one line of display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * ChunkTime = the time it takes the DCP to send one chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * of data to the LB which consists of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * pipeline delay and inter chunk gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tolerable_latency.full = line_time.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tolerable_latency.full = line_time.full - tolerable_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* We assume worst case 32bits (4 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) wm->dbpp.full = dfixed_const(4 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Determine the maximum priority mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * width = viewport width in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Determine estimated width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) estimated_width.full = dfixed_div(estimated_width, consumption_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) wm->priority_mark.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) a.full = dfixed_const(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) wm->priority_mark.full = dfixed_div(estimated_width, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void rs690_compute_mode_priority(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct rs690_watermark *wm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct rs690_watermark *wm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct drm_display_mode *mode0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 *d1mode_priority_a_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 *d2mode_priority_a_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fixed20_12 priority_mark02, priority_mark12, fill_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fixed20_12 a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (mode0 && mode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (dfixed_trunc(wm0->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) a.full = wm0->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (dfixed_trunc(wm1->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) b.full = wm1->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) a.full += b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fill_rate.full = dfixed_div(wm0->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (wm0->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) b.full = wm0->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) b.full = dfixed_mul(b, wm0->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) a.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (wm1->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) b.full = wm1->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) b.full = dfixed_mul(b, wm1->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) a.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (wm0->priority_mark.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) priority_mark02.full = wm0->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (wm0->priority_mark_max.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) priority_mark02.full = wm0->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (wm1->priority_mark.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) priority_mark12.full = wm1->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (wm1->priority_mark_max.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) priority_mark12.full = wm1->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (rdev->disp_priority == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } else if (mode0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (dfixed_trunc(wm0->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) a.full = wm0->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) fill_rate.full = dfixed_div(wm0->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (wm0->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) b.full = wm0->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) b.full = dfixed_mul(b, wm0->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) a.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) a.full = dfixed_mul(wm0->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) wm0->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) priority_mark02.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (wm0->priority_mark.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) priority_mark02.full = wm0->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (wm0->priority_mark_max.full > priority_mark02.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) priority_mark02.full = wm0->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (rdev->disp_priority == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else if (mode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (dfixed_trunc(wm1->dbpp) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) a.full = wm1->num_line_pair.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) fill_rate.full = dfixed_div(wm1->sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (wm1->consumption_rate.full > fill_rate.full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) b.full = wm1->consumption_rate.full - fill_rate.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) b.full = dfixed_mul(b, wm1->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) a.full = a.full + b.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) a.full = dfixed_mul(wm1->worst_case_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) wm1->consumption_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) b.full = dfixed_const(16 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) priority_mark12.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (wm1->priority_mark.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) priority_mark12.full = wm1->priority_mark.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (wm1->priority_mark_max.full > priority_mark12.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) priority_mark12.full = wm1->priority_mark_max.full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (rdev->disp_priority == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) void rs690_bandwidth_update(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct drm_display_mode *mode0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct drm_display_mode *mode1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct rs690_watermark wm0_high, wm0_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct rs690_watermark wm1_high, wm1_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!rdev->mode_info.mode_config_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) radeon_update_display_priority(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (rdev->mode_info.crtcs[0]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mode0 = &rdev->mode_info.crtcs[0]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (rdev->mode_info.crtcs[1]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mode1 = &rdev->mode_info.crtcs[1]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Set display0/1 priority up in the memory controller for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * modes if the user specifies HIGH for displaypriority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if ((rdev->disp_priority == 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tmp &= C_000104_MC_DISP0R_INIT_LAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tmp &= C_000104_MC_DISP1R_INIT_LAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (mode0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (mode1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rs690_line_buffer_adjust(rdev, mode0, mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) WREG32(R_006C9C_DCP_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) WREG32(R_006C9C_DCP_CONTROL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tmp = (wm0_high.lb_request_fifo_depth - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rs690_compute_mode_priority(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &wm0_high, &wm1_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mode0, mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rs690_compute_mode_priority(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) &wm0_low, &wm1_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mode0, mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) uint32_t r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) r = RREG32(R_00007C_MC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) S_000078_MC_IND_WR_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) WREG32(R_00007C_MC_DATA, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) WREG32(R_000078_MC_INDEX, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void rs690_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct rv515_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Stops all mc clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rv515_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Wait for mc idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (rs690_mc_wait_for_idle(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Program MC, should be a 32bits limited address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) WREG32_MC(R_000100_MCCFG_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) WREG32(R_000134_HDP_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) rv515_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int rs690_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) rs690_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Resume clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Initialize GPU configuration (# pipes, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) rs690_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Initialize GART (initialize after TTM so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * memory through TTM but finalize after TTM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) r = rs400_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rs600_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* 1M ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) r = r100_cp_init(rdev, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) r = radeon_audio_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_err(rdev->dev, "failed initializing audio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int rs690_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Make sur GART are not working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rs400_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Resume clock before doing reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Resume clock after posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) r = rs690_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int rs690_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) radeon_audio_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) r100_cp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rs600_irq_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rs400_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) void rs690_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) radeon_audio_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rs400_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int rs690_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Disable VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) rv515_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) radeon_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* restore some register to sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) r100_restore_sanity(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* TODO: disable VGA need to use VGA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* BIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_warn(rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (radeon_boot_test_post_card(rdev) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rs690_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) rv515_debugfs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) r = rs400_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) rs600_set_safe_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) r = rs690_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Somethings want wront with the accel init stop accel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_err(rdev->dev, "Disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rs400_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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