^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef __RS600D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __RS600D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R_000040_GEN_INT_CNTL 0x000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define C_000040_I2C_INT_EN 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define C_000040_GUI_IDLE 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define C_000040_VIPH_INT_EN 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define C_000040_SW_INT_EN 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define C_000040_GEYSERVILLE 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define C_000040_DVI_I2C_INT 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define C_000040_GUIDMA 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define C_000040_VIDDMA 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R_000044_GEN_INT_STATUS 0x000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define C_000044_VGA_INT_STAT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define C_000044_I2C_INT 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define C_000044_VIPH_INT 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S_000044_SW_INT(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define C_000044_SW_INT 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define C_000044_SW_INT_SET 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define C_000044_IDCT_INT_STAT 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define C_000044_GUIDMA_STAT 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define C_000044_VIDDMA_STAT 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R_00004C_BUS_CNTL 0x00004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define R_000070_MC_IND_INDEX 0x000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define C_000070_MC_IND_ADDR 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define C_000070_MC_IND_WR_EN 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define C_000070_MC_IND_RD_INV 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define R_000074_MC_IND_DATA 0x000074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define C_000074_MC_IND_DATA 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define R_0000F0_RBBM_SOFT_RESET 0x0000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define R_000134_HDP_FB_LOCATION 0x000134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define C_000134_HDP_FB_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define R_0007C0_CP_STAT 0x0007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define C_0007C0_MRU_BUSY 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define C_0007C0_MWU_BUSY 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define C_0007C0_CSI_BUSY 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define C_0007C0_CP_BUSY 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define R_000E40_RBBM_STATUS 0x000E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define C_000E40_E2_BUSY 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define C_000E40_RB2D_BUSY 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define C_000E40_RB3D_BUSY 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define C_000E40_VAP_BUSY 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define C_000E40_RE_BUSY 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define C_000E40_TAM_BUSY 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define C_000E40_TDM_BUSY 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define C_000E40_PB_BUSY 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define C_000E40_TIM_BUSY 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define C_000E40_GA_BUSY 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define C_000E40_CBA2D_BUSY 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define R_006534_D1MODE_VBLANK_STATUS 0x006534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define R_006540_DxMODE_INT_MASK 0x006540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define R_007828_DACA_AUTODETECT_CONTROL 0x007828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define R_007404_HDMI0_STATUS 0x007404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define S_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define G_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define C_007404_HDMI0_AZ_FORMAT_WTRIG 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define R_007408_HDMI0_AUDIO_PACKET_CONTROL 0x007408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* MC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define R_000000_MC_STATUS 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define C_000000_MC_IDLE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define R_000004_MC_FB_LOCATION 0x000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define C_000004_MC_FB_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define C_000004_MC_FB_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define R_000005_MC_AGP_LOCATION 0x000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define C_000005_MC_AGP_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define C_000005_MC_AGP_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define R_000006_AGP_BASE 0x000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define C_000006_AGP_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define R_000007_AGP_BASE_2 0x000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define R_000009_MC_CNTL1 0x000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* FIXME don't know the various field size need feedback from AMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define R_000100_MC_PT0_CNTL 0x000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define C_000100_ENABLE_PT 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define V_000102_PAGE_TABLE_FLAT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* R600 documentation suggest that this should be a number of pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define R_006548_D1MODE_PRIORITY_A_CNT 0x006548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* PLL regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define GENERAL_PWRMGT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define MOBILE_SU (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DYN_PWRMGT_SCLK_LENGTH 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define POWER_D1_SCLK_HILEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define POWER_D1_SCLK_LOLEN(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define STATIC_SCREEN_HILEN(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define STATIC_SCREEN_LOLEN(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define DYN_SCLK_VOL_CNTL 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define IO_CG_VOLTAGE_DROP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define VOLTAGE_DROP_SYNC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define VOLTAGE_DELAY_SEL(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define HDP_DYN_CNTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define HDP_FORCEON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define MC_HOST_DYN_CNTL 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define MC_HOST_FORCEON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DYN_BACKBIAS_CNTL 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define IO_CG_BACKBIAS_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* mmreg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define PWRDN_WAIT_BUSY_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define PWRDN_WAIT_PWRSEQ_OFF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define PWRDN_WAIT_PPLL_OFF (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define PWRUP_WAIT_PPLL_ON (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define PWRUP_WAIT_MEM_INIT_DONE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define PM_ASSERT_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define PM_PWRDN_PPLL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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