^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "rs400d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* This files gather functions specifics to : rs400,rs480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void rs400_gart_adjust_size(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Check gart size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) switch (rdev->mc.gtt_size/(1024*1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DRM_ERROR("Unable to use IGP GART size %uM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (unsigned)(rdev->mc.gtt_size >> 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DRM_ERROR("Forcing to 32M GART size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) rdev->mc.gtt_size = 32 * 1024 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void rs400_gart_tlb_flush(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int timeout = rdev->usec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } while (timeout > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int rs400_gart_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (rdev->gart.ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) WARN(1, "RS400 GART already initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Check gart size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch(rdev->mc.gtt_size / (1024 * 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Initialize common gart structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) r = radeon_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (rs400_debugfs_pcie_gart_info_init(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return radeon_gart_table_ram_alloc(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int rs400_gart_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) uint32_t size_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Check gart size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch(rdev->mc.gtt_size / (1024 * 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_reg = RS480_VA_SIZE_32MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) size_reg = RS480_VA_SIZE_64MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) size_reg = RS480_VA_SIZE_128MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) size_reg = RS480_VA_SIZE_256MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) size_reg = RS480_VA_SIZE_512MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) size_reg = RS480_VA_SIZE_1GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) size_reg = RS480_VA_SIZE_2GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* It should be fine to program it to max value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) WREG32(RS480_AGP_BASE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) WREG32(RADEON_BUS_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) WREG32(RADEON_MC_AGP_LOCATION, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) WREG32(RADEON_BUS_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Table should be in 32bits address space so ignore bits above. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tmp = (u32)rdev->gart.table_addr & 0xfffff000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) WREG32_MC(RS480_GART_BASE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* TODO: more tweaking here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WREG32_MC(RS480_GART_FEATURE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (RS480_TLB_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Disable snooping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) WREG32_MC(RS480_AGP_MODE_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Disable AGP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tmp = RREG32_MC(RS480_MC_MISC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) WREG32_MC(RS480_MC_MISC_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tmp = RREG32_MC(RS480_MC_MISC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp |= RS480_GART_INDEX_REG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) WREG32_MC(RS480_MC_MISC_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Enable gart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rs400_gart_tlb_flush(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (unsigned)(rdev->mc.gtt_size >> 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (unsigned long long)rdev->gart.table_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rdev->gart.ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void rs400_gart_disable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void rs400_gart_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) radeon_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rs400_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) radeon_gart_table_ram_free(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RS400_PTE_UNSNOOPED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RS400_PTE_WRITEABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RS400_PTE_READABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint32_t entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) entry = (lower_32_bits(addr) & PAGE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ((upper_32_bits(addr) & 0xff) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (flags & RADEON_GART_PAGE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) entry |= RS400_PTE_READABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (flags & RADEON_GART_PAGE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) entry |= RS400_PTE_WRITEABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!(flags & RADEON_GART_PAGE_SNOOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) entry |= RS400_PTE_UNSNOOPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) uint64_t entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 *gtt = rdev->gart.ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) gtt[i] = cpu_to_le32(lower_32_bits(entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int rs400_mc_wait_for_idle(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* read MC_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tmp = RREG32(RADEON_MC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (tmp & RADEON_MC_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void rs400_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* FIXME: is this correct ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) r420_pipes_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (rs400_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RREG32(RADEON_MC_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void rs400_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rs400_gart_adjust_size(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* DDR for all card after R300 & IGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) r100_vram_init_sizes(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) radeon_vram_location(rdev, &rdev->mc, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) radeon_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint32_t r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) WREG32(RS480_NB_MC_INDEX, reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) r = RREG32(RS480_NB_MC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) WREG32(RS480_NB_MC_INDEX, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WREG32(RS480_NB_MC_DATA, (v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) WREG32(RS480_NB_MC_INDEX, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct drm_info_node *node = (struct drm_info_node *) m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct drm_device *dev = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct radeon_device *rdev = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tmp = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tmp = RREG32(RADEON_BUS_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tmp = RREG32(RS690_HDP_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tmp = RREG32(RADEON_AGP_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tmp = RREG32(RS480_AGP_BASE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tmp = RREG32(RADEON_MC_AGP_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tmp = RREG32_MC(RS480_GART_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) seq_printf(m, "GART_BASE 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tmp = RREG32_MC(RS480_GART_FEATURE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp = RREG32_MC(RS480_MC_MISC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tmp = RREG32_MC(0x5F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tmp = RREG32_MC(0x3B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tmp = RREG32_MC(0x3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tmp = RREG32_MC(0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tmp = RREG32_MC(0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tmp = RREG32_MC(0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tmp = RREG32_MC(0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tmp = RREG32_MC(0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp = RREG32_MC(0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tmp = RREG32_MC(0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tmp = RREG32_MC(0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct drm_info_list rs400_gart_info_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void rs400_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct r100_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Stops all mc clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) r100_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Wait for mc idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (rs400_mc_wait_for_idle(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) WREG32(R_000148_MC_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) r100_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int rs400_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) r100_set_common_regs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rs400_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Resume clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) r300_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Initialize GPU configuration (# pipes, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) rs400_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) r100_enable_bm(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Initialize GART (initialize after TTM so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * memory through TTM but finalize after TTM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) r = rs400_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) r100_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* 1M ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) r = r100_cp_init(rdev, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int rs400_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Make sur GART are not working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rs400_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Resume clock before doing reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) r300_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* setup MC before calling post tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rs400_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) radeon_combios_asic_init(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Resume clock after posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) r300_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) r = rs400_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int rs400_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) r100_cp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) r100_irq_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rs400_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) void rs400_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rs400_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int rs400_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Disable VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) r100_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) radeon_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* TODO: disable VGA need to use VGA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* restore some register to sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) r100_restore_sanity(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* BIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) r = radeon_combios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_warn(rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (radeon_boot_test_post_card(rdev) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) rs400_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) r = rs400_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) r300_set_reg_safe(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) r = rs400_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Somethings want wront with the accel init stop accel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(rdev->dev, "Disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rs400_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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