^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2009 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2009 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef R600D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R600D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R6XX_MAX_SH_GPRS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R6XX_MAX_TEMP_GPRS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R6XX_MAX_SH_THREADS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R6XX_MAX_SH_STACK_ENTRIES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R6XX_MAX_BACKENDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R6XX_MAX_BACKENDS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R6XX_MAX_SIMDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R6XX_MAX_SIMDS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R6XX_MAX_PIPES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R6XX_MAX_PIPES_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* tiling bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARRAY_LINEAR_GENERAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ARRAY_LINEAR_ALIGNED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ARRAY_1D_TILED_THIN1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ARRAY_2D_TILED_THIN1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ARB_POP 0x2418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ENABLE_TC128 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ARB_GDEC_RD_CNTL 0x246C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CC_GC_SHADER_PIPE_CONFIG 0x8950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CC_RB_BACKEND_DISABLE 0x98F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R_028808_CB_COLOR_CONTROL 0x28808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define C_028808_SPECIAL_OP 0xFFFFFF8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define V_028808_SPECIAL_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define V_028808_SPECIAL_DISABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define V_028808_SPECIAL_RESOLVE_BOX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CB_COLOR0_BASE 0x28040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CB_COLOR1_BASE 0x28044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CB_COLOR2_BASE 0x28048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CB_COLOR3_BASE 0x2804C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CB_COLOR4_BASE 0x28050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CB_COLOR5_BASE 0x28054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CB_COLOR6_BASE 0x28058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CB_COLOR7_BASE 0x2805C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CB_COLOR7_FRAG 0x280FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CB_COLOR0_SIZE 0x28060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CB_COLOR0_VIEW 0x28080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R_028080_CB_COLOR0_VIEW 0x028080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define C_028080_SLICE_START 0xFFFFF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define C_028080_SLICE_MAX 0xFF001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R_028084_CB_COLOR1_VIEW 0x028084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R_028088_CB_COLOR2_VIEW 0x028088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R_02808C_CB_COLOR3_VIEW 0x02808C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R_028090_CB_COLOR4_VIEW 0x028090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R_028094_CB_COLOR5_VIEW 0x028094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R_028098_CB_COLOR6_VIEW 0x028098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R_02809C_CB_COLOR7_VIEW 0x02809C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R_028100_CB_COLOR0_MASK 0x028100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define C_028100_FMASK_TILE_MAX 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R_028104_CB_COLOR1_MASK 0x028104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R_028108_CB_COLOR2_MASK 0x028108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R_02810C_CB_COLOR3_MASK 0x02810C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R_028110_CB_COLOR4_MASK 0x028110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R_028114_CB_COLOR5_MASK 0x028114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R_028118_CB_COLOR6_MASK 0x028118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R_02811C_CB_COLOR7_MASK 0x02811C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CB_COLOR0_INFO 0x280a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define CB_FORMAT(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define CB_ARRAY_MODE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define CB_SOURCE_FORMAT(x) ((x) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define CB_SF_EXPORT_FULL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define CB_SF_EXPORT_NORM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CB_COLOR0_TILE 0x280c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CB_COLOR0_FRAG 0x280e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CB_COLOR0_MASK 0x28100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SQ_ALU_CONST_CACHE_PS_0 0x28940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SQ_ALU_CONST_CACHE_PS_1 0x28944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SQ_ALU_CONST_CACHE_PS_2 0x28948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SQ_ALU_CONST_CACHE_PS_4 0x28950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SQ_ALU_CONST_CACHE_PS_5 0x28954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SQ_ALU_CONST_CACHE_PS_6 0x28958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SQ_ALU_CONST_CACHE_PS_8 0x28960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SQ_ALU_CONST_CACHE_PS_9 0x28964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SQ_ALU_CONST_CACHE_PS_10 0x28968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SQ_ALU_CONST_CACHE_PS_12 0x28970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SQ_ALU_CONST_CACHE_PS_13 0x28974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SQ_ALU_CONST_CACHE_PS_14 0x28978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SQ_ALU_CONST_CACHE_VS_0 0x28980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SQ_ALU_CONST_CACHE_VS_1 0x28984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SQ_ALU_CONST_CACHE_VS_2 0x28988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SQ_ALU_CONST_CACHE_VS_4 0x28990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SQ_ALU_CONST_CACHE_VS_5 0x28994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SQ_ALU_CONST_CACHE_VS_6 0x28998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CONFIG_MEMSIZE 0x5428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CONFIG_CNTL 0x5424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CP_STALLED_STAT1 0x8674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CP_STALLED_STAT2 0x8678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CP_BUSY_STAT 0x867C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CP_STAT 0x8680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CP_COHER_BASE 0x85F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CP_DEBUG 0xC1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define R_0086D8_CP_ME_CNTL 0x86D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CP_ME_RAM_DATA 0xC160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CP_ME_RAM_RADDR 0xC158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CP_ME_RAM_WADDR 0xC15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CP_MEQ_THRESHOLDS 0x8764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MEQ_END(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ROQ_END(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CP_PERFMON_CNTL 0x87FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CP_PFP_UCODE_ADDR 0xC150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CP_PFP_UCODE_DATA 0xC154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CP_QUEUE_THRESHOLDS 0x8760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ROQ_IB1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ROQ_IB2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CP_RB_BASE 0xC100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CP_RB_CNTL 0xC104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RB_BUFSZ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RB_BLKSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RB_NO_UPDATE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RB_RPTR_WR_ENA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BUF_SWAP_32BIT (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CP_RB_RPTR 0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CP_RB_RPTR_ADDR 0xC10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RB_RPTR_SWAP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CP_RB_RPTR_ADDR_HI 0xC110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CP_RB_RPTR_WR 0xC108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CP_RB_WPTR 0xC114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CP_RB_WPTR_ADDR 0xC118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CP_RB_WPTR_ADDR_HI 0xC11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CP_RB_WPTR_DELAY 0x8704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CP_ROQ_IB1_STAT 0x8784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CP_ROQ_IB2_STAT 0x8788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CP_SEM_WAIT_TIMER 0x85BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DB_DEBUG 0x9830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DB_DEPTH_BASE 0x2800C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DB_HTILE_DATA_BASE 0x28014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DB_HTILE_SURFACE 0x28D24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define C_028D24_HTILE_WIDTH 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DB_WATERMARKS 0x9838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DEPTH_FREE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DEPTH_FLUSH(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DEPTH_PENDING_FREE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DEPTH_CACHELINE_FREE(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DCP_TILING_CONFIG 0x6CA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PIPE_TILING(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define BANK_TILING(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GROUP_SIZE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ROW_TILING(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BANK_SWAPS(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SAMPLE_SPLIT(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BACKEND_MAP(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GB_TILING_CONFIG 0x98F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PIPE_TILING__SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PIPE_TILING__MASK 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GC_USER_SHADER_PIPE_CONFIG 0x8954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define INACTIVE_QD_PIPES(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define INACTIVE_QD_PIPES_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define INACTIVE_SIMDS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define INACTIVE_SIMDS_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SQ_CONFIG 0x8c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) # define VC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) # define EXPORT_SRC_C (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) # define DX9_CONSTS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) # define ALU_INST_PREFER_VECTOR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define DX10_CLAMP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) # define CLAUSE_SEQ_PRIO(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) # define PS_PRIO(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) # define VS_PRIO(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) # define GS_PRIO(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) # define ES_PRIO(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SQ_GPR_RESOURCE_MGMT_1 0x8c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # define NUM_PS_GPRS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define NUM_VS_GPRS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SQ_GPR_RESOURCE_MGMT_2 0x8c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) # define NUM_GS_GPRS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) # define NUM_ES_GPRS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SQ_THREAD_RESOURCE_MGMT 0x8c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) # define NUM_PS_THREADS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) # define NUM_VS_THREADS(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) # define NUM_GS_THREADS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) # define NUM_ES_THREADS(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SQ_STACK_RESOURCE_MGMT_1 0x8c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) # define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) # define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SQ_STACK_RESOURCE_MGMT_2 0x8c14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) # define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SQ_ESGS_RING_BASE 0x8c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SQ_GSVS_RING_BASE 0x8c48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SQ_ESTMP_RING_BASE 0x8c50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SQ_GSTMP_RING_BASE 0x8c58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SQ_VSTMP_RING_BASE 0x8c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SQ_PSTMP_RING_BASE 0x8c68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SQ_FBUF_RING_BASE 0x8c70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SQ_REDUC_RING_BASE 0x8c78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GRBM_CNTL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) # define GRBM_READ_TIMEOUT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CMDFIFO_AVAIL_MASK 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GUI_ACTIVE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GRBM_STATUS2 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SOFT_RESET_CP (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CG_THERMAL_CTRL 0x7F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DIG_THERM_DPM(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DIG_THERM_DPM_MASK 0x000FF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIG_THERM_DPM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CG_THERMAL_STATUS 0x7F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ASIC_T(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ASIC_T_MASK 0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ASIC_T_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CG_THERMAL_INT 0x7F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DIG_THERM_INTH(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DIG_THERM_INTH_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DIG_THERM_INTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DIG_THERM_INTL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DIG_THERM_INTL_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DIG_THERM_INTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define THERM_INT_MASK_HIGH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define THERM_INT_MASK_LOW (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RV770_CG_THERMAL_INT 0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HDP_HOST_PATH_CNTL 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HDP_NONSURFACE_BASE 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HDP_NONSURFACE_INFO 0x2C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HDP_NONSURFACE_SIZE 0x2C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HDP_TILING_CONFIG 0x2F3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HDP_DEBUG1 0x2F34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MC_CONFIG 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MC_VM_AGP_TOP 0x2184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MC_VM_AGP_BOT 0x2188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MC_VM_AGP_BASE 0x218C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MC_VM_FB_LOCATION 0x2180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ENABLE_L1_TLB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ENABLE_L1_STRICT_ORDERING (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SYSTEM_ACCESS_MODE_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SYSTEM_ACCESS_MODE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ENABLE_SEMAPHORE_MODE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ENABLE_WAIT_L2_QUERY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define LOGICAL_PAGE_NUMBER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define RS_DQ_RD_RET_CONF 0x2348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PA_CL_ENHANCE 0x8A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLIP_VTX_REORDER_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define NUM_CLIP_SEQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PA_SC_AA_CONFIG 0x28C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define S0_X(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define S0_Y(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define S1_X(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define S1_Y(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define S2_X(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define S2_Y(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define S3_X(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define S3_Y(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define S4_X(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define S4_Y(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define S5_X(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define S5_Y(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define S6_X(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define S6_Y(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define S7_X(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define S7_Y(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PA_SC_CLIPRECT_RULE 0x2820c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PA_SC_ENHANCE 0x8BF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PA_SC_LINE_STIPPLE 0x28A0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PA_SC_LINE_STIPPLE_STATE 0x8B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PA_SC_MODE_CNTL 0x28A4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PA_SC_MULTI_CHIP_CNTL 0x8B20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PA_SC_SCREEN_SCISSOR_TL 0x28030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PA_SC_GENERIC_SCISSOR_TL 0x28240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PA_SC_WINDOW_SCISSOR_TL 0x28204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PCIE_PORT_INDEX 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PCIE_PORT_DATA 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CHMAP 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define NOOFCHAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define NOOFCHAN_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RAMCFG 0x2408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define NOOFBANK_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define NOOFRANK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define NOOFRANK_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define NOOFROWS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define NOOFROWS_MASK 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define NOOFCOLS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define NOOFCOLS_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CHANSIZE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CHANSIZE_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BURSTLENGTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BURSTLENGTH_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CHANSIZE_OVERRIDE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SCRATCH_REG0 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SCRATCH_REG1 0x8504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SCRATCH_REG2 0x8508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SCRATCH_REG3 0x850C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SCRATCH_REG4 0x8510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SCRATCH_REG5 0x8514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SCRATCH_REG6 0x8518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SCRATCH_REG7 0x851C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SCRATCH_UMSK 0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SCRATCH_ADDR 0x8544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SPI_CONFIG_CNTL 0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define GPR_WRITE_PRIORITY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DISABLE_INTERP_1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SPI_CONFIG_CNTL_1 0x913C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define VTX_DONE_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SPI_INPUT_Z 0x286D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SPI_PS_IN_CONTROL_0 0x286CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define NUM_INTERP(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define POSITION_ENA (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define POSITION_CENTROID (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define POSITION_ADDR(x) ((x)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PARAM_GEN(x) ((x)<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PARAM_GEN_ADDR(x) ((x)<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PERSP_GRADIENT_ENA (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define LINEAR_GRADIENT_ENA (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define POSITION_SAMPLE (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define BARYC_AT_SAMPLE_ENA (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SPI_PS_IN_CONTROL_1 0x286D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define GEN_INDEX_PIX (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define FRONT_FACE_ENA (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define FRONT_FACE_CHAN(x) ((x)<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FRONT_FACE_ALL_BITS (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define FRONT_FACE_ADDR(x) ((x)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define FOG_ADDR(x) ((x)<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FIXED_PT_POSITION_ENA (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SQ_MS_FIFO_SIZES 0x8CF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CACHE_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define FETCH_FIFO_HIWATER(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DONE_FIFO_HIWATER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SQ_PGM_START_ES 0x28880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SQ_PGM_START_FS 0x28894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SQ_PGM_START_GS 0x2886C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SQ_PGM_START_PS 0x28840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SQ_PGM_RESOURCES_PS 0x28850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SQ_PGM_EXPORTS_PS 0x28854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SQ_PGM_CF_OFFSET_PS 0x288cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SQ_PGM_START_VS 0x28858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SQ_PGM_RESOURCES_VS 0x28868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SQ_PGM_CF_OFFSET_VS 0x288d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SQ_VTX_CONSTANT_WORD0_0 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SQ_VTX_CONSTANT_WORD1_0 0x30004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SQ_VTX_CONSTANT_WORD2_0 0x30008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) # define SQ_VTXC_STRIDE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) # define SQ_ENDIAN_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) # define SQ_ENDIAN_8IN16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) # define SQ_ENDIAN_8IN32 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SQ_VTX_CONSTANT_WORD3_0 0x3000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SQ_VTX_CONSTANT_WORD6_0 0x38018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SQ_TEX_VTX_INVALID_BUFFER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SQ_TEX_VTX_VALID_TEXTURE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SQ_TEX_VTX_VALID_BUFFER 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SX_MISC 0x28350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SX_MEMORY_EXPORT_BASE 0x9010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SX_DEBUG_1 0x9054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SMX_EVENT_RELEASE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define TA_CNTL_AUX 0x9508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DISABLE_CUBE_WRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DISABLE_CUBE_ANISO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SYNC_GRADIENT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SYNC_WALKER (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SYNC_ALIGNER (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define BILINEAR_PRECISION_6_BIT (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define BILINEAR_PRECISION_8_BIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define TC_CNTL 0x9608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define TC_L2_SIZE(x) ((x)<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define L2_DISABLE_LATE_HIT (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define VC_ENHANCE 0x9714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define VGT_CACHE_INVALIDATION 0x88C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CACHE_INVALIDATION(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define VC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define TC_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define VC_AND_TC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define VGT_DMA_BASE 0x287E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define VGT_DMA_BASE_HI 0x287E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define VGT_ES_PER_GS 0x88CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define VGT_GS_PER_ES 0x88C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define VGT_GS_PER_VS 0x88E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define VGT_GS_VERTEX_REUSE 0x88D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define VGT_PRIMITIVE_TYPE 0x8958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define VGT_NUM_INSTANCES 0x8974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define VGT_OUT_DEALLOC_CNTL 0x28C5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DEALLOC_DIST_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define VGT_STRMOUT_EN 0x28AB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define VTX_REUSE_DEPTH_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define VGT_EVENT_INITIATOR 0x28a90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define VM_CONTEXT0_CNTL 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ENABLE_CONTEXT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define RESPONSE_TYPE_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define RESPONSE_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define VM_L2_CNTL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ENABLE_L2_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define VM_L2_CNTL2 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define INVALIDATE_ALL_L1_TLBS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define INVALIDATE_L2_CACHE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define VM_L2_CNTL3 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define VM_L2_STATUS 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define L2_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define WAIT_UNTIL 0x8040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define WAIT_CP_DMA_IDLE_bit (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define WAIT_2D_IDLE_bit (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define WAIT_3D_IDLE_bit (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define WAIT_2D_IDLECLEAN_bit (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define WAIT_3D_IDLECLEAN_bit (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* async DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DMA_TILING_CONFIG 0x3ec4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DMA_CONFIG 0x3e4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DMA_RB_CNTL 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) # define DMA_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define DMA_RB_BASE 0xd004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DMA_RB_RPTR 0xd008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DMA_RB_WPTR 0xd00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define DMA_RB_RPTR_ADDR_HI 0xd01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DMA_RB_RPTR_ADDR_LO 0xd020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DMA_IB_CNTL 0xd024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) # define DMA_IB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) # define DMA_IB_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DMA_IB_RPTR 0xd028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DMA_CNTL 0xd02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) # define TRAP_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) # define SEM_WAIT_INT_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) # define DATA_SWAP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) # define FENCE_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) # define CTXEMPTY_INT_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DMA_STATUS_REG 0xd034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) # define DMA_IDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DMA_MODE 0xd0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* async DMA packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (((t) & 0x1) << 23) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) (((s) & 0x1) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (((n) & 0xFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* async DMA Packet types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DMA_PACKET_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DMA_PACKET_COPY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DMA_PACKET_INDIRECT_BUFFER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DMA_PACKET_SEMAPHORE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DMA_PACKET_FENCE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DMA_PACKET_TRAP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DMA_PACKET_NOP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define IH_RB_CNTL 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) # define IH_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define IH_RB_BASE 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define IH_RB_RPTR 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define IH_RB_WPTR 0x3e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) # define RB_OVERFLOW (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) # define WPTR_OFFSET_MASK 0x3fffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define IH_RB_WPTR_ADDR_HI 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define IH_RB_WPTR_ADDR_LO 0x3e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define IH_CNTL 0x3e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) # define ENABLE_INTR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) # define IH_MC_SWAP(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) # define IH_MC_SWAP_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) # define IH_MC_SWAP_16BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) # define IH_MC_SWAP_32BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) # define IH_MC_SWAP_64BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) # define RPTR_REARM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) # define MC_WRREQ_CREDIT(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) # define MC_WR_CLEAN_CNT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define RLC_CNTL 0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) # define RLC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define RLC_HB_BASE 0x3f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define RLC_HB_CNTL 0x3f0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define RLC_HB_RPTR 0x3f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define RLC_HB_WPTR 0x3f1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define RLC_HB_WPTR_LSB_ADDR 0x3f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define RLC_HB_WPTR_MSB_ADDR 0x3f18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define RLC_MC_CNTL 0x3f44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define RLC_UCODE_CNTL 0x3f48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define RLC_UCODE_ADDR 0x3f2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define RLC_UCODE_DATA 0x3f30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SRBM_SOFT_RESET 0xe60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) # define SOFT_RESET_BIF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) # define SOFT_RESET_DMA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) # define SOFT_RESET_RLC (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) # define SOFT_RESET_UVD (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) # define RV770_SOFT_RESET_DMA (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define BIF_SCRATCH0 0x5438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define BUS_CNTL 0x5420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) # define BIOS_ROM_DIS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) # define VGA_COHE_SPEC_TIMER_DIS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CP_INT_CNTL 0xc124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) # define CNTX_BUSY_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) # define CNTX_EMPTY_INT_ENABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) # define SCRATCH_INT_ENABLE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) # define TIME_STAMP_INT_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) # define IB2_INT_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) # define IB1_INT_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) # define RB_INT_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define CP_INT_STATUS 0xc128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) # define SCRATCH_INT_STAT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) # define TIME_STAMP_INT_STAT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) # define IB2_INT_STAT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) # define IB1_INT_STAT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) # define RB_INT_STAT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define GRBM_INT_CNTL 0x8060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) # define RDERR_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) # define GUI_IDLE_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define INTERRUPT_CNTL 0x5468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) # define IH_DUMMY_RD_OVERRIDE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) # define IH_DUMMY_RD_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) # define IH_REQ_NONSNOOP_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) # define GEN_IH_INT_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define INTERRUPT_CNTL2 0x546c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define D1MODE_VBLANK_STATUS 0x6534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define D2MODE_VBLANK_STATUS 0x6d34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) # define DxMODE_VBLANK_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) # define DxMODE_VBLANK_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) # define DxMODE_VBLANK_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) # define DxMODE_VBLANK_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define D1MODE_VLINE_STATUS 0x653c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define D2MODE_VLINE_STATUS 0x6d3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) # define DxMODE_VLINE_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) # define DxMODE_VLINE_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) # define DxMODE_VLINE_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) # define DxMODE_VLINE_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define DxMODE_INT_MASK 0x6540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) # define D1MODE_VBLANK_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) # define D1MODE_VLINE_INT_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) # define D2MODE_VBLANK_INT_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) # define D2MODE_VLINE_INT_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) # define DC_HPD1_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) # define DC_HPD2_INTERRUPT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define DISP_INTERRUPT_STATUS 0x7edc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) # define LB_D1_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) # define LB_D2_VLINE_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) # define LB_D1_VBLANK_INTERRUPT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) # define LB_D2_VBLANK_INTERRUPT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) # define DACA_AUTODETECT_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) # define DACB_AUTODETECT_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) # define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) # define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) # define DC_HPD4_INTERRUPT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) # define DC_HPD4_RX_INTERRUPT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) # define DC_HPD3_INTERRUPT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) # define DC_HPD1_RX_INTERRUPT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) # define DC_HPD2_RX_INTERRUPT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) # define DC_HPD3_RX_INTERRUPT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) # define AUX1_SW_DONE_INTERRUPT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) # define AUX1_LS_DONE_INTERRUPT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) # define AUX2_SW_DONE_INTERRUPT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) # define AUX2_LS_DONE_INTERRUPT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) # define AUX3_SW_DONE_INTERRUPT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) # define AUX3_LS_DONE_INTERRUPT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) # define AUX4_SW_DONE_INTERRUPT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) # define AUX4_LS_DONE_INTERRUPT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) # define AUX5_SW_DONE_INTERRUPT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) # define AUX5_LS_DONE_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) # define AUX6_SW_DONE_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) # define AUX6_LS_DONE_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) # define DC_HPD5_INTERRUPT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) # define DC_HPD5_RX_INTERRUPT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) # define DC_HPD6_INTERRUPT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) # define DC_HPD6_RX_INTERRUPT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define DACA_AUTO_DETECT_CONTROL 0x7828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define DACB_AUTO_DETECT_CONTROL 0x7a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) # define DACx_AUTODETECT_MODE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) # define DACx_AUTODETECT_MODE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) # define DACx_AUTODETECT_MODE_CONNECT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) # define DACx_AUTODETECT_MODE_DISCONNECT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DACA_AUTODETECT_INT_CONTROL 0x7838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DACB_AUTODETECT_INT_CONTROL 0x7a38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) # define DACx_AUTODETECT_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) # define DACx_AUTODETECT_INT_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) # define DC_HOT_PLUG_DETECTx_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* DCE 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define DC_HPD1_INT_STATUS 0x7d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define DC_HPD2_INT_STATUS 0x7d0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define DC_HPD3_INT_STATUS 0x7d18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define DC_HPD4_INT_STATUS 0x7d24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define DC_HPD5_INT_STATUS 0x7dc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define DC_HPD6_INT_STATUS 0x7df4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) # define DC_HPDx_INT_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) # define DC_HPDx_SENSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) # define DC_HPDx_RX_INT_STATUS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* DCE 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define DC_HPD1_INT_CONTROL 0x7d04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define DC_HPD2_INT_CONTROL 0x7d10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define DC_HPD3_INT_CONTROL 0x7d1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define DC_HPD4_INT_CONTROL 0x7d28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define DC_HPD5_INT_CONTROL 0x7dc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define DC_HPD6_INT_CONTROL 0x7df8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) # define DC_HPDx_INT_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) # define DC_HPDx_INT_POLARITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) # define DC_HPDx_INT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) # define DC_HPDx_RX_INT_ACK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) # define DC_HPDx_RX_INT_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* DCE 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DC_HPD1_CONTROL 0x7d08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DC_HPD2_CONTROL 0x7d14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define DC_HPD3_CONTROL 0x7d20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DC_HPD4_CONTROL 0x7d2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DC_HPD5_CONTROL 0x7dc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DC_HPD6_CONTROL 0x7dfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) # define DC_HPDx_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define D1GRPH_INTERRUPT_STATUS 0x6158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define D2GRPH_INTERRUPT_STATUS 0x6958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) # define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define D1GRPH_INTERRUPT_CONTROL 0x615c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define D2GRPH_INTERRUPT_CONTROL 0x695c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) # define DxGRPH_PFLIP_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) # define DxGRPH_PFLIP_INT_TYPE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* PCIE link stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) # define LC_POINT_7_PLUS_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) # define LC_LINK_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) # define LC_LINK_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) # define LC_LINK_WIDTH_X0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) # define LC_LINK_WIDTH_X1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) # define LC_LINK_WIDTH_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) # define LC_LINK_WIDTH_X4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) # define LC_LINK_WIDTH_X8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) # define LC_LINK_WIDTH_X16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) # define LC_LINK_WIDTH_RD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) # define LC_LINK_WIDTH_RD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) # define LC_RECONFIG_NOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) # define LC_RENEGOTIATION_SUPPORT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) # define LC_RENEGOTIATE_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) # define LC_SHORT_RECONFIG_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) # define LC_UPCONFIGURE_SUPPORT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) # define LC_UPCONFIGURE_DIS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) # define LC_CURRENT_DATA_RATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define MM_CFGREGS_CNTL 0x544c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) # define MM_WR_TO_CFG_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define LINK_CNTL2 0x88 /* F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) # define TARGET_LINK_SPEED_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) # define SELECTABLE_DEEMPHASIS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define AZ_HOT_PLUG_CONTROL 0x7300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) # define AZ_FORCE_CODEC_WAKE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) # define JACK_DETECTION_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) # define UNSOLICITED_RESPONSE_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) # define CODEC_HOT_PLUG_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) # define AUDIO_ENABLED (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* DCE3 adds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) # define PIN0_AUDIO_ENABLED (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) # define PIN1_AUDIO_ENABLED (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) # define PIN2_AUDIO_ENABLED (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) # define PIN3_AUDIO_ENABLED (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Audio clocks DCE 2.0/3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define AUDIO_DTO 0x7340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Audio clocks DCE 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define DCCG_AUDIO_DTO0_PHASE 0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define DCCG_AUDIO_DTO0_MODULE 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define DCCG_AUDIO_DTO0_LOAD 0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) # define DTO_LOAD (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define DCCG_AUDIO_DTO0_CNTL 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define DCCG_AUDIO_DTO1_PHASE 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define DCCG_AUDIO_DTO1_MODULE 0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define DCCG_AUDIO_DTO1_LOAD 0x052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define DCCG_AUDIO_DTO1_CNTL 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define DCCG_AUDIO_DTO_SELECT 0x0534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* digital blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define TMDSA_CNTL 0x7880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) # define TMDSA_HDMI_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define LVTMA_CNTL 0x7a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) # define LVTMA_HDMI_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define DDIA_CNTL 0x7200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) # define DDIA_HDMI_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define DIG0_CNTL 0x75a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) # define DIG_MODE(x) (((x) & 7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) # define DIG_MODE_DP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) # define DIG_MODE_LVDS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) # define DIG_MODE_TMDS_DVI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) # define DIG_MODE_TMDS_HDMI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) # define DIG_MODE_SDVO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define DIG1_CNTL 0x79a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define SPEAKER_ALLOCATION_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define SPEAKER_ALLOCATION_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define HDMI_CONNECTION (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define DP_CONNECTION (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* max channels minus one. 7 = 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * bit0 = 32 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * bit1 = 44.1 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * bit2 = 48 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * bit3 = 88.2 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * bit4 = 96 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * bit5 = 176.4 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * bit6 = 192 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * different due to the new DIG blocks, but also have 2 instances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * DCE 3.0 HDMI blocks are part of each DIG encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* rs6xx/rs740/r6xx/dce3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define HDMI0_CONTROL 0x7400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* rs6xx/rs740/r6xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) # define HDMI0_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) # define HDMI0_STREAM(x) (((x) & 3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) # define HDMI0_STREAM_TMDSA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) # define HDMI0_STREAM_LVTMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) # define HDMI0_STREAM_DVOA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) # define HDMI0_STREAM_DDIA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* rs6xx/r6xx/dce3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) # define HDMI0_ERROR_ACK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) # define HDMI0_ERROR_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define HDMI0_STATUS 0x7404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) # define HDMI0_ACTIVE_AVMUTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) # define HDMI0_AUDIO_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) # define HDMI0_AZ_FORMAT_WTRIG (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define HDMI0_AUDIO_PACKET_CONTROL 0x7408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) # define HDMI0_AUDIO_DELAY_EN_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) # define HDMI0_AUDIO_TEST_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) # define HDMI0_AUDIO_PACKETS_PER_LINE_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) # define HDMI0_60958_CS_UPDATE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define HDMI0_AUDIO_CRC_CONTROL 0x740c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) # define HDMI0_AUDIO_CRC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define DCE3_HDMI0_ACR_PACKET_CONTROL 0x740c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define HDMI0_VBI_PACKET_CONTROL 0x7410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) # define HDMI0_NULL_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) # define HDMI0_GC_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define HDMI0_INFOFRAME_CONTROL0 0x7414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) # define HDMI0_AVI_INFO_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) # define HDMI0_AVI_INFO_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) # define HDMI0_AUDIO_INFO_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) # define HDMI0_AUDIO_INFO_CONT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) # define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) # define HDMI0_MPEG_INFO_SEND (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) # define HDMI0_MPEG_INFO_CONT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) # define HDMI0_MPEG_INFO_UPDATE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define HDMI0_INFOFRAME_CONTROL1 0x7418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) # define HDMI0_AVI_INFO_LINE_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) # define HDMI0_AUDIO_INFO_LINE_MASK (0x3f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define HDMI0_GENERIC_PACKET_CONTROL 0x741c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) # define HDMI0_GENERIC0_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) # define HDMI0_GENERIC0_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) # define HDMI0_GENERIC0_UPDATE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) # define HDMI0_GENERIC1_SEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) # define HDMI0_GENERIC1_CONT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) # define HDMI0_GENERIC0_LINE_MASK (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) # define HDMI0_GENERIC1_LINE_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define HDMI0_GC 0x7428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) # define HDMI0_GC_AVMUTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define HDMI0_AVI_INFO0 0x7454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) # define HDMI0_AVI_INFO_Y_RGB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) # define HDMI0_AVI_INFO_Y_YCBCR422 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) # define HDMI0_AVI_INFO_Y_YCBCR444 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define HDMI0_AVI_INFO1 0x7458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define HDMI0_AVI_INFO2 0x745c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define HDMI0_AVI_INFO3 0x7460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define HDMI0_MPEG_INFO0 0x7464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define HDMI0_MPEG_INFO1 0x7468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define HDMI0_GENERIC0_HDR 0x746c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define HDMI0_GENERIC0_0 0x7470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define HDMI0_GENERIC0_1 0x7474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define HDMI0_GENERIC0_2 0x7478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define HDMI0_GENERIC0_3 0x747c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define HDMI0_GENERIC0_4 0x7480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define HDMI0_GENERIC0_5 0x7484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define HDMI0_GENERIC0_6 0x7488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define HDMI0_GENERIC1_HDR 0x748c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define HDMI0_GENERIC1_0 0x7490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define HDMI0_GENERIC1_1 0x7494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define HDMI0_GENERIC1_2 0x7498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define HDMI0_GENERIC1_3 0x749c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define HDMI0_GENERIC1_4 0x74a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define HDMI0_GENERIC1_5 0x74a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define HDMI0_GENERIC1_6 0x74a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define HDMI0_ACR_32_0 0x74ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) # define HDMI0_ACR_CTS_32_MASK (0xfffff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define HDMI0_ACR_32_1 0x74b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) # define HDMI0_ACR_N_32_MASK (0xfffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define HDMI0_ACR_44_0 0x74b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) # define HDMI0_ACR_CTS_44_MASK (0xfffff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define HDMI0_ACR_44_1 0x74b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) # define HDMI0_ACR_N_44_MASK (0xfffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define HDMI0_ACR_48_0 0x74bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) # define HDMI0_ACR_CTS_48_MASK (0xfffff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define HDMI0_ACR_48_1 0x74c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) # define HDMI0_ACR_N_48_MASK (0xfffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define HDMI0_ACR_STATUS_0 0x74c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define HDMI0_ACR_STATUS_1 0x74c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define HDMI0_AUDIO_INFO0 0x74cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define HDMI0_AUDIO_INFO1 0x74d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define HDMI0_60958_0 0x74d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) # define HDMI0_60958_CS_A(x) (((x) & 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) # define HDMI0_60958_CS_B(x) (((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) # define HDMI0_60958_CS_C(x) (((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) # define HDMI0_60958_CS_D(x) (((x) & 3) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) # define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) # define HDMI0_60958_CS_CLOCK_ACCURACY_MASK (3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define HDMI0_60958_1 0x74d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) # define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define HDMI0_ACR_PACKET_CONTROL 0x74dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) # define HDMI0_ACR_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) # define HDMI0_ACR_CONT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) # define HDMI0_ACR_HW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) # define HDMI0_ACR_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) # define HDMI0_ACR_44 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) # define HDMI0_ACR_48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) # define HDMI0_ACR_AUTO_SEND (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define DCE3_HDMI0_AUDIO_CRC_CONTROL 0x74dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define HDMI0_RAMP_CONTROL0 0x74e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define HDMI0_RAMP_CONTROL1 0x74e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define HDMI0_RAMP_CONTROL2 0x74e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define HDMI0_RAMP_CONTROL3 0x74ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* HDMI0_60958_2 is r7xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define HDMI0_60958_2 0x74f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* r6xx only; second instance starts at 0x7700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define HDMI1_CONTROL 0x7700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define HDMI1_STATUS 0x7704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define HDMI1_AUDIO_PACKET_CONTROL 0x7708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* DCE3; second instance starts at 0x7800 NOT 0x7700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define DCE3_HDMI1_CONTROL 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define DCE3_HDMI1_STATUS 0x7804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* DCE3.2 (for interrupts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define AFMT_STATUS 0x7600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) # define AFMT_AUDIO_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define AFMT_AUDIO_PACKET_CONTROL 0x7604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) # define AFMT_AUDIO_TEST_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) # define AFMT_60958_CS_UPDATE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* DCE3 FMT blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define FMT_CONTROL 0x6700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) # define FMT_PIXEL_ENCODING (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define FMT_BIT_DEPTH_CONTROL 0x6710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) # define FMT_TRUNCATE_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) # define FMT_TRUNCATE_DEPTH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) # define FMT_SPATIAL_DITHER_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) # define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) # define FMT_RGB_RANDOM_ENABLE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) # define FMT_TEMPORAL_DITHER_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) # define FMT_TEMPORAL_LEVEL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) # define FMT_25FRC_SEL(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) # define FMT_50FRC_SEL(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) # define FMT_75FRC_SEL(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define FMT_CLAMP_CONTROL 0x672c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) # define FMT_CLAMP_DATA_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) # define FMT_CLAMP_6BPC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) # define FMT_CLAMP_8BPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) # define FMT_CLAMP_10BPC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) # define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) # define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) # define SPLL_REF_DIV(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) # define SPLL_REF_DIV_MASK (7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) # define SPLL_FB_DIV(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) # define SPLL_FB_DIV_MASK (0xff << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) # define SPLL_PULSEEN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) # define SPLL_PULSENUM(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) # define SPLL_PULSENUM_MASK (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) # define SPLL_SW_HILEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) # define SPLL_SW_HILEN_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) # define SPLL_SW_LOLEN(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) # define SPLL_SW_LOLEN_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) # define SPLL_DIVEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) # define SPLL_BYPASS_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) # define SPLL_CHG_STATUS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) # define SPLL_CTLREQ (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) # define SPLL_CTLACK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define GENERAL_PWRMGT 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) # define MOBILE_SU (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) # define THERMAL_PROTECTION_DIS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) # define THERMAL_PROTECTION_TYPE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) # define ENABLE_GEN2PCIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) # define SW_GPIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) # define SW_GPIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define CG_TPC 0x61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) # define TPCC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) # define TPCC_MASK (0x7fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) # define TPU(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) # define TPU_MASK (0x1f << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define SCLK_PWRMGT_CNTL 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) # define SCLK_TURNOFF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) # define SPLL_TURNOFF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) # define SU_SCLK_USE_BCLK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) # define CLK_TURN_ON_STAGGER (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) # define CLK_TURN_OFF_STAGGER (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) # define FIR_FORCE_TREND_SEL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) # define FIR_TREND_MODE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) # define DYN_GFX_CLK_OFF_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) # define VDDC3D_TURNOFF_D1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) # define VDDC3D_TURNOFF_D2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) # define VDDC3D_TURNOFF_D3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) # define SPLL_TURNOFF_D2 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) # define SCLK_LOW_D1 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) # define DYN_GFX_CLK_OFF_MC_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define MCLK_PWRMGT_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) # define MPLL_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) # define YCLK_TURNOFF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) # define MPLL_TURNOFF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) # define SU_MCLK_USE_BCLK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) # define DLL_READY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) # define MC_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) # define MRDCKA_SLEEP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) # define MRDCKB_SLEEP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) # define MRDCKC_SLEEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) # define MRDCKD_SLEEP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) # define MRDCKE_SLEEP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) # define MRDCKF_SLEEP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) # define MRDCKG_SLEEP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) # define MRDCKH_SLEEP (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) # define MRDCKA_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) # define MRDCKB_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) # define MRDCKC_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) # define MRDCKD_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) # define MRDCKE_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) # define MRDCKF_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) # define MRDCKG_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) # define MRDCKH_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) # define USE_DISPLAY_GAP_CTXSW (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) # define USE_DISPLAY_URGENT_CTXSW (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define MPLL_TIME 0x634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) # define MPLL_LOCK_TIME(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) # define MPLL_LOCK_TIME_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) # define MPLL_RESET_TIME(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) # define MPLL_RESET_TIME_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) # define STEP_0_SPLL_POST_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) # define STEP_0_SPLL_FB_DIV(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) # define STEP_0_SPLL_REF_DIV(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) # define STEP_0_SPLL_REF_DIV_MASK (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) # define STEP_0_POST_DIV_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) # define STEP_0_SPLL_STEP_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) # define STEP_0_SPLL_ENTRY_VALID (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define VID_RT 0x6f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) # define VID_CRT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) # define VID_CRT_MASK (0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) # define VID_CRTU(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) # define VID_CRTU_MASK (7 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) # define SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) # define SSTU_MASK (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define CTXSW_PROFILE_INDEX 0x6fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) # define CTXSW_FREQ_STATE_ENABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) # define TARGET_PROFILE_INDEX_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) # define TARGET_PROFILE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) # define CURRENT_PROFILE_INDEX_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) # define CURRENT_PROFILE_INDEX_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) # define DYN_PWR_ENTER_INDEX(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) # define DYN_PWR_ENTER_INDEX_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) # define DYN_PWR_ENTER_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) # define CURR_MCLK_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) # define CURR_MCLK_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) # define CURR_SCLK_INDEX_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) # define CURR_SCLK_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) # define CURR_VID_INDEX_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) # define CURR_VID_INDEX_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define LOWER_GPIO_ENABLE 0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define UPPER_GPIO_ENABLE 0x714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define CTXSW_VID_LOWER_GPIO_CNTL 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define VID_UPPER_GPIO_CNTL 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define CG_CTX_CGTT3D_R 0x744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) # define PHC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) # define PHC_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) # define SDC(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) # define SDC_MASK (0x3fff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define CG_VDDC3D_OOR 0x748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) # define SU(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) # define SU_MASK (0xf << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define CG_FTV 0x74c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define CG_FFCT_0 0x750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) # define UTC_0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) # define UTC_0_MASK (0x3ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) # define DTC_0(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) # define DTC_0_MASK (0x3ff << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define CG_BSP 0x78c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) # define BSP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) # define BSP_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) # define BSU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) # define BSU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define CG_RT 0x790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) # define FLS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) # define FLS_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) # define FMS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) # define FMS_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define CG_LT 0x794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) # define FHS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) # define FHS_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define CG_GIT 0x798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) # define CG_GICST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) # define CG_GICST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) # define CG_GIPOT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) # define CG_GIPOT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define CG_SSP 0x7a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) # define CG_SST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) # define CG_SST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) # define CG_SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) # define CG_SSTU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define CG_RLC_REQ_AND_RSP 0x7c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) # define RLC_CG_REQ_TYPE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) # define RLC_CG_REQ_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) # define CG_RLC_RSP_TYPE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) # define CG_RLC_RSP_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define CG_FC_T 0x7cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) # define FC_T(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) # define FC_T_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) # define FC_TU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) # define FC_TU_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define GPIOPAD_MASK 0x1798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define GPIOPAD_A 0x179c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define GPIOPAD_EN 0x17a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define GRBM_PWR_CNTL 0x800c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) # define REQ_TYPE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) # define REQ_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) # define RSP_TYPE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) # define RSP_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * UVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define UVD_SEMA_ADDR_LOW 0xef00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define UVD_SEMA_ADDR_HIGH 0xef04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define UVD_SEMA_CMD 0xef08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define UVD_GPCOM_VCPU_CMD 0xef0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define UVD_GPCOM_VCPU_DATA0 0xef10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define UVD_GPCOM_VCPU_DATA1 0xef14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define UVD_ENGINE_CNTL 0xef18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define UVD_NO_OP 0xeffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define UVD_SEMA_CNTL 0xf400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define UVD_RB_ARB_CTRL 0xf480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define UVD_LMI_EXT40_ADDR 0xf498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define UVD_CGC_GATE 0xf4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define UVD_LMI_CTRL2 0xf4f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define UVD_MASTINT_EN 0xf500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define UVD_FW_START 0xf51C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define UVD_LMI_ADDR_EXT 0xf594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define UVD_LMI_CTRL 0xf598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define UVD_LMI_SWAP_CNTL 0xf5b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define UVD_MP_SWAP_CNTL 0xf5bC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define UVD_MPC_CNTL 0xf5dC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define UVD_MPC_SET_MUXA0 0xf5e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define UVD_MPC_SET_MUXA1 0xf5e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define UVD_MPC_SET_MUXB0 0xf5eC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define UVD_MPC_SET_MUXB1 0xf5f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define UVD_MPC_SET_MUX 0xf5f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define UVD_MPC_SET_ALU 0xf5f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define UVD_VCPU_CACHE_OFFSET0 0xf608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define UVD_VCPU_CACHE_SIZE0 0xf60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define UVD_VCPU_CACHE_OFFSET1 0xf610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define UVD_VCPU_CACHE_SIZE1 0xf614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define UVD_VCPU_CACHE_OFFSET2 0xf618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define UVD_VCPU_CACHE_SIZE2 0xf61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define UVD_VCPU_CNTL 0xf660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define UVD_SOFT_RESET 0xf680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define RBC_SOFT_RESET (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define LBSI_SOFT_RESET (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define LMI_SOFT_RESET (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define VCPU_SOFT_RESET (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define CSM_SOFT_RESET (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define CXW_SOFT_RESET (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define TAP_SOFT_RESET (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define LMI_UMC_SOFT_RESET (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define UVD_RBC_IB_BASE 0xf684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define UVD_RBC_IB_SIZE 0xf688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define UVD_RBC_RB_BASE 0xf68c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define UVD_RBC_RB_RPTR 0xf690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define UVD_RBC_RB_WPTR 0xf694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define UVD_RBC_RB_WPTR_CNTL 0xf698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define UVD_STATUS 0xf6bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define UVD_RBC_RB_CNTL 0xf6a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define UVD_RBC_RB_RPTR_ADDR 0xf6a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define UVD_CONTEXT_ID 0xf6f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* rs780 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define GFX_MACRO_BYPASS_CNTL 0x30c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define SPLL_BYPASS_CNTL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define UPLL_BYPASS_CNTL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define CG_UPLL_FUNC_CNTL 0x7e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) # define UPLL_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) # define UPLL_SLEEP_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) # define UPLL_BYPASS_EN_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) # define UPLL_CTLREQ_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) # define UPLL_FB_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) # define UPLL_FB_DIV_MASK 0x0000FFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) # define UPLL_REF_DIV(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) # define UPLL_REF_DIV_MASK 0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) # define UPLL_REFCLK_SRC_SEL_MASK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) # define UPLL_CTLACK_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) # define UPLL_CTLACK2_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define CG_UPLL_FUNC_CNTL_2 0x7e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) # define UPLL_SW_HILEN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) # define UPLL_SW_LOLEN(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) # define UPLL_SW_HILEN2(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) # define UPLL_SW_LOLEN2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) # define UPLL_DIVEN_MASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) # define UPLL_DIVEN2_MASK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) # define UPLL_SW_MASK 0x0003FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) # define VCLK_SRC_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) # define VCLK_SRC_SEL_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) # define DCLK_SRC_SEL(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) # define DCLK_SRC_SEL_MASK 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * PM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) (((reg) >> 2) & 0xFFFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) (((op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* Packet 3 types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define PACKET3_INDIRECT_BUFFER_END 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define PACKET3_SET_PREDICATION 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define PACKET3_REG_RMW 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define PACKET3_COND_EXEC 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define PACKET3_PRED_EXEC 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define PACKET3_START_3D_CMDBUF 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define PACKET3_DRAW_INDEX_2 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define PACKET3_CONTEXT_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define PACKET3_DRAW_INDEX_IMMD_BE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define PACKET3_INDEX_TYPE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define PACKET3_DRAW_INDEX 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define PACKET3_DRAW_INDEX_AUTO 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define PACKET3_DRAW_INDEX_IMMD 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define PACKET3_NUM_INSTANCES 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define PACKET3_INDIRECT_BUFFER_MP 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define PACKET3_MEM_SEMAPHORE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define PACKET3_MPEG_INDEX 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define PACKET3_COPY_DW 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define PACKET3_WAIT_REG_MEM 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define PACKET3_MEM_WRITE 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define PACKET3_INDIRECT_BUFFER 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define PACKET3_CP_DMA 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* 1. header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * 2. SRC_ADDR_LO [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * 4. DST_ADDR_LO [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * 5. DST_ADDR_HI [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /* COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define PACKET3_SURFACE_SYNC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) # define PACKET3_TC_ACTION_ENA (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) # define PACKET3_VC_ACTION_ENA (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) # define PACKET3_CB_ACTION_ENA (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) # define PACKET3_DB_ACTION_ENA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) # define PACKET3_SH_ACTION_ENA (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) # define PACKET3_SMX_ACTION_ENA (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define PACKET3_ME_INITIALIZE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define PACKET3_COND_WRITE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define PACKET3_EVENT_WRITE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define EVENT_TYPE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define EVENT_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* 0 - any non-TS event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * 1 - ZPASS_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * 2 - SAMPLE_PIPELINESTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * 3 - SAMPLE_STREAMOUTSTAT*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * 4 - *S_PARTIAL_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * 5 - TS events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define PACKET3_EVENT_WRITE_EOP 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define DATA_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* 0 - discard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * 1 - send low 32bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * 2 - send 64bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * 3 - send 64bit counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define INT_SEL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * 1 - interrupt only (DATA_SEL = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * 2 - interrupt when data write is confirmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define PACKET3_ONE_REG_WRITE 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define PACKET3_SET_CONFIG_REG 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define PACKET3_SET_CONTEXT_REG 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define PACKET3_SET_CONTEXT_REG_END 0x00029000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define PACKET3_SET_ALU_CONST 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define PACKET3_SET_ALU_CONST_END 0x00032000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define PACKET3_SET_BOOL_CONST 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define PACKET3_SET_BOOL_CONST_END 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define PACKET3_SET_LOOP_CONST 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define PACKET3_SET_LOOP_CONST_END 0x0003e380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define PACKET3_SET_RESOURCE 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define PACKET3_SET_RESOURCE_OFFSET 0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define PACKET3_SET_RESOURCE_END 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define PACKET3_SET_SAMPLER 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define PACKET3_SET_SAMPLER_END 0x0003cff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define PACKET3_SET_CTL_CONST 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define PACKET3_SET_CTL_CONST_END 0x0003e200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define PACKET3_SURFACE_BASE_UPDATE 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define R_000011_K8_FB_LOCATION 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define R_000012_MC_MISC_UMA_CNTL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define R_0028F8_MC_INDEX 0x28F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define C_0028F8_MC_IND_ADDR 0xFFFFFE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define R_0028FC_MC_DATA 0x28FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define R_008020_GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define R_008010_GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define S_008010_VC_BUSY(x) (((x) & 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define S_008010_TC_BUSY(x) (((x) & 1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define S_008010_SX_BUSY(x) (((x) & 1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define S_008010_SH_BUSY(x) (((x) & 1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define S_008010_SC_BUSY(x) (((x) & 1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define S_008010_PA_BUSY(x) (((x) & 1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define S_008010_CR_BUSY(x) (((x) & 1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define S_008010_CP_BUSY(x) (((x) & 1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define G_008010_TA_BUSY(x) (((x) >> 14) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define R_008014_GRBM_STATUS2 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define R_000E50_SRBM_STATUS 0x0E50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define R_000E60_SRBM_SOFT_RESET 0x0E60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define R_028C04_PA_SC_AA_CONFIG 0x028C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define R_0280E0_CB_COLOR0_FRAG 0x0280E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define C_0280E0_BASE_256B 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define R_0280E4_CB_COLOR1_FRAG 0x0280E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define R_0280E8_CB_COLOR2_FRAG 0x0280E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define R_0280EC_CB_COLOR3_FRAG 0x0280EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define R_0280F0_CB_COLOR4_FRAG 0x0280F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define R_0280F4_CB_COLOR5_FRAG 0x0280F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define R_0280F8_CB_COLOR6_FRAG 0x0280F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define R_0280FC_CB_COLOR7_FRAG 0x0280FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define R_0280C0_CB_COLOR0_TILE 0x0280C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define C_0280C0_BASE_256B 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define R_0280C4_CB_COLOR1_TILE 0x0280C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define R_0280C8_CB_COLOR2_TILE 0x0280C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define R_0280CC_CB_COLOR3_TILE 0x0280CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define R_0280D0_CB_COLOR4_TILE 0x0280D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define R_0280D4_CB_COLOR5_TILE 0x0280D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define R_0280D8_CB_COLOR6_TILE 0x0280D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define R_0280DC_CB_COLOR7_TILE 0x0280DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define R_0280A0_CB_COLOR0_INFO 0x0280A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define C_0280A0_ENDIAN 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define C_0280A0_FORMAT 0xFFFFFF03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define V_0280A0_COLOR_INVALID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define V_0280A0_COLOR_8 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define V_0280A0_COLOR_4_4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define V_0280A0_COLOR_3_3_2 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define V_0280A0_COLOR_16 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define V_0280A0_COLOR_16_FLOAT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define V_0280A0_COLOR_8_8 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define V_0280A0_COLOR_5_6_5 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define V_0280A0_COLOR_6_5_5 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define V_0280A0_COLOR_1_5_5_5 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define V_0280A0_COLOR_4_4_4_4 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define V_0280A0_COLOR_5_5_5_1 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define V_0280A0_COLOR_32 0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define V_0280A0_COLOR_32_FLOAT 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define V_0280A0_COLOR_16_16 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define V_0280A0_COLOR_16_16_FLOAT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define V_0280A0_COLOR_8_24 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define V_0280A0_COLOR_8_24_FLOAT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define V_0280A0_COLOR_24_8 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define V_0280A0_COLOR_24_8_FLOAT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define V_0280A0_COLOR_10_11_11 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define V_0280A0_COLOR_11_11_10 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define V_0280A0_COLOR_2_10_10_10 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define V_0280A0_COLOR_8_8_8_8 0x0000001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define V_0280A0_COLOR_10_10_10_2 0x0000001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define V_0280A0_COLOR_32_32 0x0000001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define V_0280A0_COLOR_16_16_16_16 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define V_0280A0_COLOR_32_32_32_32 0x00000022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define C_0280A0_ARRAY_MODE 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define C_0280A0_READ_SIZE 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define C_0280A0_COMP_SWAP 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define C_0280A0_TILE_MODE 0xFFF3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define V_0280A0_TILE_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define V_0280A0_CLEAR_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define V_0280A0_FRAG_ENABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define C_0280A0_ROUND_MODE 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define C_0280A0_TILE_COMPACT 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define R_0280A4_CB_COLOR1_INFO 0x0280A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define R_0280A8_CB_COLOR2_INFO 0x0280A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define R_0280AC_CB_COLOR3_INFO 0x0280AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define R_0280B0_CB_COLOR4_INFO 0x0280B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define R_0280B4_CB_COLOR5_INFO 0x0280B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define R_0280B8_CB_COLOR6_INFO 0x0280B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define R_0280BC_CB_COLOR7_INFO 0x0280BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define R_028060_CB_COLOR0_SIZE 0x028060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define C_028060_PITCH_TILE_MAX 0xFFFFFC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define C_028060_SLICE_TILE_MAX 0xC00003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define R_028064_CB_COLOR1_SIZE 0x028064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define R_028068_CB_COLOR2_SIZE 0x028068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define R_02806C_CB_COLOR3_SIZE 0x02806C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define R_028070_CB_COLOR4_SIZE 0x028070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define R_028074_CB_COLOR5_SIZE 0x028074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define R_028078_CB_COLOR6_SIZE 0x028078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define R_02807C_CB_COLOR7_SIZE 0x02807C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define R_028238_CB_TARGET_MASK 0x028238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define R_02823C_CB_SHADER_MASK 0x02823C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #define R_028AB0_VGT_STRMOUT_EN 0x028AB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define C_028AB0_STREAMOUT 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define C_028B20_BUFFER_0_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define C_028B20_BUFFER_1_EN 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define C_028B20_BUFFER_2_EN 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define C_028B20_BUFFER_3_EN 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define C_028B20_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define S_038000_DIM(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define G_038000_DIM(x) (((x) >> 0) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define C_038000_DIM 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define V_038000_SQ_TEX_DIM_1D 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define V_038000_SQ_TEX_DIM_2D 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define V_038000_SQ_TEX_DIM_3D 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define C_038000_TILE_MODE 0xFFFFFF87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define C_038000_TILE_TYPE 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define C_038000_PITCH 0xFFF800FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define C_038000_TEX_WIDTH 0x0007FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define C_038004_TEX_HEIGHT 0xFFFFE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define C_038004_TEX_DEPTH 0xFC001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define C_038004_DATA_FORMAT 0x03FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define V_038004_COLOR_INVALID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define V_038004_COLOR_8 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) #define V_038004_COLOR_4_4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define V_038004_COLOR_3_3_2 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define V_038004_COLOR_16 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define V_038004_COLOR_16_FLOAT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define V_038004_COLOR_8_8 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define V_038004_COLOR_5_6_5 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define V_038004_COLOR_6_5_5 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define V_038004_COLOR_1_5_5_5 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define V_038004_COLOR_4_4_4_4 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define V_038004_COLOR_5_5_5_1 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define V_038004_COLOR_32 0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define V_038004_COLOR_32_FLOAT 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define V_038004_COLOR_16_16 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #define V_038004_COLOR_16_16_FLOAT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define V_038004_COLOR_8_24 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define V_038004_COLOR_8_24_FLOAT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define V_038004_COLOR_24_8 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define V_038004_COLOR_24_8_FLOAT 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define V_038004_COLOR_10_11_11 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define V_038004_COLOR_10_11_11_FLOAT 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define V_038004_COLOR_11_11_10 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define V_038004_COLOR_11_11_10_FLOAT 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define V_038004_COLOR_2_10_10_10 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define V_038004_COLOR_8_8_8_8 0x0000001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define V_038004_COLOR_10_10_10_2 0x0000001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define V_038004_COLOR_32_32 0x0000001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #define V_038004_COLOR_32_32_FLOAT 0x0000001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define V_038004_COLOR_16_16_16_16 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define V_038004_COLOR_32_32_32_32 0x00000022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define V_038004_FMT_1 0x00000025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define V_038004_FMT_GB_GR 0x00000027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define V_038004_FMT_BG_RG 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define V_038004_FMT_32_AS_8 0x00000029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define V_038004_FMT_32_AS_8_8 0x0000002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define V_038004_FMT_8_8_8 0x0000002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define V_038004_FMT_16_16_16 0x0000002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define V_038004_FMT_16_16_16_FLOAT 0x0000002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define V_038004_FMT_32_32_32 0x0000002F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define V_038004_FMT_32_32_32_FLOAT 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define V_038004_FMT_BC1 0x00000031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define V_038004_FMT_BC2 0x00000032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #define V_038004_FMT_BC3 0x00000033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define V_038004_FMT_BC4 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define V_038004_FMT_BC5 0x00000035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define V_038004_FMT_BC6 0x00000036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define V_038004_FMT_BC7 0x00000037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define V_038004_FMT_32_AS_32_32_32_32 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define C_038010_FORMAT_COMP_X 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define C_038010_FORMAT_COMP_W 0xFFFFFF3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define C_038010_SRF_MODE_ALL 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define C_038010_ENDIAN_SWAP 0xFFFFCFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define C_038010_REQUEST_SIZE 0xFFFF3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define C_038010_DST_SEL_X 0xFFF8FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define C_038010_DST_SEL_Y 0xFFC7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) #define C_038010_DST_SEL_Z 0xFE3FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define C_038010_DST_SEL_W 0xF1FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) # define SQ_SEL_X 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) # define SQ_SEL_Y 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) # define SQ_SEL_Z 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) # define SQ_SEL_W 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) # define SQ_SEL_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) # define SQ_SEL_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #define C_038010_BASE_LEVEL 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define C_038014_LAST_LEVEL 0xFFFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #define C_038014_BASE_ARRAY 0xFFFE000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #define C_038014_LAST_ARRAY 0xC001FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #define C_0288A8_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) #define C_008C44_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define C_0288B0_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define C_008C54_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define C_0288C0_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define C_008C74_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define C_0288B4_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) #define C_008C5C_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define C_0288AC_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) #define C_008C4C_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #define C_0288BC_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #define C_008C6C_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) #define C_0288C4_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #define C_008C7C_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define C_0288B8_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define C_008C64_MEM_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define C_0288C8_ITEMSIZE 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define R_028010_DB_DEPTH_INFO 0x028010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) #define S_028010_FORMAT(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define C_028010_FORMAT 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define V_028010_DEPTH_INVALID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define V_028010_DEPTH_16 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define V_028010_DEPTH_X8_24 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define V_028010_DEPTH_8_24 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define V_028010_DEPTH_X8_24_FLOAT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define V_028010_DEPTH_8_24_FLOAT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define V_028010_DEPTH_32_FLOAT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define C_028010_READ_SIZE 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define C_028010_ARRAY_MODE 0xFFF87FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) #define C_028010_TILE_COMPACT 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #define R_028000_DB_DEPTH_SIZE 0x028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) #define C_028000_PITCH_TILE_MAX 0xFFFFFC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #define C_028000_SLICE_TILE_MAX 0xC00003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #define R_028004_DB_DEPTH_VIEW 0x028004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) #define C_028004_SLICE_START 0xFFFFF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define C_028004_SLICE_MAX 0xFF001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #define R_028800_DB_DEPTH_CONTROL 0x028800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) #define C_028800_Z_ENABLE 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) #define C_028800_ZFUNC 0xFFFFFF8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #define C_028800_STENCILFUNC 0xFFFFF8FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) #define C_028800_STENCILFAIL 0xFFFFC7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define C_028800_STENCILZPASS 0xFFFE3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define C_028800_STENCILZFAIL 0xFFF1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define C_028800_STENCILFAIL_BF 0xFC7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) #define C_028800_STENCILZPASS_BF 0xE3FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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