^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "r520d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int r520_mc_wait_for_idle(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* read MC_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) tmp = RREG32_MC(R520_MC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (tmp & R520_MC_STATUS_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void r520_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned pipe_select_current, gb_pipe_select, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) rv515_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * DST_PIPE_CONFIG 0x170C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * GB_TILE_CONFIG 0x4018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * GB_FIFO_SIZE 0x4024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * GB_PIPE_SELECT 0x402C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * GB_PIPE_SELECT2 0x4124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Z_PIPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Z_PIPE_MASK 0x000000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * GB_FIFO_SIZE2 0x4128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * SC_SFIFO_SIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * SC_SFIFO_SIZE_MASK 0x000000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * SC_MFIFO_SIZE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SC_MFIFO_SIZE_MASK 0x00000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * FG_SFIFO_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * FG_SFIFO_SIZE_MASK 0x000000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ZB_MFIFO_SIZE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * ZB_MFIFO_SIZE_MASK 0x0000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * GA_ENHANCE 0x4274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * SU_REG_DEST 0x42C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* workaround for RV530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (rdev->family == CHIP_RV530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WREG32(0x4128, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) r420_pipes_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tmp = RREG32(R300_DST_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pipe_select_current = (tmp >> 2) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tmp = (1 << pipe_select_current) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (((gb_pipe_select >> 8) & 0xF) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WREG32_PLL(0x000D, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (r520_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void r520_vram_get_type(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tmp = RREG32_MC(R520_MC_CNTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rdev->mc.vram_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rdev->mc.vram_width = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rdev->mc.vram_width = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rdev->mc.vram_width = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (tmp & R520_MC_CHANNEL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rdev->mc.vram_width *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void r520_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) r520_vram_get_type(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) r100_vram_init_sizes(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) radeon_vram_location(rdev, &rdev->mc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rdev->mc.gtt_base_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!(rdev->flags & RADEON_IS_AGP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) radeon_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void r520_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct rv515_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Stops all mc clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rv515_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Wait for mc idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (r520_mc_wait_for_idle(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Write VRAM size in case we are limiting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Program MC, should be a 32bits limited address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) WREG32_MC(R_000004_MC_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) WREG32(R_000134_HDP_FB_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) WREG32_MC(R_000005_MC_AGP_LOCATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) WREG32_MC(R_000007_AGP_BASE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) WREG32_MC(R_000006_AGP_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) WREG32_MC(R_000007_AGP_BASE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rv515_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int r520_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) r520_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Resume clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Initialize GPU configuration (# pipes, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) r520_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Initialize GART (initialize after TTM so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * memory through TTM but finalize after TTM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (rdev->flags & RADEON_IS_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) r = rv370_pcie_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rs600_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* 1M ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) r = r100_cp_init(rdev, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int r520_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Make sur GART are not working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rv370_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Resume clock before doing reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Resume clock after posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rv515_clock_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) r = r520_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int r520_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) radeon_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* restore some register to sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) r100_restore_sanity(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* TODO: disable VGA need to use VGA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* BIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_warn(rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (radeon_boot_test_post_card(rdev) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!radeon_card_posted(rdev) && rdev->bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DRM_INFO("GPU not posted. posting now...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* initialize AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) r = radeon_agp_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) radeon_agp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) r520_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rv515_debugfs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) r = rv370_pcie_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rv515_set_safe_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) r = r520_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Somethings want wront with the accel init stop accel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(rdev->dev, "Disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rv370_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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