^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "r100d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "r420_reg_safe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "r420d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "radeon_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void r420_pm_init_profile(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* low sh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* mid sh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* high sh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* low mh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* mid mh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* high mh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void r420_set_reg_safe(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void r420_pipes_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned gb_pipe_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned num_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* GA_ENHANCE workaround TCL deadlock issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (1 << 2) | (1 << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* add idle wait as per freedesktop.org bug 24041 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (r100_gui_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* get max number of pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* SE chips have 1 pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if ((rdev->pdev->device == 0x5e4c) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (rdev->pdev->device == 0x5e4f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) num_pipes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rdev->num_gb_pipes = num_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) switch (num_pipes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* force to 1 pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) num_pipes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp = (0 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tmp = (3 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tmp = (6 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmp = (7 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Sub pixel 1/12 so we can have 4K rendering according to doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WREG32(R300_GB_TILE_CONFIG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (r100_gui_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) tmp = RREG32(R300_DST_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WREG32(R300_RB2D_DSTCACHE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RREG32(R300_RB2D_DSTCACHE_MODE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) R300_DC_AUTOFLUSH_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) R300_DC_DC_DISABLE_IGNORE_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (r100_gui_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (rdev->family == CHIP_RV530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tmp = RREG32(RV530_GB_PIPE_SELECT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if ((tmp & 3) == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rdev->num_z_pipes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rdev->num_z_pipes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rdev->num_z_pipes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rdev->num_gb_pipes, rdev->num_z_pipes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) r = RREG32(R_0001FC_MC_IND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_irqsave(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) S_0001F8_MC_IND_WR_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) WREG32(R_0001FC_MC_IND_DATA, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void r420_debugfs(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (r100_debugfs_rbbm_init(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_ERROR("Failed to register debugfs file for RBBM !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (r420_debugfs_pipes_info_init(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DRM_ERROR("Failed to register debugfs file for pipes !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void r420_clock_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 sclk_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (radeon_dynclks != -1 && radeon_dynclks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) radeon_atom_set_clock_gating(rdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rdev->family == CHIP_R420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void r420_cp_errata_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* RV410 and R420 can lock up if CP DMA to host memory happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * while the 2D engine is busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * The proper workaround is to queue a RESYNC at the beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * of the CP init, apparently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) r = radeon_ring_lock(rdev, ring, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) WARN_ON(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) radeon_ring_write(ring, rdev->config.r300.resync_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) radeon_ring_write(ring, 0xDEADBEEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void r420_cp_errata_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Catch the RESYNC we dispatched all the way back,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * at the very beginning of the CP init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) r = radeon_ring_lock(rdev, ring, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) WARN_ON(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) radeon_ring_write(ring, R300_RB3D_DC_FINISH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int r420_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* set common regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) r100_set_common_regs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* program mc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) r300_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Resume clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) r420_clock_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Initialize GART (initialize after TTM so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * memory through TTM but finalize after TTM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (rdev->flags & RADEON_IS_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) r = rv370_pcie_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (rdev->flags & RADEON_IS_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) r = r100_pci_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) r420_pipes_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) r100_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* 1M ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) r = r100_cp_init(rdev, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) r420_cp_errata_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int r420_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Make sur GART are not working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rv370_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (rdev->flags & RADEON_IS_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) r100_pci_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Resume clock before doing reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) r420_clock_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) radeon_combios_asic_init(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Resume clock after posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) r420_clock_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) r = r420_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int r420_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) r420_cp_errata_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) r100_cp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) r100_irq_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rv370_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (rdev->flags & RADEON_IS_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) r100_pci_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void r420_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rv370_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (rdev->flags & RADEON_IS_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) r100_pci_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) radeon_combios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int r420_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) radeon_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* TODO: disable VGA need to use VGA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* restore some register to sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) r100_restore_sanity(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* BIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) r = radeon_combios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Reset gpu before posting otherwise ATOM will enter infinite loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (radeon_asic_reset(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_warn(rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RREG32(R_000E40_RBBM_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RREG32(R_0007C0_CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* check if cards are posted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (radeon_boot_test_post_card(rdev) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* initialize AGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (rdev->flags & RADEON_IS_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) r = radeon_agp_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) radeon_agp_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) r300_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) r420_debugfs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (rdev->family == CHIP_R420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) r100_enable_bm(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (rdev->flags & RADEON_IS_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) r = rv370_pcie_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (rdev->flags & RADEON_IS_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) r = r100_pci_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) r420_set_reg_safe(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) r = r420_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Somethings want wront with the accel init stop accel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(rdev->dev, "Disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) r100_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (rdev->flags & RADEON_IS_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rv370_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (rdev->flags & RADEON_IS_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) r100_pci_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) radeon_agp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Debugfs info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct drm_info_node *node = (struct drm_info_node *) m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct drm_device *dev = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct radeon_device *rdev = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tmp = RREG32(R400_GB_PIPE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tmp = RREG32(R300_GB_TILE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tmp = RREG32(R300_DST_PIPE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct drm_info_list r420_pipes_info_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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