^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Red Hat Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2009 Jerome Glisse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Authors: Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Jerome Glisse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef __R100D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __R100D_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CP_PACKET0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PACKET0_BASE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PACKET0_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PACKET0_COUNT_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CP_PACKET1 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CP_PACKET3 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PACKET3_IT_OPCODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PACKET3_IT_OPCODE_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PACKET3_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PACKET3_COUNT_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* PACKET3 op code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PACKET3_3D_DRAW_VBUF 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PACKET3_3D_DRAW_IMMD 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PACKET3_3D_DRAW_INDX 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PACKET3_3D_LOAD_VBPNTR 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PACKET3_3D_CLEAR_ZMASK 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PACKET3_INDX_BUFFER 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PACKET3_3D_DRAW_VBUF_2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PACKET3_3D_DRAW_IMMD_2 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PACKET3_3D_DRAW_INDX_2 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PACKET3_3D_CLEAR_HIZ 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PACKET3_BITBLT_MULTI 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PACKET0(reg, n) (CP_PACKET0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REG_SET(PACKET0_COUNT, (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PACKET3(op, n) (CP_PACKET3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) REG_SET(PACKET3_IT_OPCODE, (op)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) REG_SET(PACKET3_COUNT, (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R_0000F0_RBBM_SOFT_RESET 0x0000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R_000030_BUS_CNTL 0x000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define C_000030_BUS_RETRY_WS 0xFFF0FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define C_000030_BUS_SUSPEND 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define S_000030_LAT_16X(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define C_000030_LAT_16X 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define C_000030_ENFRCWRDY 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define C_000030_BUS_MSTR_WS 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define S_000030_SERR_EN(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define C_000030_SERR_EN 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define C_000030_BUS_READ_BURST 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define R_000040_GEN_INT_CNTL 0x000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define C_000040_CRTC_VBLANK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define C_000040_CRTC_VLINE 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define C_000040_CRTC_VSYNC 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define C_000040_SNAPSHOT 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define C_000040_FP_DETECT 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define C_000040_CRTC2_VLINE 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define C_000040_CRTC2_VSYNC 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define C_000040_SNAPSHOT2 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define C_000040_CRTC2_VBLANK 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define C_000040_FP2_DETECT 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define C_000040_I2C_INT_EN 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define C_000040_GUI_IDLE 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define C_000040_VIPH_INT_EN 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define C_000040_SW_INT_EN 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define C_000040_GEYSERVILLE 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define C_000040_DVI_I2C_INT 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define C_000040_GUIDMA 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define C_000040_VIDDMA 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define R_000044_GEN_INT_STATUS 0x000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define C_000044_FP_DETECT_STAT 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define C_000044_I2C_INT 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define C_000044_I2C_INT_AK 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define C_000044_VIPH_INT 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define S_000044_SW_INT(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define C_000044_SW_INT 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define C_000044_SW_INT_AK 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define C_000044_SW_INT_SET 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define C_000044_GUIDMA_STAT 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define C_000044_GUIDMA_AK 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define C_000044_VIDDMA_STAT 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define C_000044_VIDDMA_AK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define R_000050_CRTC_GEN_CNTL 0x000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define C_000050_CRTC_ICON_EN 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define C_000050_CRTC_CUR_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define C_000050_CRTC_EN 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define R_000054_CRTC_EXT_CNTL 0x000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define C_000054_VGA_TEXT_132 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define S_000054_CRT_ON(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define C_000054_CRT_ON 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define C_000054_VGA_PACK_DIS 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define R_000148_MC_FB_LOCATION 0x000148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define C_000148_MC_FB_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define C_000148_MC_FB_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define R_00014C_MC_AGP_LOCATION 0x00014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define C_00014C_MC_AGP_START 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define C_00014C_MC_AGP_TOP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define R_000170_AGP_BASE 0x000170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define C_000170_AGP_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define R_00023C_DISPLAY_BASE_ADDR 0x00023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define C_00023C_DISPLAY_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define R_000260_CUR_OFFSET 0x000260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define C_000260_CUR_OFFSET 0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define C_000260_CUR_LOCK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define R_000360_CUR2_OFFSET 0x000360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define C_000360_CUR2_OFFSET 0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define C_000360_CUR2_LOCK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define R_0003C2_GENMO_WT 0x0003C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define C_0003C2_VGA_RAM_EN 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define C_0003C2_VGA_CKSEL 0xF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define C_0003C2_VGA_HSYNC_POL 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define C_0003C2_VGA_VSYNC_POL 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define C_0003F8_CRT2_ON 0xFFFFFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define C_0003F8_CRTC2_EN 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define R_000420_OV0_SCALE_CNTL 0x000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define C_000420_OV0_INT_EMU 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define R_00070C_CP_RB_RPTR_ADDR 0x00070C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define C_00070C_RB_RPTR_ADDR 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define R_000740_CP_CSQ_CNTL 0x000740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define C_000740_CSQ_MODE 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define R_000770_SCRATCH_UMSK 0x000770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define C_000770_SCRATCH_UMSK 0xFFFFFFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define C_000770_SCRATCH_SWAP 0xFFFCFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define R_000774_SCRATCH_ADDR 0x000774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define C_000774_SCRATCH_ADDR 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define R_0007C0_CP_STAT 0x0007C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define C_0007C0_MRU_BUSY 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define C_0007C0_MWU_BUSY 0xFFFFFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define C_0007C0_CSI_BUSY 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define C_0007C0_CP_BUSY 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define R_000E40_RBBM_STATUS 0x000E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define C_000E40_E2_BUSY 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define C_000E40_RB2D_BUSY 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define C_000E40_RB3D_BUSY 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define C_000E40_SE_BUSY 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define C_000E40_RE_BUSY 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define C_000E40_TAM_BUSY 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define C_000E40_TDM_BUSY 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define C_000E40_PB_BUSY 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define R_00000D_SCLK_CNTL 0x00000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define C_00000D_FORCE_CP 0xFFFEFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define C_00000D_FORCE_HDP 0xFFFDFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define C_00000D_FORCE_DISP 0xFFFBFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define C_00000D_FORCE_TOP 0xFFF7FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define C_00000D_FORCE_E2 0xFFEFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define C_00000D_FORCE_SE 0xFFDFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define C_00000D_FORCE_IDCT 0xFFBFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define C_00000D_FORCE_VIP 0xFF7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define C_00000D_FORCE_RE 0xFEFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define C_00000D_FORCE_PB 0xFDFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define C_00000D_FORCE_TAM 0xFBFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define C_00000D_FORCE_TDM 0xF7FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define C_00000D_FORCE_RB 0xEFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* PLL regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define SCLK_CNTL 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define FORCE_HDP (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define CLK_PWRMGT_CNTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define GLOBAL_PMAN_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define DISP_PM (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define PLL_PWRMGT_CNTL 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MPLL_TURNOFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define SPLL_TURNOFF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define PPLL_TURNOFF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define P2PLL_TURNOFF (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define TVPLL_TURNOFF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define MOBILE_SU (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SU_SCLK_USE_BCLK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SCLK_CNTL2 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define REDUCED_SPEED_SCLK_MODE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define MCLK_MISC 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define SCLK_MORE_CNTL 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define REDUCED_SPEED_SCLK_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define IO_CG_VOLTAGE_DROP (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define VOLTAGE_DELAY_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define VOLTAGE_DROP_SYNC (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* mmreg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define DISP_PWR_MAN 0xd08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define DISP_D3_GRPH_RST (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define DISP_D3_SUBPIC_RST (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define DISP_D3_OV0_RST (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define DISP_D1D2_GRPH_RST (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define DISP_D1D2_SUBPIC_RST (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define DISP_D1D2_OV0_RST (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define DISP_DVO_ENABLE_RST (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define TV_ENABLE_RST (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define AUTO_PWRUP_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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