^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2013 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef _PPTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _PPTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) typedef struct _ATOM_PPLIB_THERMALCONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) UCHAR ucI2cLine; // as interpreted by DAL I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) UCHAR ucI2cAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) UCHAR ucFanParameters; // Fan Control Parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) UCHAR ucReserved; // ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) UCHAR ucFlags; // to be defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } ATOM_PPLIB_THERMALCONTROLLER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ATOM_PP_THERMALCONTROLLER_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ATOM_PP_THERMALCONTROLLER_LM64 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ATOM_PP_THERMALCONTROLLER_RV6xx 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ATOM_PP_THERMALCONTROLLER_RV770 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ATOM_PP_THERMALCONTROLLER_ADT7473 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ATOM_PP_THERMALCONTROLLER_KONG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATOM_PP_THERMALCONTROLLER_LM96163 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATOM_PP_THERMALCONTROLLER_KAVERI 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) // We probably should reserve the bit 0x80 for this use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) // The driver can pick the correct internal controller based on the ASIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) typedef struct _ATOM_PPLIB_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) UCHAR ucNonClockStateIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) UCHAR ucClockStateIndices[1]; // variable-sized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } ATOM_PPLIB_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) typedef struct _ATOM_PPLIB_FANTABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) UCHAR ucTHyst; // Temperature hysteresis. Integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) USHORT usTMed; // The middle temperature where we change slopes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) USHORT usTHigh; // The high point above TMed for adjusting the second slope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) USHORT usPWMMed; // The PWM value (in percent) at TMed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) USHORT usPWMHigh; // The PWM value at THigh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } ATOM_PPLIB_FANTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) typedef struct _ATOM_PPLIB_FANTABLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ATOM_PPLIB_FANTABLE basicTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) USHORT usTMax; // The max temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } ATOM_PPLIB_FANTABLE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) typedef struct _ATOM_PPLIB_FANTABLE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ATOM_PPLIB_FANTABLE2 basicTable2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) UCHAR ucFanControlMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) USHORT usFanPWMMax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) USHORT usFanOutputSensitivity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } ATOM_PPLIB_FANTABLE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typedef struct _ATOM_PPLIB_EXTENDEDHEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ULONG ulMaxEngineClock; // For Overdrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ULONG ulMaxMemoryClock; // For Overdrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) // Add extra system parameters here, always adjust size to include all fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } ATOM_PPLIB_EXTENDEDHEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) typedef struct _ATOM_PPLIB_POWERPLAYTABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) UCHAR ucDataRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) UCHAR ucNumStates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) UCHAR ucStateEntrySize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) UCHAR ucClockInfoSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UCHAR ucNonClockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) USHORT usStateArrayOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) // offset from start of this table to array of ASIC-specific structures,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) // currently ATOM_PPLIB_CLOCK_INFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) USHORT usClockInfoArrayOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) USHORT usNonClockInfoArrayOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) USHORT usBackbiasTime; // in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) USHORT usVoltageTime; // in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) USHORT usTableSize; //the size of this structure, or the extended structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ATOM_PPLIB_THERMALCONTROLLER sThermalController;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) USHORT usBootClockInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) USHORT usBootNonClockInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } ATOM_PPLIB_POWERPLAYTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ATOM_PPLIB_POWERPLAYTABLE basicTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) UCHAR ucNumCustomThermalPolicy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) USHORT usCustomThermalPolicyArrayOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) USHORT usFormatID; // To be used ONLY by PPGen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) USHORT usFanTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) USHORT usExtendendedHeaderOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ULONG ulGoldenPPID; // PPGen use only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ULONG ulGoldenRevision; // PPGen use only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) USHORT usVddcDependencyOnSCLKOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) USHORT usVddciDependencyOnMCLKOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) USHORT usVddcDependencyOnMCLKOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) USHORT usMaxClockVoltageOnDCOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) USHORT usMvddDependencyOnMCLKOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ULONG ulTDPLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ULONG ulNearTDPLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ULONG ulSQRampingThreshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) USHORT usTDPODLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) USHORT usLoadLineSlope; // in milliOhms * 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) //// ATOM_PPLIB_NONCLOCK_INFO::usClassification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) // 2, 4, 6, 7 are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) // 0 is 2.5Gb/s, 1 is 5Gb/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) // lookup into reduced refresh-rate table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) // 2-15 TBD as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) //memory related flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) //M3 Arb //2bits, current 3 sets of parameters in total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ATOM_PPLIB_M3ARB_MASK 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ATOM_PPLIB_M3ARB_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ATOM_PPLIB_ENABLE_DRR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) // remaining 16 bits are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) typedef struct _ATOM_PPLIB_THERMAL_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) UCHAR ucMinTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) UCHAR ucMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) UCHAR ucThermalAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) // Contained in an array starting at the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ATOM_PPLIB_NONCLOCKINFO_VER1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ATOM_PPLIB_NONCLOCKINFO_VER2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) typedef struct _ATOM_PPLIB_NONCLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) USHORT usClassification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) UCHAR ucMinTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) UCHAR ucMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ULONG ulCapsAndSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) UCHAR ucRequiredPower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) USHORT usClassification2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ULONG ulVCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ULONG ulDCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) UCHAR ucUnused[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } ATOM_PPLIB_NONCLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) // Contained in an array starting at the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) // referenced from ATOM_PPLIB_STATE::ucClockStateIndices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) USHORT usEngineClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) UCHAR ucEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) USHORT usMemoryClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) UCHAR ucMemoryClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) USHORT usVDDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) USHORT usUnused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) USHORT usUnused2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } ATOM_PPLIB_R600_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) UCHAR ucLowEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) USHORT usHighEngineClockLow; // High Engine clock in MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) UCHAR ucHighEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) UCHAR ucMemoryClockHigh; // Currentyl unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) UCHAR ucPadding; // For proper alignment and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) USHORT usVDDC; // For the 780, use: None, Low, High, Variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ULONG ulFlags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } ATOM_PPLIB_RS780_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ATOM_PPLIB_RS780_SPMCLK_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) USHORT usEngineClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) UCHAR ucEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) USHORT usMemoryClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) UCHAR ucMemoryClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) USHORT usVDDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) USHORT usVDDCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) USHORT usUnused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) USHORT usEngineClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) UCHAR ucEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) USHORT usMemoryClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) UCHAR ucMemoryClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) USHORT usVDDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) USHORT usVDDCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) UCHAR ucPCIEGen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) UCHAR ucUnused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } ATOM_PPLIB_SI_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) USHORT usEngineClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) UCHAR ucEngineClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) USHORT usMemoryClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) UCHAR ucMemoryClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) UCHAR ucPCIEGen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) USHORT usPCIELane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } ATOM_PPLIB_CI_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) UCHAR ucEngineClockHigh; //clockfrequency >> 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) UCHAR vddcIndex; //2-bit vddc index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) USHORT tdpLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) //please initalize to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) USHORT rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) //please initialize to 0s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ULONG rsv2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }ATOM_PPLIB_SUMO_CLOCK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) typedef struct _ATOM_PPLIB_STATE_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) //number of valid dpm levels in this state; Driver uses it to calculate the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) UCHAR ucNumDPMLevels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) //a index to the array of nonClockInfos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) UCHAR nonClockInfoIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Driver will read the first ucNumDPMLevels in this array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) UCHAR clockInfoIndex[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } ATOM_PPLIB_STATE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) typedef struct _StateArray{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) //how many states we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) UCHAR ucNumEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ATOM_PPLIB_STATE_V2 states[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }StateArray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) typedef struct _ClockInfoArray{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) //how many clock levels we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) UCHAR ucNumEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) //sizeof(ATOM_PPLIB_CLOCK_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) UCHAR ucEntrySize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) UCHAR clockInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }ClockInfoArray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) typedef struct _NonClockInfoArray{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) //how many non-clock levels we have. normally should be same as number of states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) UCHAR ucNumEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) UCHAR ucEntrySize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }NonClockInfoArray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) USHORT usClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) UCHAR ucClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }ATOM_PPLIB_Clock_Voltage_Dependency_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) UCHAR ucNumEntries; // Number of entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }ATOM_PPLIB_Clock_Voltage_Dependency_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) USHORT usSclkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) UCHAR ucSclkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) USHORT usMclkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) UCHAR ucMclkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) USHORT usVddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) USHORT usVddci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }ATOM_PPLIB_Clock_Voltage_Limit_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) UCHAR ucNumEntries; // Number of entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }ATOM_PPLIB_Clock_Voltage_Limit_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) union _ATOM_PPLIB_CAC_Leakage_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) USHORT usVddc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) USHORT usVddc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) USHORT usVddc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) typedef struct _ATOM_PPLIB_CAC_Leakage_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) UCHAR ucNumEntries; // Number of entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }ATOM_PPLIB_CAC_Leakage_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) USHORT usSclkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) UCHAR ucSclkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) USHORT usMclkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) UCHAR ucMclkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }ATOM_PPLIB_PhaseSheddingLimits_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) UCHAR ucNumEntries; // Number of entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }ATOM_PPLIB_PhaseSheddingLimits_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) typedef struct _VCEClockInfo{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) USHORT usEVClkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) UCHAR ucEVClkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) USHORT usECClkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) UCHAR ucECClkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }VCEClockInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) typedef struct _VCEClockInfoArray{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) UCHAR ucNumEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) VCEClockInfo entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }VCEClockInfoArray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) UCHAR ucVCEClockInfoIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) UCHAR numEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) typedef struct _ATOM_PPLIB_VCE_State_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) UCHAR ucVCEClockInfoIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }ATOM_PPLIB_VCE_State_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) typedef struct _ATOM_PPLIB_VCE_State_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) UCHAR numEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ATOM_PPLIB_VCE_State_Record entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }ATOM_PPLIB_VCE_State_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) typedef struct _ATOM_PPLIB_VCE_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) // VCEClockInfoArray array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) // ATOM_PPLIB_VCE_State_Table states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }ATOM_PPLIB_VCE_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) typedef struct _UVDClockInfo{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) USHORT usVClkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) UCHAR ucVClkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) USHORT usDClkLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) UCHAR ucDClkHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }UVDClockInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) typedef struct _UVDClockInfoArray{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) UCHAR ucNumEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) UVDClockInfo entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }UVDClockInfoArray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) UCHAR ucUVDClockInfoIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) UCHAR numEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) typedef struct _ATOM_PPLIB_UVD_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) // UVDClockInfoArray array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }ATOM_PPLIB_UVD_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) USHORT usSAMClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) UCHAR ucSAMClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }ATOM_PPLIB_SAMClk_Voltage_Limit_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) UCHAR numEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) typedef struct _ATOM_PPLIB_SAMU_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }ATOM_PPLIB_SAMU_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) USHORT usACPClockLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) UCHAR ucACPClockHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }ATOM_PPLIB_ACPClk_Voltage_Limit_Record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) UCHAR numEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }ATOM_PPLIB_ACPClk_Voltage_Limit_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) typedef struct _ATOM_PPLIB_ACP_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }ATOM_PPLIB_ACP_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) typedef struct _ATOM_PowerTune_Table{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) USHORT usTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) USHORT usConfigurableTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) USHORT usTDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) USHORT usBatteryPowerLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) USHORT usSmallPowerLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) USHORT usLowCACLeakage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) USHORT usHighCACLeakage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }ATOM_PowerTune_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) typedef struct _ATOM_PPLIB_POWERTUNE_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ATOM_PowerTune_Table power_tune_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }ATOM_PPLIB_POWERTUNE_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) UCHAR revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ATOM_PowerTune_Table power_tune_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) USHORT usMaximumPowerDeliveryLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) USHORT usReserve[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } ATOM_PPLIB_POWERTUNE_Table_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define ATOM_PPM_A_A 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define ATOM_PPM_A_I 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) typedef struct _ATOM_PPLIB_PPM_Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) UCHAR ucRevId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) UCHAR ucPpmDesign; //A+I or A+A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) USHORT usCpuCoreNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ULONG ulPlatformTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ULONG ulSmallACPlatformTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ULONG ulPlatformTDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ULONG ulSmallACPlatformTDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ULONG ulApuTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ULONG ulDGpuTDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ULONG ulDGpuUlvPower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ULONG ulTjmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } ATOM_PPLIB_PPM_Table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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