Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright 2011 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #ifndef PP_SMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PP_SMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #pragma pack(push, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PPSMC_SWSTATE_FLAG_DC                           0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PPSMC_SWSTATE_FLAG_UVD                          0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PPSMC_SWSTATE_FLAG_VCE                          0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PPSMC_SWSTATE_FLAG_PCIE_X1                      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PPSMC_SYSTEMFLAG_GDDR5                          0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO        0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PPSMC_DISPLAY_WATERMARK_LOW                     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PPSMC_DISPLAY_WATERMARK_HIGH                    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PPSMC_STATEFLAG_POWERBOOST         0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define FDO_MODE_HARDWARE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define FDO_MODE_PIECE_WISE_LINEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) enum FAN_CONTROL {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	FAN_CONTROL_FUZZY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	FAN_CONTROL_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PPSMC_Result_OK             ((uint8_t)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PPSMC_Result_Failed         ((uint8_t)0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) typedef uint8_t PPSMC_Result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PPSMC_MSG_Halt                      ((uint8_t)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PPSMC_MSG_Resume                    ((uint8_t)0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PPSMC_MSG_ZeroLevelsDisabled        ((uint8_t)0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PPSMC_MSG_OneLevelsDisabled         ((uint8_t)0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PPSMC_MSG_TwoLevelsDisabled         ((uint8_t)0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PPSMC_MSG_EnableThermalInterrupt    ((uint8_t)0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PPSMC_MSG_RunningOnAC               ((uint8_t)0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PPSMC_MSG_SwitchToSwState           ((uint8_t)0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PPSMC_MSG_SwitchToInitialState      ((uint8_t)0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PPSMC_MSG_NoForcedLevel             ((uint8_t)0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PPSMC_MSG_ForceHigh                 ((uint8_t)0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PPSMC_MSG_ForceMediumOrHigh         ((uint8_t)0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PPSMC_MSG_SwitchToMinimumPower      ((uint8_t)0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PPSMC_MSG_ResumeFromMinimumPower    ((uint8_t)0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PPSMC_MSG_EnableCac                 ((uint8_t)0x53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PPSMC_MSG_DisableCac                ((uint8_t)0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PPSMC_TDPClampingActive             ((uint8_t)0x59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PPSMC_TDPClampingInactive           ((uint8_t)0x5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PPSMC_StartFanControl               ((uint8_t)0x5B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PPSMC_StopFanControl                ((uint8_t)0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PPSMC_MSG_NoDisplay                 ((uint8_t)0x5D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PPSMC_MSG_HasDisplay                ((uint8_t)0x5E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PPSMC_MSG_UVDPowerOFF               ((uint8_t)0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PPSMC_MSG_UVDPowerON                ((uint8_t)0x61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PPSMC_MSG_EnableULV                 ((uint8_t)0x62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PPSMC_MSG_DisableULV                ((uint8_t)0x63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PPSMC_MSG_EnterULV                  ((uint8_t)0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PPSMC_MSG_ExitULV                   ((uint8_t)0x65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PPSMC_CACLongTermAvgEnable          ((uint8_t)0x6E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PPSMC_CACLongTermAvgDisable         ((uint8_t)0x6F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint8_t)0x7A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PPSMC_FlushDataCache                ((uint8_t)0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PPSMC_MSG_SetEnabledLevels          ((uint8_t)0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PPSMC_MSG_SetForcedLevels           ((uint8_t)0x83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PPSMC_MSG_ResetToDefaults           ((uint8_t)0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PPSMC_MSG_EnableDTE                 ((uint8_t)0x87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PPSMC_MSG_DisableDTE                ((uint8_t)0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PPSMC_MSG_ThrottleOVRDSCLKDS        ((uint8_t)0x96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PPSMC_MSG_CancelThrottleOVRDSCLKDS  ((uint8_t)0x97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* CI/KV/KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* TN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PPSMC_MSG_DPM_Config                ((uint32_t) 0x102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PPSMC_MSG_DPM_ForceState            ((uint32_t) 0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PPSMC_MSG_PG_SIMD_Config            ((uint32_t) 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PPSMC_MSG_Thermal_Cntl_Enable       ((uint32_t) 0x10a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PPSMC_MSG_Voltage_Cntl_Enable       ((uint32_t) 0x109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PPSMC_MSG_VCEPowerOFF               ((uint32_t) 0x10e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PPSMC_MSG_VCEPowerON                ((uint32_t) 0x10f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PPSMC_MSG_DPM_N_LevelsDisabled      ((uint32_t) 0x112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PPSMC_MSG_DCE_RemoveVoltageAdjustment   ((uint32_t) 0x11d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PPSMC_MSG_DCE_AllowVoltageAdjustment    ((uint32_t) 0x11e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PPSMC_MSG_EnableBAPM                ((uint32_t) 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PPSMC_MSG_DisableBAPM               ((uint32_t) 0x121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PPSMC_MSG_UVD_DPM_Config            ((uint32_t) 0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) typedef uint16_t PPSMC_Msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #pragma pack(pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif