^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2010 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef NI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CAYMAN_MAX_SH_GPRS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAYMAN_MAX_TEMP_GPRS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CAYMAN_MAX_SH_THREADS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CAYMAN_MAX_SH_STACK_ENTRIES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CAYMAN_MAX_FRC_EOV_CNT 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CAYMAN_MAX_BACKENDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CAYMAN_MAX_BACKENDS_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAYMAN_MAX_SIMDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CAYMAN_MAX_PIPES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CAYMAN_MAX_PIPES_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CAYMAN_MAX_LDS_NUM 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CAYMAN_MAX_TCC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CAYMAN_MAX_TCC_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMIF_ADDR_CONFIG 0xBD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* fusion vce clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CG_ECLK_CNTL 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define ECLK_DIVIDER_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define ECLK_DIR_CNTL_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CG_ECLK_STATUS 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define ECLK_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* DCE6 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMIF_ADDR_CALC 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SRBM_GFX_CNTL 0x0E44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RINGID(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VMID(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRBM_STATUS 0x0E50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RLC_RQ_PENDING (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VMC_BUSY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCB_BUSY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCB_NON_DISPLAY_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCC_BUSY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCD_BUSY (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SEM_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RLC_BUSY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IH_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SRBM_SOFT_RESET 0x0E60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SOFT_RESET_BIF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOFT_RESET_CG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SOFT_RESET_DC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOFT_RESET_DMA1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SOFT_RESET_GRBM (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SOFT_RESET_HDP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SOFT_RESET_IH (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SOFT_RESET_MC (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOFT_RESET_RLC (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SOFT_RESET_ROM (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SOFT_RESET_SEM (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SOFT_RESET_VMC (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOFT_RESET_DMA (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOFT_RESET_TST (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SOFT_RESET_REGBB (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SOFT_RESET_ORB (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SRBM_READ_ERROR 0xE98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SRBM_INT_CNTL 0xEA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SRBM_INT_ACK 0xEA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SRBM_STATUS2 0x0EC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DMA_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DMA1_BUSY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RESPONSE_TYPE_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RESPONSE_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VM_L2_CNTL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ENABLE_L2_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* CONTEXT1_IDENTITY_ACCESS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 0 physical = logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * 1 logical via context1 page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * 2 inside identity aperture use translation, outside physical = logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 3 inside identity aperture physical = logical, outside use translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VM_L2_CNTL2 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INVALIDATE_ALL_L1_TLBS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INVALIDATE_L2_CACHE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VM_L2_CNTL3 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BANK_SELECT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CACHE_UPDATE_MODE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VM_L2_STATUS 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define L2_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VM_CONTEXT0_CNTL 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ENABLE_CONTEXT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VM_CONTEXT1_CNTL 0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VM_CONTEXT0_CNTL2 0x1430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VM_CONTEXT1_CNTL2 0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VM_INVALIDATE_REQUEST 0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VM_INVALIDATE_RESPONSE 0x147c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PROTECTIONS_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PROTECTIONS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* bit 0: range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * bit 2: pde0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * bit 3: valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * bit 4: read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * bit 5: write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MEMORY_CLIENT_ID_MASK (0xff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MEMORY_CLIENT_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MEMORY_CLIENT_RW_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MEMORY_CLIENT_RW_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FAULT_VMID_MASK (0x7 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FAULT_VMID_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MC_SHARED_CHMAP 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define NOOFCHAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define NOOFCHAN_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MC_SHARED_CHREMAP 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MC_VM_MX_L1_TLB_CNTL 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ENABLE_L1_TLB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FUS_MC_VM_FB_OFFSET 0x2068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MC_SHARED_BLACKOUT_CNTL 0x20ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MC_ARB_RAMCFG 0x2760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define NOOFBANK_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define NOOFRANK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define NOOFRANK_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define NOOFROWS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define NOOFROWS_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define NOOFCOLS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define NOOFCOLS_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CHANSIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CHANSIZE_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BURSTLENGTH_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BURSTLENGTH_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CHANSIZE_OVERRIDE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MC_SEQ_SUP_CNTL 0x28c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RUN_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MC_SEQ_SUP_PGM 0x28cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MC_IO_PAD_CNTL_D0 0x29d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MEM_FALL_OUT_CMD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MC_SEQ_IO_DEBUG_DATA 0x2a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HDP_HOST_PATH_CNTL 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HDP_NONSURFACE_BASE 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HDP_NONSURFACE_INFO 0x2C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HDP_NONSURFACE_SIZE 0x2C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HDP_ADDR_CONFIG 0x2F48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HDP_MISC_CNTL 0x2F4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CGTS_SYS_TCC_DISABLE 0x3F90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RLC_GFX_INDEX 0x3FC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CONFIG_MEMSIZE 0x5428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GRBM_CNTL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GRBM_READ_TIMEOUT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CMDFIFO_AVAIL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define RING2_RQ_PENDING (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define RING1_RQ_PENDING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CF_RQ_PENDING (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PF_RQ_PENDING (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GDS_DMA_RQ_PENDING (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GRBM_EE_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SX_CLEAN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DB_CLEAN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CB_CLEAN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TA_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GDS_BUSY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VGT_BUSY_NO_DMA (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VGT_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IA_BUSY_NO_DMA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IA_BUSY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SX_BUSY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SH_BUSY (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SPI_BUSY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SC_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DB_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CP_COHERENCY_BUSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CP_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GUI_ACTIVE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GRBM_STATUS_SE0 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GRBM_STATUS_SE1 0x8018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SE_SX_CLEAN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SE_DB_CLEAN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SE_CB_CLEAN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SE_VGT_BUSY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SE_PA_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SE_TA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SE_SX_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SE_SPI_BUSY (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SE_SH_BUSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SE_SC_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SE_DB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SE_CB_BUSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SOFT_RESET_CP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SOFT_RESET_CB (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SOFT_RESET_DB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SOFT_RESET_GDS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SOFT_RESET_PA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SOFT_RESET_SC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SOFT_RESET_SPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SOFT_RESET_SH (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SOFT_RESET_SX (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SOFT_RESET_TC (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SOFT_RESET_TA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SOFT_RESET_VGT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SOFT_RESET_IA (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GRBM_GFX_INDEX 0x802C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define INSTANCE_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SE_INDEX(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define INSTANCE_BROADCAST_WRITES (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SE_BROADCAST_WRITES (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SCRATCH_REG0 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SCRATCH_REG1 0x8504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SCRATCH_REG2 0x8508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SCRATCH_REG3 0x850C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SCRATCH_REG4 0x8510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SCRATCH_REG5 0x8514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SCRATCH_REG6 0x8518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SCRATCH_REG7 0x851C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SCRATCH_UMSK 0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SCRATCH_ADDR 0x8544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CP_SEM_WAIT_TIMER 0x85BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CP_COHER_CNTL2 0x85E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CP_STALLED_STAT1 0x8674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CP_STALLED_STAT2 0x8678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CP_BUSY_STAT 0x867C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CP_STAT 0x8680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CP_ME_CNTL 0x86D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CP_ME_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CP_PFP_HALT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CP_RB2_RPTR 0x86f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CP_RB1_RPTR 0x86fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CP_RB0_RPTR 0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CP_RB_WPTR_DELAY 0x8704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CP_MEQ_THRESHOLDS 0x8764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MEQ1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MEQ2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CP_PERFMON_CNTL 0x87FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define VGT_CACHE_INVALIDATION 0x88C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CACHE_INVALIDATION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define VC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TC_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define VC_AND_TC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AUTO_INVLD_EN(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define NO_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ES_AUTO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GS_AUTO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ES_AND_GS_AUTO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define VGT_GS_VERTEX_REUSE 0x88D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CC_GC_SHADER_PIPE_CONFIG 0x8950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GC_USER_SHADER_PIPE_CONFIG 0x8954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define INACTIVE_QD_PIPES(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define INACTIVE_QD_PIPES_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define INACTIVE_QD_PIPES_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define INACTIVE_SIMDS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define INACTIVE_SIMDS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define INACTIVE_SIMDS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define VGT_PRIMITIVE_TYPE 0x8958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define VGT_NUM_INSTANCES 0x8974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define VGT_TF_RING_SIZE 0x8988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define VGT_OFFCHIP_LDS_BASE 0x89b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PA_SC_LINE_STIPPLE_STATE 0x8B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PA_CL_ENHANCE 0x8A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLIP_VTX_REORDER_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define NUM_CLIP_SEQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PA_SC_FIFO_SIZE 0x8BCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SQ_CONFIG 0x8C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define VC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define EXPORT_SRC_C (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define GFX_PRIO(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CS1_PRIO(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CS2_PRIO(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define NUM_PS_GPRS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define NUM_VS_GPRS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SQ_ESGS_RING_SIZE 0x8c44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SQ_GSVS_RING_SIZE 0x8c4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SQ_ESTMP_RING_BASE 0x8c50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SQ_ESTMP_RING_SIZE 0x8c54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SQ_GSTMP_RING_BASE 0x8c58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SQ_GSTMP_RING_SIZE 0x8c5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SQ_VSTMP_RING_BASE 0x8c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SQ_VSTMP_RING_SIZE 0x8c64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SQ_PSTMP_RING_BASE 0x8c68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SQ_PSTMP_RING_SIZE 0x8c6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SQ_MS_FIFO_SIZES 0x8CF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CACHE_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define FETCH_FIFO_HIWATER(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DONE_FIFO_HIWATER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SQ_LSTMP_RING_BASE 0x8e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SQ_LSTMP_RING_SIZE 0x8e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SQ_HSTMP_RING_BASE 0x8e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SQ_HSTMP_RING_SIZE 0x8e1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DYN_GPR_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SQ_CONST_MEM_BASE 0x8df8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SX_EXPORT_BUFFER_SIZES 0x900C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define COLOR_BUFFER_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define POSITION_BUFFER_SIZE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SMX_BUFFER_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SX_DEBUG_1 0x9058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SPI_CONFIG_CNTL 0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define GPR_WRITE_PRIORITY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SPI_CONFIG_CNTL_1 0x913C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define VTX_DONE_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CGTS_TCC_DISABLE 0x9148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CGTS_USER_TCC_DISABLE 0x914C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define TCC_DISABLE_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define TCC_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CGTS_SM_CTRL_REG 0x9150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define OVERRIDE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define TA_CNTL_AUX 0x9508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DISABLE_CUBE_WRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DISABLE_CUBE_ANISO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TCP_CHAN_STEER_LO 0x960c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TCP_CHAN_STEER_HI 0x9610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CC_RB_BACKEND_DISABLE 0x98F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define GB_ADDR_CONFIG 0x98F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define NUM_PIPES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define NUM_PIPES_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define NUM_PIPES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PIPE_INTERLEAVE_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define NUM_SHADER_ENGINES(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define NUM_SHADER_ENGINES_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define NUM_SHADER_ENGINES_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define NUM_GPUS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define NUM_GPUS_MASK 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define NUM_GPUS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MULTI_GPU_TILE_SIZE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define ROW_SIZE(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define ROW_SIZE_MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define ROW_SIZE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define NUM_LOWER_PIPES(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define NUM_LOWER_PIPES_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define NUM_LOWER_PIPES_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define GB_BACKEND_MAP 0x98FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CB_PERF_CTR0_SEL_0 0x9A20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CB_PERF_CTR0_SEL_1 0x9A24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CB_PERF_CTR1_SEL_0 0x9A28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CB_PERF_CTR1_SEL_1 0x9A2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CB_PERF_CTR2_SEL_0 0x9A30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CB_PERF_CTR2_SEL_1 0x9A34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CB_PERF_CTR3_SEL_0 0x9A38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CB_PERF_CTR3_SEL_1 0x9A3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define BACKEND_DISABLE_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define BACKEND_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SMX_DC_CTL0 0xA020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define USE_HASH_FUNCTION (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define NUMBER_OF_SETS(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define FLUSH_ALL_ON_EVENT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define STALL_ON_EVENT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SMX_EVENT_CTL 0xA02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ES_FLUSH_CTL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GS_FLUSH_CTL(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ACK_FLUSH_CTL(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SYNC_FLUSH_CTL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CP_RB0_BASE 0xC100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define CP_RB0_CNTL 0xC104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RB_BUFSZ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RB_BLKSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RB_NO_UPDATE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define RB_RPTR_WR_ENA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define BUF_SWAP_32BIT (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CP_RB0_RPTR_ADDR 0xC10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CP_RB0_RPTR_ADDR_HI 0xC110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CP_RB0_WPTR 0xC114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define CP_INT_CNTL 0xC124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) # define CNTX_BUSY_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) # define CNTX_EMPTY_INT_ENABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) # define TIME_STAMP_INT_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define CP_RB1_BASE 0xC180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define CP_RB1_CNTL 0xC184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CP_RB1_RPTR_ADDR 0xC188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define CP_RB1_RPTR_ADDR_HI 0xC18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define CP_RB1_WPTR 0xC190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CP_RB2_BASE 0xC194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CP_RB2_CNTL 0xC198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CP_RB2_RPTR_ADDR 0xC19C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define CP_RB2_RPTR_ADDR_HI 0xC1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CP_RB2_WPTR 0xC1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define CP_PFP_UCODE_ADDR 0xC150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CP_PFP_UCODE_DATA 0xC154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CP_ME_RAM_RADDR 0xC158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define CP_ME_RAM_WADDR 0xC15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define CP_ME_RAM_DATA 0xC160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CP_DEBUG 0xC1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define VGT_EVENT_INITIATOR 0x28a90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* TN SMU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define TN_CURRENT_GNB_TEMP 0x1F390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* pm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SMC_MSG 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define HOST_SMC_MSG(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define HOST_SMC_MSG_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HOST_SMC_MSG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define HOST_SMC_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define HOST_SMC_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define HOST_SMC_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SMC_HOST_MSG(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SMC_HOST_MSG_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SMC_HOST_MSG_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SMC_HOST_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SMC_HOST_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SMC_HOST_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define CG_SPLL_FUNC_CNTL 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SPLL_SLEEP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SPLL_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SPLL_REF_DIV_MASK (0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SPLL_PDIV_A(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SPLL_PDIV_A_MASK (0x7f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SPLL_PDIV_A_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CG_SPLL_FUNC_CNTL_2 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CG_SPLL_FUNC_CNTL_3 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SPLL_FB_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MPLL_CNTL_MODE 0x61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) # define SS_SSEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) # define SS_DSMODE_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MPLL_AD_FUNC_CNTL 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define CLKF(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define CLKF_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define CLKR(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CLKR_MASK (0x1f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define CLKFRAC(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define CLKFRAC_MASK (0x1f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define YCLK_POST_DIV(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define YCLK_POST_DIV_MASK (3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define IBIAS(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IBIAS_MASK (0x3ff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define PDNB (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MPLL_AD_FUNC_CNTL_2 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define BYPASS (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define BIAS_GEN_PDNB (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define RESET_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define VCO_MODE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MPLL_DQ_FUNC_CNTL 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MPLL_DQ_FUNC_CNTL_2 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define GENERAL_PWRMGT 0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) # define ENABLE_GEN2PCIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) # define ENABLE_GEN2XSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) # define SW_SMIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) # define SW_SMIO_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) # define BACKBIAS_PAD_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) # define BACKBIAS_VALUE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) # define AC_DC_SW (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SCLK_PWRMGT_CNTL 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) # define SCLK_LOW_D1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) # define FIR_RESET (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) # define FIR_FORCE_TREND_SEL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) # define FIR_TREND_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) # define DYN_GFX_CLK_OFF_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) # define GFX_CLK_FORCE_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) # define GFX_CLK_REQUEST_OFF (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) # define GFX_CLK_FORCE_OFF (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) # define DYN_LIGHT_SLEEP_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MCLK_PWRMGT_CNTL 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) # define DLL_SPEED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) # define DLL_SPEED_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) # define MPLL_PWRMGT_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) # define MRDCKA0_PDNB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) # define MRDCKA1_PDNB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) # define MRDCKB0_PDNB (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) # define MRDCKB1_PDNB (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) # define MRDCKC0_PDNB (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) # define MRDCKC1_PDNB (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) # define MRDCKD0_PDNB (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) # define MRDCKD1_PDNB (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) # define MRDCKA0_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) # define MRDCKA1_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) # define MRDCKB0_RESET (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) # define MRDCKB1_RESET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) # define MRDCKC0_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) # define MRDCKC1_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) # define MRDCKD0_RESET (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) # define MRDCKD1_RESET (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) # define USE_DISPLAY_GAP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) # define MPLL_TURNOFF_D2 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define DLL_CNTL 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) # define MRDCKA0_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) # define MRDCKA1_BYPASS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) # define MRDCKB0_BYPASS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) # define MRDCKB1_BYPASS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) # define MRDCKC0_BYPASS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) # define MRDCKC1_BYPASS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) # define MRDCKD0_BYPASS (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) # define MRDCKD1_BYPASS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) # define CURRENT_STATE_INDEX_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) # define CURRENT_STATE_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define CG_AT 0x6d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) # define CG_R(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) # define CG_R_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) # define CG_L(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) # define CG_L_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define CG_BIF_REQ_AND_RSP 0x7f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define CG_CLIENT_REQ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define CG_CLIENT_REQ_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define CG_CLIENT_REQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define CG_CLIENT_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define CG_CLIENT_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define CG_CLIENT_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define CLIENT_CG_REQ(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define CLIENT_CG_REQ_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define CLIENT_CG_REQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define CLIENT_CG_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define CLIENT_CG_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define CLIENT_CG_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define CG_SPLL_SPREAD_SPECTRUM 0x790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define CLK_S(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define CLK_S_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define CLK_S_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define CLK_V(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define CLK_V_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define CLK_V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SMC_SCRATCH0 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define CG_SPLL_FUNC_CNTL_4 0x850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MPLL_SS1 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define CLKV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define CLKV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define MPLL_SS2 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define CLKS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define CLKS_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define CG_CAC_CTRL 0x88c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define TID_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define TID_CNT_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define TID_UNIT(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TID_UNIT_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define CG_IND_ADDR 0x8f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define CG_IND_DATA 0x8fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* CGIND regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define CG_CGTT_LOCAL_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define CG_CGTT_LOCAL_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define MC_CG_CONFIG 0x25bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define MCDW_WR_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define MCDX_WR_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define MCDY_WR_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MCDZ_WR_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define MC_RD_ENABLE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define MC_RD_ENABLE_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define INDEX_MASK (0xfff << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define MC_ARB_CAC_CNTL 0x2750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define READ_WEIGHT(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define READ_WEIGHT_MASK (0x3f << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define READ_WEIGHT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define WRITE_WEIGHT(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define WRITE_WEIGHT_MASK (0x3f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define WRITE_WEIGHT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define ALLOW_OVERFLOW (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define MC_ARB_DRAM_TIMING 0x2774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define MC_ARB_DRAM_TIMING2 0x2778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define MC_ARB_RFSH_RATE 0x27b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define POWERMODE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define POWERMODE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define POWERMODE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define POWERMODE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define POWERMODE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define POWERMODE1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define POWERMODE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define POWERMODE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define POWERMODE2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define POWERMODE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define POWERMODE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define POWERMODE3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define MC_ARB_CG 0x27e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define CG_ARB_REQ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define CG_ARB_REQ_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define CG_ARB_REQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define CG_ARB_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define CG_ARB_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define CG_ARB_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define ARB_CG_REQ(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define ARB_CG_REQ_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define ARB_CG_REQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define ARB_CG_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define ARB_CG_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define ARB_CG_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define MC_ARB_DRAM_TIMING_1 0x27f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define MC_ARB_DRAM_TIMING_2 0x27f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define MC_ARB_DRAM_TIMING_3 0x27f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define MC_ARB_DRAM_TIMING2_1 0x27fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define MC_ARB_DRAM_TIMING2_2 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define MC_ARB_DRAM_TIMING2_3 0x2804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define MC_ARB_BURST_TIME 0x2808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define STATE0_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define STATE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define STATE1(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define STATE1_MASK (0x1f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define STATE1_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define STATE2(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define STATE2_MASK (0x1f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define STATE2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define STATE3(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define STATE3_MASK (0x1f << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define STATE3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MC_CG_DATAPORT 0x2884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MC_SEQ_RAS_TIMING 0x28a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MC_SEQ_CAS_TIMING 0x28a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MC_SEQ_MISC_TIMING 0x28a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MC_SEQ_MISC_TIMING2 0x28ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MC_SEQ_PMG_TIMING 0x28b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MC_SEQ_RD_CTL_D0 0x28b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MC_SEQ_RD_CTL_D1 0x28b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MC_SEQ_WR_CTL_D0 0x28bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MC_SEQ_WR_CTL_D1 0x28c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MC_SEQ_MISC1 0x2a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define MC_SEQ_RESERVE_M 0x2a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define MC_PMG_CMD_EMRS 0x2a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MC_SEQ_MISC3 0x2a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define MC_SEQ_MISC5 0x2a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define MC_SEQ_MISC6 0x2a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define MC_SEQ_MISC7 0x2a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define MC_SEQ_RAS_TIMING_LP 0x2a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define MC_SEQ_CAS_TIMING_LP 0x2a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MC_SEQ_MISC_TIMING_LP 0x2a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define MC_SEQ_MISC_TIMING2_LP 0x2a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define MC_SEQ_WR_CTL_D1_LP 0x2a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define MC_PMG_CMD_MRS 0x2aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define MC_SEQ_RD_CTL_D1_LP 0x2b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MC_PMG_CMD_MRS1 0x2b44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MC_SEQ_PMG_TIMING_LP 0x2b4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define MC_PMG_CMD_MRS2 0x2b5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define AUX_CONTROL 0x6200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define AUX_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define AUX_LS_READ_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define AUX_DET_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define AUX_HPD_SEL(x) (((x) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define AUX_IMPCAL_REQ_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define AUX_TEST_MODE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define AUX_DEGLITCH_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define AUX_SW_CONTROL 0x6204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define AUX_SW_GO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define AUX_LS_READ_TRIG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define AUX_SW_INTERRUPT_CONTROL 0x620c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define AUX_SW_DONE_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define AUX_SW_DONE_ACK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define AUX_SW_DONE_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define AUX_SW_LS_DONE_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define AUX_SW_LS_DONE_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define AUX_SW_STATUS 0x6210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define AUX_SW_DONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define AUX_SW_REQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define AUX_SW_RX_TIMEOUT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define AUX_SW_RX_OVERFLOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define AUX_SW_RX_HPD_DISCON (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define AUX_SW_RX_PARTIAL_BYTE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define AUX_SW_NON_AUX_MODE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define AUX_SW_RX_INVALID_STOP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define AUX_SW_RX_SYNC_INVALID_L (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define AUX_SW_RX_SYNC_INVALID_H (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define AUX_SW_RX_INVALID_START (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define AUX_SW_RX_RECV_NO_DET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define AUX_SW_RX_RECV_INVALID_H (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define AUX_SW_RX_RECV_INVALID_V (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define AUX_SW_DATA 0x6218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define AUX_SW_DATA_RW (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define LB_SYNC_RESET_SEL 0x6b28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define LB_SYNC_RESET_SEL_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define LB_SYNC_RESET_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DC_STUTTER_CNTL 0x6b30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DC_STUTTER_ENABLE_A (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define DC_STUTTER_ENABLE_B (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define SQ_CAC_THRESHOLD 0x8e4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define VSP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define VSP_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define VSP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define VSP0(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define VSP0_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define VSP0_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define GPR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define GPR_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define GPR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SQ_POWER_THROTTLE 0x8e58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MIN_POWER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MIN_POWER_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define MIN_POWER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define MAX_POWER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MAX_POWER_MASK (0x3fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MAX_POWER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define SQ_POWER_THROTTLE2 0x8e5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MAX_POWER_DELTA(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MAX_POWER_DELTA_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MAX_POWER_DELTA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define STI_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define STI_SIZE_MASK (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define STI_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define LTI_RATIO(x) ((x) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define LTI_RATIO_MASK (0xf << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define LTI_RATIO_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* CG indirect registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define CG_CAC_REGION_1_WEIGHT_0 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define WEIGHT_TCP_SIG0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define WEIGHT_TCP_SIG0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define WEIGHT_TCP_SIG0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define WEIGHT_TCP_SIG1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define WEIGHT_TCP_SIG1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define WEIGHT_TCP_SIG1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define WEIGHT_TA_SIG(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define WEIGHT_TA_SIG_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define WEIGHT_TA_SIG_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define CG_CAC_REGION_1_WEIGHT_1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define WEIGHT_TCC_EN0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define WEIGHT_TCC_EN0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define WEIGHT_TCC_EN0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define WEIGHT_TCC_EN1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define WEIGHT_TCC_EN1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define WEIGHT_TCC_EN1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define WEIGHT_TCC_EN2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define WEIGHT_TCC_EN2_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define WEIGHT_TCC_EN2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define WEIGHT_TCC_EN3(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define WEIGHT_TCC_EN3_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define WEIGHT_TCC_EN3_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define CG_CAC_REGION_2_WEIGHT_0 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define WEIGHT_CB_EN0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define WEIGHT_CB_EN0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define WEIGHT_CB_EN0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define WEIGHT_CB_EN1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define WEIGHT_CB_EN1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define WEIGHT_CB_EN1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define WEIGHT_CB_EN2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define WEIGHT_CB_EN2_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define WEIGHT_CB_EN2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define WEIGHT_CB_EN3(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define WEIGHT_CB_EN3_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define WEIGHT_CB_EN3_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define CG_CAC_REGION_2_WEIGHT_1 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define WEIGHT_DB_SIG0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define WEIGHT_DB_SIG0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define WEIGHT_DB_SIG0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define WEIGHT_DB_SIG1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define WEIGHT_DB_SIG1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define WEIGHT_DB_SIG1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define WEIGHT_DB_SIG2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define WEIGHT_DB_SIG2_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define WEIGHT_DB_SIG2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define WEIGHT_DB_SIG3(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define WEIGHT_DB_SIG3_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define WEIGHT_DB_SIG3_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define CG_CAC_REGION_2_WEIGHT_2 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define WEIGHT_SXM_SIG0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define WEIGHT_SXM_SIG0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define WEIGHT_SXM_SIG0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define WEIGHT_SXM_SIG1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define WEIGHT_SXM_SIG1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define WEIGHT_SXM_SIG1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define WEIGHT_SXM_SIG2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define WEIGHT_SXM_SIG2_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define WEIGHT_SXM_SIG2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define WEIGHT_SXS_SIG0(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define WEIGHT_SXS_SIG0_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define WEIGHT_SXS_SIG0_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define WEIGHT_SXS_SIG1(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define WEIGHT_SXS_SIG1_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define WEIGHT_SXS_SIG1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define CG_CAC_REGION_3_WEIGHT_0 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define WEIGHT_XBR_0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define WEIGHT_XBR_0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define WEIGHT_XBR_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define WEIGHT_XBR_1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define WEIGHT_XBR_1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define WEIGHT_XBR_1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define WEIGHT_XBR_2(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define WEIGHT_XBR_2_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define WEIGHT_XBR_2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define WEIGHT_SPI_SIG0(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define WEIGHT_SPI_SIG0_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define WEIGHT_SPI_SIG0_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define CG_CAC_REGION_3_WEIGHT_1 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define WEIGHT_SPI_SIG1(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define WEIGHT_SPI_SIG1_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define WEIGHT_SPI_SIG1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define WEIGHT_SPI_SIG2(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define WEIGHT_SPI_SIG2_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define WEIGHT_SPI_SIG2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define WEIGHT_SPI_SIG3(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define WEIGHT_SPI_SIG3_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define WEIGHT_SPI_SIG3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define WEIGHT_SPI_SIG4(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define WEIGHT_SPI_SIG4_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define WEIGHT_SPI_SIG4_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define WEIGHT_SPI_SIG5(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define WEIGHT_SPI_SIG5_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define WEIGHT_SPI_SIG5_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define CG_CAC_REGION_4_WEIGHT_0 0x8a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define WEIGHT_LDS_SIG0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define WEIGHT_LDS_SIG0_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define WEIGHT_LDS_SIG0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define WEIGHT_LDS_SIG1(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define WEIGHT_LDS_SIG1_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define WEIGHT_LDS_SIG1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define WEIGHT_SC(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define WEIGHT_SC_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define WEIGHT_SC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define CG_CAC_REGION_4_WEIGHT_1 0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define WEIGHT_BIF(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define WEIGHT_BIF_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define WEIGHT_BIF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define WEIGHT_CP(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define WEIGHT_CP_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define WEIGHT_CP_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define WEIGHT_PA_SIG0(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define WEIGHT_PA_SIG0_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define WEIGHT_PA_SIG0_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define WEIGHT_PA_SIG1(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define WEIGHT_PA_SIG1_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define WEIGHT_PA_SIG1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define WEIGHT_VGT_SIG0(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define WEIGHT_VGT_SIG0_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define WEIGHT_VGT_SIG0_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define CG_CAC_REGION_4_WEIGHT_2 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define WEIGHT_VGT_SIG1(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define WEIGHT_VGT_SIG1_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define WEIGHT_VGT_SIG1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define WEIGHT_VGT_SIG2(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define WEIGHT_VGT_SIG2_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define WEIGHT_VGT_SIG2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define WEIGHT_DC_SIG0(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define WEIGHT_DC_SIG0_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define WEIGHT_DC_SIG0_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define WEIGHT_DC_SIG1(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define WEIGHT_DC_SIG1_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define WEIGHT_DC_SIG1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define WEIGHT_DC_SIG2(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define WEIGHT_DC_SIG2_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define WEIGHT_DC_SIG2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define CG_CAC_REGION_4_WEIGHT_3 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define WEIGHT_DC_SIG3(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define WEIGHT_DC_SIG3_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define WEIGHT_DC_SIG3_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define WEIGHT_UVD_SIG0(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define WEIGHT_UVD_SIG0_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define WEIGHT_UVD_SIG0_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define WEIGHT_UVD_SIG1(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define WEIGHT_UVD_SIG1_MASK (0x3f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define WEIGHT_UVD_SIG1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define WEIGHT_SPARE0(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define WEIGHT_SPARE0_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define WEIGHT_SPARE0_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define WEIGHT_SPARE1(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define WEIGHT_SPARE1_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define WEIGHT_SPARE1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define CG_CAC_REGION_5_WEIGHT_0 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define WEIGHT_SQ_VSP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define WEIGHT_SQ_VSP_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define WEIGHT_SQ_VSP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define WEIGHT_SQ_VSP0(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define WEIGHT_SQ_VSP0_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define CG_CAC_REGION_4_OVERRIDE_4 0xab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define OVR_MODE_SPARE_0(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define OVR_MODE_SPARE_0_MASK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define OVR_MODE_SPARE_0_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define OVR_VAL_SPARE_0(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define OVR_VAL_SPARE_0_MASK (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define OVR_VAL_SPARE_0_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define OVR_MODE_SPARE_1(x) ((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define OVR_MODE_SPARE_1_MASK (0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define OVR_MODE_SPARE_1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define OVR_VAL_SPARE_1(x) ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define OVR_VAL_SPARE_1_MASK (0x3f << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define OVR_VAL_SPARE_1_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define CG_CAC_REGION_5_WEIGHT_1 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define WEIGHT_SQ_GPR(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define WEIGHT_SQ_GPR_MASK (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define WEIGHT_SQ_GPR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define WEIGHT_SQ_LDS(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define WEIGHT_SQ_LDS_MASK (0x3fff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define WEIGHT_SQ_LDS_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* PCIE link stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) # define LC_LINK_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) # define LC_LINK_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) # define LC_LINK_WIDTH_X0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) # define LC_LINK_WIDTH_X1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) # define LC_LINK_WIDTH_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) # define LC_LINK_WIDTH_X4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) # define LC_LINK_WIDTH_X8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) # define LC_LINK_WIDTH_X16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) # define LC_LINK_WIDTH_RD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) # define LC_LINK_WIDTH_RD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) # define LC_RECONFIG_NOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) # define LC_RENEGOTIATION_SUPPORT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) # define LC_RENEGOTIATE_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) # define LC_SHORT_RECONFIG_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) # define LC_UPCONFIGURE_SUPPORT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) # define LC_UPCONFIGURE_DIS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) # define LC_CURRENT_DATA_RATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define MM_CFGREGS_CNTL 0x544c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) # define MM_WR_TO_CFG_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define LINK_CNTL2 0x88 /* F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) # define TARGET_LINK_SPEED_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) # define SELECTABLE_DEEMPHASIS (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * UVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define UVD_SEMA_ADDR_LOW 0xEF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define UVD_SEMA_ADDR_HIGH 0xEF04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define UVD_SEMA_CMD 0xEF08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define UVD_UDEC_ADDR_CONFIG 0xEF4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define UVD_NO_OP 0xEFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define UVD_RBC_RB_RPTR 0xF690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define UVD_RBC_RB_WPTR 0xF694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define UVD_STATUS 0xf6bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * PM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) (((reg) >> 2) & 0xFFFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) (((op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Packet 3 types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define PACKET3_SET_BASE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define PACKET3_CLEAR_STATE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define PACKET3_INDEX_BUFFER_SIZE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define PACKET3_DEALLOC_STATE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define PACKET3_DISPATCH_DIRECT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define PACKET3_DISPATCH_INDIRECT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define PACKET3_INDIRECT_BUFFER_END 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define PACKET3_MODE_CONTROL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define PACKET3_SET_PREDICATION 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define PACKET3_REG_RMW 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define PACKET3_COND_EXEC 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define PACKET3_PRED_EXEC 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define PACKET3_DRAW_INDIRECT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define PACKET3_DRAW_INDEX_INDIRECT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define PACKET3_INDEX_BASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define PACKET3_DRAW_INDEX_2 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define PACKET3_CONTEXT_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define PACKET3_DRAW_INDEX_OFFSET 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define PACKET3_INDEX_TYPE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define PACKET3_DRAW_INDEX 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define PACKET3_DRAW_INDEX_AUTO 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define PACKET3_DRAW_INDEX_IMMD 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define PACKET3_NUM_INSTANCES 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define PACKET3_INDIRECT_BUFFER 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define PACKET3_WRITE_DATA 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define PACKET3_MEM_SEMAPHORE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define PACKET3_MPEG_INDEX 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define PACKET3_WAIT_REG_MEM 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* 0 - always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * 1 - <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * 2 - <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * 3 - ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * 4 - !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * 5 - >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * 6 - >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* 0 - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * 1 - mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* 0 - me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * 1 - pfp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define PACKET3_MEM_WRITE 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define PACKET3_PFP_SYNC_ME 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define PACKET3_SURFACE_SYNC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) # define PACKET3_FULL_CACHE_ENA (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) # define PACKET3_TC_ACTION_ENA (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) # define PACKET3_CB_ACTION_ENA (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) # define PACKET3_DB_ACTION_ENA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) # define PACKET3_SH_ACTION_ENA (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) # define PACKET3_SX_ACTION_ENA (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) # define PACKET3_ENGINE_ME (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define PACKET3_ME_INITIALIZE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define PACKET3_COND_WRITE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define PACKET3_EVENT_WRITE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define EVENT_TYPE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define EVENT_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* 0 - any non-TS event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * 1 - ZPASS_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * 2 - SAMPLE_PIPELINESTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * 3 - SAMPLE_STREAMOUTSTAT*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * 4 - *S_PARTIAL_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * 5 - TS events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define PACKET3_EVENT_WRITE_EOP 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define DATA_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* 0 - discard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * 1 - send low 32bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * 2 - send 64bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * 3 - send 64bit counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define INT_SEL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * 1 - interrupt only (DATA_SEL = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * 2 - interrupt when data write is confirmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define PACKET3_EVENT_WRITE_EOS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define PACKET3_PREAMBLE_CNTL 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define PACKET3_ONE_REG_WRITE 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define PACKET3_SET_CONFIG_REG 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PACKET3_SET_CONFIG_REG_START 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define PACKET3_SET_CONTEXT_REG 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define PACKET3_SET_CONTEXT_REG_START 0x00028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define PACKET3_SET_CONTEXT_REG_END 0x00029000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define PACKET3_SET_ALU_CONST 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* alu const buffers only; no reg file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define PACKET3_SET_BOOL_CONST 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define PACKET3_SET_BOOL_CONST_START 0x0003a500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define PACKET3_SET_BOOL_CONST_END 0x0003a518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define PACKET3_SET_LOOP_CONST 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define PACKET3_SET_LOOP_CONST_START 0x0003a200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define PACKET3_SET_LOOP_CONST_END 0x0003a500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define PACKET3_SET_RESOURCE 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define PACKET3_SET_RESOURCE_START 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define PACKET3_SET_RESOURCE_END 0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define PACKET3_SET_SAMPLER 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define PACKET3_SET_SAMPLER_START 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define PACKET3_SET_SAMPLER_END 0x0003c600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define PACKET3_SET_CTL_CONST 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define PACKET3_SET_CTL_CONST_START 0x0003cff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define PACKET3_SET_RESOURCE_OFFSET 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PACKET3_SET_ALU_CONST_VS 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define PACKET3_SET_ALU_CONST_DI 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define PACKET3_SET_RESOURCE_INDIRECT 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define PACKET3_SET_APPEND_CNT 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define PACKET3_ME_WRITE 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define DMA_RB_CNTL 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) # define DMA_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define DMA_RB_BASE 0xd004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define DMA_RB_RPTR 0xd008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define DMA_RB_WPTR 0xd00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define DMA_RB_RPTR_ADDR_HI 0xd01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define DMA_RB_RPTR_ADDR_LO 0xd020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define DMA_IB_CNTL 0xd024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) # define DMA_IB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) # define DMA_IB_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) # define CMD_VMID_FORCE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define DMA_IB_RPTR 0xd028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define DMA_CNTL 0xd02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) # define TRAP_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) # define SEM_WAIT_INT_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) # define DATA_SWAP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) # define FENCE_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) # define CTXEMPTY_INT_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define DMA_STATUS_REG 0xd034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) # define DMA_IDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define DMA_TILING_CONFIG 0xd0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define DMA_MODE 0xd0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (((t) & 0x1) << 23) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) (((s) & 0x1) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) (((vmid) & 0xF) << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) (1 << 26) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) (1 << 21) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) (((n) & 0xFFFFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define DMA_SRBM_POLL_PACKET ((9 << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) (1 << 27) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) (1 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define DMA_SRBM_READ_PACKET ((9 << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) (1 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* async DMA Packet types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define DMA_PACKET_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define DMA_PACKET_COPY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define DMA_PACKET_INDIRECT_BUFFER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define DMA_PACKET_SEMAPHORE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define DMA_PACKET_FENCE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define DMA_PACKET_TRAP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define DMA_PACKET_SRBM_WRITE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define DMA_PACKET_CONSTANT_FILL 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define DMA_PACKET_NOP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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