^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2012 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef CIK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CIK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CIK_RB_BITMAP_WIDTH_PER_SH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* DIDT IND registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DIDT_SQ_CTRL0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define DIDT_CTRL_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DIDT_DB_CTRL0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DIDT_TD_CTRL0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DIDT_TCP_CTRL0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* SMC IND registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DPM_TABLE_475 0x3F768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define SamuBootLevel(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define SamuBootLevel_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define SamuBootLevel_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define AcpBootLevel(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define AcpBootLevel_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # define AcpBootLevel_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define VceBootLevel(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define VceBootLevel_MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) # define VceBootLevel_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define UvdBootLevel(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define UvdBootLevel_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define UvdBootLevel_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FIRMWARE_FLAGS 0x3F800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define INTERRUPTS_ENABLED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NB_DPM_CONFIG_1 0x3F9E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define Dpm0PgNbPsLo(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define Dpm0PgNbPsLo_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define Dpm0PgNbPsLo_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define Dpm0PgNbPsHi(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define Dpm0PgNbPsHi_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define Dpm0PgNbPsHi_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define DpmXNbPsLo(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define DpmXNbPsLo_MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define DpmXNbPsLo_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define DpmXNbPsHi(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define DpmXNbPsHi_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define DpmXNbPsHi_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SMC_SYSCON_RESET_CNTL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define RST_REG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define CK_DISABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define CKEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SMC_SYSCON_MISC_CNTL 0x80000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SMC_SYSCON_MSG_ARG_0 0x80000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SMC_PC_C 0x80000370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SMC_SCRATCH9 0x80000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RCU_UC_EVENTS 0xC0000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define BOOT_SEQ_DONE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GENERAL_PWRMGT 0xC0200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define SW_SMIO_INDEX_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define SW_SMIO_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define GPU_COUNTER_CLK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CNB_PWRMGT_CNTL 0xC0200004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define GNB_SLOW_MODE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define GNB_SLOW_MODE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define GNB_SLOW_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # define GNB_SLOW (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define FORCE_NB_PS1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define DPM_ENABLED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_PWRMGT_CNTL 0xC0200008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define SCLK_PWRMGT_OFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define RESET_BUSY_CNT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define RESET_SCLK_CNT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define DYNAMIC_PM_EN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define CURRENT_STATE_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define CURRENT_STATE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define CURR_MCLK_INDEX_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define CURR_MCLK_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define CURR_SCLK_INDEX_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define CURR_SCLK_INDEX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CG_SSP 0xC0200044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define SST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define SST_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define SSTU(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define SSTU_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CG_DISPLAY_GAP_CNTL 0xC0200060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define DISP_GAP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define DISP_GAP_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define VBI_TIMER_COUNT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define VBI_TIMER_UNIT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define VBI_TIMER_UNIT_MASK (7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define DISP_GAP_MCHG(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define DISP_GAP_MCHG_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SMU_VOLTAGE_STATUS 0xC0200094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define CURR_PCIE_INDEX_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define CURR_PCIE_INDEX_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CG_ULV_PARAMETER 0xC0200158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CG_FTV_0 0xC02001A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CG_FTV_1 0xC02001AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CG_FTV_2 0xC02001B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CG_FTV_3 0xC02001B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CG_FTV_4 0xC02001B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CG_FTV_5 0xC02001BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CG_FTV_6 0xC02001C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CG_FTV_7 0xC02001C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CG_DISPLAY_GAP_CNTL2 0xC0200230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LCAC_SX0_OVR_SEL 0xC0400D04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LCAC_SX0_OVR_VAL 0xC0400D08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LCAC_MC0_CNTL 0xC0400D30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LCAC_MC0_OVR_SEL 0xC0400D34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LCAC_MC0_OVR_VAL 0xC0400D38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LCAC_MC1_CNTL 0xC0400D3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LCAC_MC1_OVR_SEL 0xC0400D40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LCAC_MC1_OVR_VAL 0xC0400D44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LCAC_MC2_OVR_SEL 0xC0400D4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LCAC_MC2_OVR_VAL 0xC0400D50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LCAC_MC3_OVR_SEL 0xC0400D58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LCAC_MC3_OVR_VAL 0xC0400D5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LCAC_CPL_CNTL 0xC0400D80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LCAC_CPL_OVR_SEL 0xC0400D84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LCAC_CPL_OVR_VAL 0xC0400D88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* dGPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CG_THERMAL_CTRL 0xC0300004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DPM_EVENT_SRC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DPM_EVENT_SRC_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DIG_THERM_DPM(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DIG_THERM_DPM_MASK 0x003FC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DIG_THERM_DPM_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CG_THERMAL_STATUS 0xC0300008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FDO_PWM_DUTY(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FDO_PWM_DUTY_MASK (0xff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FDO_PWM_DUTY_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CG_THERMAL_INT 0xC030000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CI_DIG_THERM_INTH(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CI_DIG_THERM_INTH_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CI_DIG_THERM_INTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CI_DIG_THERM_INTL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CI_DIG_THERM_INTL_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CI_DIG_THERM_INTL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define THERM_INT_MASK_HIGH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define THERM_INT_MASK_LOW (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CG_MULT_THERMAL_CTRL 0xC0300010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEMP_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEMP_SEL_MASK (0xff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEMP_SEL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CG_MULT_THERMAL_STATUS 0xC0300014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ASIC_MAX_TEMP(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ASIC_MAX_TEMP_MASK 0x000001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ASIC_MAX_TEMP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CTF_TEMP(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CTF_TEMP_MASK 0x0003fe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CTF_TEMP_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CG_FDO_CTRL0 0xC0300064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define FDO_STATIC_DUTY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FDO_STATIC_DUTY_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FDO_STATIC_DUTY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CG_FDO_CTRL1 0xC0300068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FMAX_DUTY100(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define FMAX_DUTY100_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define FMAX_DUTY100_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CG_FDO_CTRL2 0xC030006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TMIN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TMIN_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TMIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FDO_PWM_MODE(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define FDO_PWM_MODE_MASK (7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FDO_PWM_MODE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TACH_PWM_RESP_RATE(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TACH_PWM_RESP_RATE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CG_TACH_CTRL 0xC0300070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) # define EDGE_PER_REV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define EDGE_PER_REV_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define EDGE_PER_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) # define TARGET_PERIOD(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define TARGET_PERIOD_MASK 0xfffffff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) # define TARGET_PERIOD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CG_TACH_STATUS 0xC0300074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) # define TACH_PERIOD(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) # define TACH_PERIOD_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define TACH_PERIOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CG_ECLK_CNTL 0xC05000AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define ECLK_DIVIDER_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define ECLK_DIR_CNTL_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CG_ECLK_STATUS 0xC05000B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define ECLK_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CG_SPLL_FUNC_CNTL 0xC0500140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SPLL_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SPLL_PWRON (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SPLL_BYPASS_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SPLL_REF_DIV(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SPLL_REF_DIV_MASK (0x3f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SPLL_PDIV_A(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SPLL_PDIV_A_MASK (0x7f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SPLL_PDIV_A_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CG_SPLL_FUNC_CNTL_2 0xC0500144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SCLK_MUX_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SCLK_MUX_SEL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CG_SPLL_FUNC_CNTL_3 0xC0500148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SPLL_FB_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SPLL_FB_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SPLL_DITHEN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CG_SPLL_FUNC_CNTL_4 0xC050014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SSEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_S(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_S_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_S_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_V(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_V_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MPLL_BYPASSCLK_SEL 0xC050019C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) # define MPLL_CLKOUT_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define MPLL_CLKOUT_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CG_CLKPIN_CNTL 0xC05001A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) # define XTALIN_DIVIDE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define BCLK_AS_XCLK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CG_CLKPIN_CNTL_2 0xC05001A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) # define FORCE_BIF_REFCLK_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) # define MUX_TCLK_TO_XCLK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define THM_CLK_CNTL 0xC05001A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) # define CMON_CLK_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) # define CMON_CLK_SEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) # define TMON_CLK_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) # define TMON_CLK_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MISC_CLK_CTRL 0xC05001AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) # define ZCLK_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) # define ZCLK_SEL_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* KV/KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CG_THERMAL_INT_CTRL 0xC2100028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DIG_THERM_INTH(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DIG_THERM_INTH_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIG_THERM_INTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DIG_THERM_INTL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DIG_THERM_INTL_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DIG_THERM_INTL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define THERM_INTH_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define THERM_INTL_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* PCIE registers idx/data 0x38/0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) # define PLL_RAMP_UP_TIME_0_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) # define PLL_RAMP_UP_TIME_1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PCIE_CNTL2 0x1001001c /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) # define SLV_MEM_LS_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) # define MST_MEM_LS_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) # define REPLAY_MEM_LS_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PCIE_LC_STATUS1 0x1400028 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) # define LC_REVERSE_RCVR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) # define LC_REVERSE_XMIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) # define LC_OPERATING_LINK_WIDTH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) # define LC_DETECTED_LINK_WIDTH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PCIE_P_CNTL 0x1400040 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) # define P_IGNORE_EDB_ERR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PCIE_LC_CNTL 0x100100A0 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) # define LC_L0S_INACTIVITY(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) # define LC_L0S_INACTIVITY_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) # define LC_L0S_INACTIVITY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) # define LC_L1_INACTIVITY(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) # define LC_L1_INACTIVITY_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) # define LC_L1_INACTIVITY_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) # define LC_PMI_TO_L1_DIS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) # define LC_ASPM_TO_L1_DIS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) # define LC_LINK_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) # define LC_LINK_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) # define LC_LINK_WIDTH_X0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) # define LC_LINK_WIDTH_X1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) # define LC_LINK_WIDTH_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) # define LC_LINK_WIDTH_X4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) # define LC_LINK_WIDTH_X8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) # define LC_LINK_WIDTH_X16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) # define LC_LINK_WIDTH_RD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) # define LC_LINK_WIDTH_RD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) # define LC_RECONFIG_NOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) # define LC_RENEGOTIATION_SUPPORT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) # define LC_RENEGOTIATE_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) # define LC_SHORT_RECONFIG_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) # define LC_UPCONFIGURE_SUPPORT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) # define LC_UPCONFIGURE_DIS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) # define LC_DYN_LANES_PWR_STATE_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) # define LC_XMIT_N_FTS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) # define LC_XMIT_N_FTS_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) # define LC_XMIT_N_FTS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) # define LC_N_FTS_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) # define LC_GEN3_EN_STRAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) # define LC_CURRENT_DATA_RATE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) # define LC_GO_TO_RECOVERY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) # define LC_REDO_EQ (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) # define LC_SET_QUIESCE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* direct registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PCIE_INDEX 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PCIE_DATA 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SMC_IND_INDEX_0 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SMC_IND_DATA_0 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SMC_IND_ACCESS_CNTL 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define AUTO_INCREMENT_IND_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SMC_MESSAGE_0 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SMC_MSG_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SMC_RESP_0 0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SMC_RESP_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SMC_MSG_ARG_0 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define VGA_HDP_CONTROL 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define VGA_MEMORY_DISABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DMIF_ADDR_CALC 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SRBM_GFX_CNTL 0xE44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PIPEID(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MEID(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define VMID(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define QUEUEID(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SRBM_STATUS2 0xE4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SDMA_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SDMA1_BUSY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SRBM_STATUS 0xE50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define UVD_RQ_PENDING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define GRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define VMC_BUSY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MCB_BUSY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MCB_NON_DISPLAY_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MCC_BUSY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MCD_BUSY (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SEM_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define IH_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define UVD_BUSY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRBM_SOFT_RESET 0xE60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SOFT_RESET_BIF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SOFT_RESET_R0PLL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SOFT_RESET_DC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SOFT_RESET_SDMA1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SOFT_RESET_GRBM (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SOFT_RESET_HDP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SOFT_RESET_IH (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SOFT_RESET_MC (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SOFT_RESET_ROM (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SOFT_RESET_SEM (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SOFT_RESET_VMC (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SOFT_RESET_SDMA (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SOFT_RESET_TST (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SOFT_RESET_REGBB (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SOFT_RESET_ORB (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SOFT_RESET_VCE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SRBM_READ_ERROR 0xE98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SRBM_INT_CNTL 0xEA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SRBM_INT_ACK 0xEA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define VM_L2_CNTL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ENABLE_L2_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define VM_L2_CNTL2 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define INVALIDATE_ALL_L1_TLBS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define INVALIDATE_L2_CACHE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define INVALIDATE_PTE_AND_PDE_CACHES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define INVALIDATE_ONLY_PTE_CACHES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define INVALIDATE_ONLY_PDE_CACHES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define VM_L2_CNTL3 0x1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define BANK_SELECT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define VM_L2_STATUS 0x140C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define L2_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define VM_CONTEXT0_CNTL 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ENABLE_CONTEXT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define VM_CONTEXT1_CNTL 0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define VM_CONTEXT0_CNTL2 0x1430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define VM_CONTEXT1_CNTL2 0x1434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define VM_INVALIDATE_REQUEST 0x1478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define VM_INVALIDATE_RESPONSE 0x147c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PROTECTIONS_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PROTECTIONS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* bit 0: range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * bit 1: pde0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * bit 2: valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * bit 3: read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * bit 4: write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MEMORY_CLIENT_ID_MASK (0xff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MEMORY_CLIENT_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define MEMORY_CLIENT_RW_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MEMORY_CLIENT_RW_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define FAULT_VMID_MASK (0xf << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define FAULT_VMID_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define VM_L2_CG 0x15c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MC_CG_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MC_LS_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define MC_SHARED_CHMAP 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define NOOFCHAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define NOOFCHAN_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define MC_SHARED_CHREMAP 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define CHUB_CONTROL 0x1864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define BYPASS_VM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define MC_VM_FB_LOCATION 0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define MC_VM_AGP_TOP 0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MC_VM_AGP_BOT 0x202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define MC_VM_AGP_BASE 0x2030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MC_VM_MX_L1_TLB_CNTL 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ENABLE_L1_TLB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define MC_VM_FB_OFFSET 0x2068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define MC_SHARED_BLACKOUT_CNTL 0x20ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MC_HUB_MISC_HUB_CG 0x20b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MC_HUB_MISC_VM_CG 0x20bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MC_HUB_MISC_SIP_CG 0x20c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MC_XPB_CLK_GAT 0x2478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define MC_CITF_MISC_RD_CG 0x2648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define MC_CITF_MISC_WR_CG 0x264c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define MC_CITF_MISC_VM_CG 0x2650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define MC_ARB_RAMCFG 0x2760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define NOOFBANK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define NOOFBANK_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define NOOFRANK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define NOOFRANK_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define NOOFROWS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define NOOFROWS_MASK 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define NOOFCOLS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define NOOFCOLS_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CHANSIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define CHANSIZE_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define NOOFGROUPS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define NOOFGROUPS_MASK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define MC_ARB_DRAM_TIMING 0x2774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define MC_ARB_DRAM_TIMING2 0x2778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MC_ARB_BURST_TIME 0x2808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define STATE0_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define STATE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define STATE1(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define STATE1_MASK (0x1f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define STATE1_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define STATE2(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define STATE2_MASK (0x1f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define STATE2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define STATE3(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define STATE3_MASK (0x1f << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define STATE3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define MC_SEQ_RAS_TIMING 0x28a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MC_SEQ_CAS_TIMING 0x28a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define MC_SEQ_MISC_TIMING 0x28a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define MC_SEQ_MISC_TIMING2 0x28ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define MC_SEQ_PMG_TIMING 0x28b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MC_SEQ_RD_CTL_D0 0x28b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define MC_SEQ_RD_CTL_D1 0x28b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MC_SEQ_WR_CTL_D0 0x28bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MC_SEQ_WR_CTL_D1 0x28c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MC_SEQ_SUP_CNTL 0x28c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define RUN_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define MC_SEQ_SUP_PGM 0x28cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define MC_PMG_AUTO_CMD 0x28d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define TRAIN_DONE_D0 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define TRAIN_DONE_D1 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define MC_IO_PAD_CNTL_D0 0x29d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define MEM_FALL_OUT_CMD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define MC_SEQ_MISC0_VEN_ID_VALUE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MC_SEQ_MISC0_REV_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define MC_SEQ_MISC0_REV_ID_VALUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define MC_SEQ_MISC1 0x2a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MC_SEQ_RESERVE_M 0x2a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define MC_PMG_CMD_EMRS 0x2a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define MC_SEQ_IO_DEBUG_DATA 0x2a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define MC_SEQ_MISC5 0x2a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define MC_SEQ_MISC6 0x2a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define MC_SEQ_MISC7 0x2a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MC_SEQ_RAS_TIMING_LP 0x2a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define MC_SEQ_CAS_TIMING_LP 0x2a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define MC_SEQ_MISC_TIMING_LP 0x2a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define MC_SEQ_MISC_TIMING2_LP 0x2a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define MC_SEQ_WR_CTL_D1_LP 0x2a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define MC_PMG_CMD_MRS 0x2aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MC_SEQ_RD_CTL_D1_LP 0x2b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define MC_PMG_CMD_MRS1 0x2b44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define MC_SEQ_PMG_TIMING_LP 0x2b4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define MC_SEQ_WR_CTL_2 0x2b54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define MC_SEQ_WR_CTL_2_LP 0x2b58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define MC_PMG_CMD_MRS2 0x2b5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define MCLK_PWRMGT_CNTL 0x2ba0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) # define DLL_SPEED(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) # define DLL_SPEED_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) # define DLL_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) # define MC_INT_CNTL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) # define MRDCK0_PDNB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) # define MRDCK1_PDNB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) # define MRDCK0_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) # define MRDCK1_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) # define DLL_READY_READ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define DLL_CNTL 0x2ba4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) # define MRDCK0_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) # define MRDCK1_BYPASS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define MPLL_FUNC_CNTL 0x2bb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define BWCTRL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define BWCTRL_MASK (0xff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MPLL_FUNC_CNTL_1 0x2bb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define VCO_MODE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define VCO_MODE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define CLKFRAC(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define CLKFRAC_MASK (0xfff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define CLKF(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define CLKF_MASK (0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define MPLL_FUNC_CNTL_2 0x2bbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MPLL_AD_FUNC_CNTL 0x2bc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define YCLK_POST_DIV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define YCLK_POST_DIV_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define MPLL_DQ_FUNC_CNTL 0x2bc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define YCLK_SEL(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define YCLK_SEL_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define MPLL_SS1 0x2bcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define CLKV(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define CLKV_MASK (0x3ffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define MPLL_SS2 0x2bd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define CLKS(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define CLKS_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define HDP_HOST_PATH_CNTL 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define CLOCK_GATING_DIS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define HDP_NONSURFACE_BASE 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define HDP_NONSURFACE_INFO 0x2C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define HDP_NONSURFACE_SIZE 0x2C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define HDP_ADDR_CONFIG 0x2F48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define HDP_MISC_CNTL 0x2F4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define HDP_MEM_POWER_LS 0x2F50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define HDP_LS_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define ATC_MISC_CG 0x3350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define GMCON_RENG_EXECUTE 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define RENG_EXECUTE_ON_PWR_UP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define GMCON_MISC 0x350c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define STCTRL_STUTTER_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define GMCON_PGFSM_CONFIG 0x3538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define GMCON_PGFSM_WRITE 0x353c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define GMCON_PGFSM_READ 0x3540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define GMCON_MISC3 0x3544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MC_SEQ_CNTL_3 0x3600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) # define CAC_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MC_SEQ_G5PDX_CTRL 0x3604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MC_SEQ_G5PDX_CTRL_LP 0x3608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MC_SEQ_G5PDX_CMD0 0x360c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MC_SEQ_G5PDX_CMD0_LP 0x3610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MC_SEQ_G5PDX_CMD1 0x3614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define MC_SEQ_G5PDX_CMD1_LP 0x3618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MC_SEQ_PMG_DVS_CTL 0x3628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define MC_SEQ_PMG_DVS_CTL_LP 0x362c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define MC_SEQ_PMG_DVS_CMD 0x3630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define MC_SEQ_PMG_DVS_CMD_LP 0x3634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MC_SEQ_DLL_STBY 0x3638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define MC_SEQ_DLL_STBY_LP 0x363c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define IH_RB_CNTL 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) # define IH_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define IH_RB_BASE 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define IH_RB_RPTR 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define IH_RB_WPTR 0x3e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) # define RB_OVERFLOW (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) # define WPTR_OFFSET_MASK 0x3fffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define IH_RB_WPTR_ADDR_HI 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define IH_RB_WPTR_ADDR_LO 0x3e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define IH_CNTL 0x3e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) # define ENABLE_INTR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) # define IH_MC_SWAP(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) # define IH_MC_SWAP_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) # define IH_MC_SWAP_16BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) # define IH_MC_SWAP_32BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) # define IH_MC_SWAP_64BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) # define RPTR_REARM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) # define MC_WRREQ_CREDIT(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) # define MC_WR_CLEAN_CNT(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) # define MC_VMID(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define BIF_LNCNT_RESET 0x5220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) # define RESET_LNCNT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define CONFIG_MEMSIZE 0x5428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define INTERRUPT_CNTL 0x5468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) # define IH_DUMMY_RD_OVERRIDE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) # define IH_DUMMY_RD_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) # define IH_REQ_NONSNOOP_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) # define GEN_IH_INT_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define INTERRUPT_CNTL2 0x546c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define BIF_FB_EN 0x5490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define FB_READ_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define FB_WRITE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define GPU_HDP_FLUSH_REQ 0x54DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define GPU_HDP_FLUSH_DONE 0x54E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define CP0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define CP1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define CP2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define CP3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define CP4 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define CP5 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define CP6 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define CP7 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define CP8 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define CP9 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define SDMA0 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define SDMA1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define LB_MEMORY_CTRL 0x6b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define LB_MEMORY_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define LB_MEMORY_CONFIG(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) # define LATENCY_WATERMARK_MASK(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define LB_VLINE_STATUS 0x6b24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) # define VLINE_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) # define VLINE_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) # define VLINE_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) # define VLINE_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) # define VLINE_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define LB_VBLANK_STATUS 0x6b2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) # define VBLANK_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) # define VBLANK_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) # define VBLANK_STAT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) # define VBLANK_INTERRUPT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) # define VBLANK_INTERRUPT_TYPE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define LB_INTERRUPT_MASK 0x6b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) # define VBLANK_INTERRUPT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) # define VLINE_INTERRUPT_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) # define VLINE2_INTERRUPT_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DISP_INTERRUPT_STATUS 0x60f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) # define LB_D1_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) # define LB_D1_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) # define DC_HPD1_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) # define DC_HPD1_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) # define DACA_AUTODETECT_INTERRUPT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) # define DACB_AUTODETECT_INTERRUPT (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) # define LB_D2_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) # define LB_D2_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) # define DC_HPD2_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) # define DC_HPD2_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) # define DISP_TIMER_INTERRUPT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) # define LB_D3_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) # define LB_D3_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) # define DC_HPD3_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) # define DC_HPD3_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) # define LB_D4_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) # define LB_D4_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) # define DC_HPD4_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) # define DC_HPD4_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) # define LB_D5_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) # define LB_D5_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) # define DC_HPD5_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) # define DC_HPD5_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) # define LB_D6_VLINE_INTERRUPT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) # define LB_D6_VBLANK_INTERRUPT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) # define DC_HPD6_INTERRUPT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) # define DC_HPD6_RX_INTERRUPT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define GRPH_INT_STATUS 0x6858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) # define GRPH_PFLIP_INT_CLEAR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define GRPH_INT_CONTROL 0x685c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) # define GRPH_PFLIP_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) # define GRPH_PFLIP_INT_TYPE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define DAC_AUTODETECT_INT_CONTROL 0x67c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define DC_HPD1_INT_STATUS 0x601c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define DC_HPD2_INT_STATUS 0x6028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define DC_HPD3_INT_STATUS 0x6034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define DC_HPD4_INT_STATUS 0x6040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define DC_HPD5_INT_STATUS 0x604c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define DC_HPD6_INT_STATUS 0x6058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) # define DC_HPDx_INT_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) # define DC_HPDx_SENSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) # define DC_HPDx_SENSE_DELAYED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) # define DC_HPDx_RX_INT_STATUS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define DC_HPD1_INT_CONTROL 0x6020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define DC_HPD2_INT_CONTROL 0x602c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define DC_HPD3_INT_CONTROL 0x6038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define DC_HPD4_INT_CONTROL 0x6044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define DC_HPD5_INT_CONTROL 0x6050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define DC_HPD6_INT_CONTROL 0x605c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) # define DC_HPDx_INT_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) # define DC_HPDx_INT_POLARITY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) # define DC_HPDx_INT_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) # define DC_HPDx_RX_INT_ACK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) # define DC_HPDx_RX_INT_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define DC_HPD1_CONTROL 0x6024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define DC_HPD2_CONTROL 0x6030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define DC_HPD3_CONTROL 0x603c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define DC_HPD4_CONTROL 0x6048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define DC_HPD5_CONTROL 0x6054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define DC_HPD6_CONTROL 0x6060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) # define DC_HPDx_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) # define STUTTER_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* DCE8 FMT blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define FMT_DYNAMIC_EXP_CNTL 0x6fb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) # define FMT_DYNAMIC_EXP_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) # define FMT_DYNAMIC_EXP_MODE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define FMT_CONTROL 0x6fb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) # define FMT_PIXEL_ENCODING (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define FMT_BIT_DEPTH_CONTROL 0x6fc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) # define FMT_TRUNCATE_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) # define FMT_TRUNCATE_MODE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) # define FMT_SPATIAL_DITHER_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) # define FMT_RGB_RANDOM_ENABLE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) # define FMT_TEMPORAL_DITHER_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) # define FMT_TEMPORAL_LEVEL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) # define FMT_25FRC_SEL(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) # define FMT_50FRC_SEL(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) # define FMT_75FRC_SEL(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define FMT_CLAMP_CONTROL 0x6fe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) # define FMT_CLAMP_DATA_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) # define FMT_CLAMP_6BPC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) # define FMT_CLAMP_8BPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) # define FMT_CLAMP_10BPC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define GRBM_CNTL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define GRBM_READ_TIMEOUT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define GRBM_STATUS2 0x8008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define ME1PIPE0_RQ_PENDING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define ME1PIPE1_RQ_PENDING (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define ME1PIPE2_RQ_PENDING (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define ME1PIPE3_RQ_PENDING (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define ME2PIPE0_RQ_PENDING (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define ME2PIPE1_RQ_PENDING (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define ME2PIPE2_RQ_PENDING (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define ME2PIPE3_RQ_PENDING (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define RLC_RQ_PENDING (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define RLC_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define TC_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define CPF_BUSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define CPC_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define CPG_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define GRBM_STATUS 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define SRBM_RQ_PENDING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define GDS_DMA_RQ_PENDING (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define DB_CLEAN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define CB_CLEAN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define TA_BUSY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define GDS_BUSY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define WD_BUSY_NO_DMA (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define VGT_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define IA_BUSY_NO_DMA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define IA_BUSY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define SX_BUSY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define WD_BUSY (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define SPI_BUSY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define BCI_BUSY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define SC_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define PA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define DB_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define CP_COHERENCY_BUSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define CP_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define CB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define GUI_ACTIVE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define GRBM_STATUS_SE0 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define GRBM_STATUS_SE1 0x8018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define GRBM_STATUS_SE2 0x8038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define GRBM_STATUS_SE3 0x803C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define SE_DB_CLEAN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SE_CB_CLEAN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define SE_BCI_BUSY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define SE_VGT_BUSY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define SE_PA_BUSY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define SE_TA_BUSY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define SE_SX_BUSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define SE_SPI_BUSY (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define SE_SC_BUSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define SE_DB_BUSY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define SE_CB_BUSY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define GRBM_SOFT_RESET 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define SOFT_RESET_RLC (1 << 2) /* RLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define SOFT_RESET_GFX (1 << 16) /* GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define GRBM_INT_CNTL 0x8060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) # define RDERR_INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) # define GUI_IDLE_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define CP_CPC_STATUS 0x8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define CP_CPC_BUSY_STAT 0x8214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define CP_CPC_STALLED_STAT1 0x8218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define CP_CPF_STATUS 0x821c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define CP_CPF_BUSY_STAT 0x8220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define CP_CPF_STALLED_STAT1 0x8224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define CP_MEC_CNTL 0x8234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define MEC_ME2_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define MEC_ME1_HALT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define CP_MEC_CNTL 0x8234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define MEC_ME2_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define MEC_ME1_HALT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define CP_STALLED_STAT3 0x8670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define CP_STALLED_STAT1 0x8674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define CP_STALLED_STAT2 0x8678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define CP_STAT 0x8680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define CP_ME_CNTL 0x86D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define CP_CE_HALT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define CP_PFP_HALT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define CP_ME_HALT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define CP_RB0_RPTR 0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define CP_RB_WPTR_DELAY 0x8704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define CP_RB_WPTR_POLL_CNTL 0x8708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define IDLE_POLL_COUNT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define IDLE_POLL_COUNT_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define CP_MEQ_THRESHOLDS 0x8764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define MEQ1_START(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define MEQ2_START(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define VGT_VTX_VECT_EJECT_REG 0x88B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define VGT_CACHE_INVALIDATION 0x88C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define CACHE_INVALIDATION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define VC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define TC_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define VC_AND_TC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define AUTO_INVLD_EN(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define NO_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define ES_AUTO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define GS_AUTO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define ES_AND_GS_AUTO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define VGT_GS_VERTEX_REUSE 0x88D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define INACTIVE_CUS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define INACTIVE_CUS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define PA_CL_ENHANCE 0x8A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define CLIP_VTX_REORDER_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define NUM_CLIP_SEQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define PA_SC_FIFO_SIZE 0x8BCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define PA_SC_ENHANCE 0x8BF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define DISABLE_PA_SC_GUIDANCE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SQ_CONFIG 0x8C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SH_MEM_BASES 0x8C28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* if PTR32, these are the bases for scratch and lds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SHARED_BASE(x) ((x) << 16) /* LDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SH_MEM_APE1_BASE 0x8C2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* if PTR32, this is the base location of GPUVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SH_MEM_APE1_LIMIT 0x8C30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* if PTR32, this is the upper limit of GPUVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define SH_MEM_CONFIG 0x8C34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define PTR32 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define ALIGNMENT_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SH_MEM_ALIGNMENT_MODE_DWORD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SH_MEM_ALIGNMENT_MODE_STRICT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define DEFAULT_MTYPE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define APE1_MTYPE(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define MTYPE_CACHED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define MTYPE_NONCACHED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SX_DEBUG_1 0x9060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SPI_CONFIG_CNTL 0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SPI_CONFIG_CNTL_1 0x913C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define VTX_DONE_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define TA_CNTL_AUX 0x9508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define DB_DEBUG 0x9830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define DB_DEBUG2 0x9834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define DB_DEBUG3 0x9838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define CC_RB_BACKEND_DISABLE 0x98F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define BACKEND_DISABLE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define GB_ADDR_CONFIG 0x98F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define NUM_PIPES(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define NUM_PIPES_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define NUM_PIPES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define PIPE_INTERLEAVE_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define NUM_SHADER_ENGINES(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define NUM_SHADER_ENGINES_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define NUM_SHADER_ENGINES_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define ROW_SIZE(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define ROW_SIZE_MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define ROW_SIZE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define GB_TILE_MODE0 0x9910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) # define ARRAY_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) # define ARRAY_LINEAR_GENERAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) # define ARRAY_LINEAR_ALIGNED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) # define ARRAY_1D_TILED_THIN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) # define ARRAY_2D_TILED_THIN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) # define ARRAY_PRT_TILED_THIN1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) # define ARRAY_PRT_2D_TILED_THIN1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) # define PIPE_CONFIG(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) # define ADDR_SURF_P2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) # define ADDR_SURF_P4_8x16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) # define ADDR_SURF_P4_16x16 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) # define ADDR_SURF_P4_16x32 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) # define ADDR_SURF_P4_32x32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) # define ADDR_SURF_P8_16x16_8x16 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) # define ADDR_SURF_P8_16x32_8x16 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) # define ADDR_SURF_P8_32x32_8x16 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) # define ADDR_SURF_P8_16x32_16x16 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) # define ADDR_SURF_P8_32x32_16x16 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) # define ADDR_SURF_P8_32x32_16x32 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) # define ADDR_SURF_P8_32x64_32x32 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) # define ADDR_SURF_P16_32x32_8x16 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) # define ADDR_SURF_P16_32x32_16x16 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) # define TILE_SPLIT(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) # define ADDR_SURF_TILE_SPLIT_64B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) # define ADDR_SURF_TILE_SPLIT_128B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) # define ADDR_SURF_TILE_SPLIT_256B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) # define ADDR_SURF_TILE_SPLIT_512B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) # define ADDR_SURF_TILE_SPLIT_1KB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) # define ADDR_SURF_TILE_SPLIT_2KB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) # define ADDR_SURF_TILE_SPLIT_4KB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) # define ADDR_SURF_DISPLAY_MICRO_TILING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) # define ADDR_SURF_THIN_MICRO_TILING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) # define ADDR_SURF_DEPTH_MICRO_TILING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) # define ADDR_SURF_ROTATED_MICRO_TILING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) # define SAMPLE_SPLIT(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) # define ADDR_SURF_SAMPLE_SPLIT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) # define ADDR_SURF_SAMPLE_SPLIT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) # define ADDR_SURF_SAMPLE_SPLIT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) # define ADDR_SURF_SAMPLE_SPLIT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define GB_MACROTILE_MODE0 0x9990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) # define BANK_WIDTH(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) # define ADDR_SURF_BANK_WIDTH_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) # define ADDR_SURF_BANK_WIDTH_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) # define ADDR_SURF_BANK_WIDTH_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) # define ADDR_SURF_BANK_WIDTH_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) # define BANK_HEIGHT(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) # define ADDR_SURF_BANK_HEIGHT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) # define ADDR_SURF_BANK_HEIGHT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) # define ADDR_SURF_BANK_HEIGHT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) # define ADDR_SURF_BANK_HEIGHT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) # define MACRO_TILE_ASPECT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) # define ADDR_SURF_MACRO_ASPECT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) # define ADDR_SURF_MACRO_ASPECT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) # define ADDR_SURF_MACRO_ASPECT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) # define ADDR_SURF_MACRO_ASPECT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) # define NUM_BANKS(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) # define ADDR_SURF_2_BANK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) # define ADDR_SURF_4_BANK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) # define ADDR_SURF_8_BANK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) # define ADDR_SURF_16_BANK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define CB_HW_CONTROL 0x9A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define BACKEND_DISABLE_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define BACKEND_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define TCP_CHAN_STEER_LO 0xac0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define TCP_CHAN_STEER_HI 0xac10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define TC_CFG_L1_LOAD_POLICY0 0xAC68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define TC_CFG_L1_LOAD_POLICY1 0xAC6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define TC_CFG_L1_STORE_POLICY 0xAC70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define TC_CFG_L2_LOAD_POLICY0 0xAC74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define TC_CFG_L2_LOAD_POLICY1 0xAC78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define TC_CFG_L2_STORE_POLICY0 0xAC7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define TC_CFG_L2_STORE_POLICY1 0xAC80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define TC_CFG_L2_ATOMIC_POLICY 0xAC84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define TC_CFG_L1_VOLATILE 0xAC88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define TC_CFG_L2_VOLATILE 0xAC8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define CP_RB0_BASE 0xC100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define CP_RB0_CNTL 0xC104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define RB_BUFSZ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define RB_BLKSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define BUF_SWAP_32BIT (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define RB_NO_UPDATE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define RB_RPTR_WR_ENA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define CP_RB0_RPTR_ADDR 0xC10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define RB_RPTR_SWAP_32BIT (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define CP_RB0_RPTR_ADDR_HI 0xC110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define CP_RB0_WPTR 0xC114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define CP_DEVICE_ID 0xC12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define CP_ENDIAN_SWAP 0xC140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define CP_RB_VMID 0xC144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define CP_PFP_UCODE_ADDR 0xC150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define CP_PFP_UCODE_DATA 0xC154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define CP_ME_RAM_RADDR 0xC158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define CP_ME_RAM_WADDR 0xC15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define CP_ME_RAM_DATA 0xC160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define CP_CE_UCODE_ADDR 0xC168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define CP_CE_UCODE_DATA 0xC16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define CP_MEC_ME1_UCODE_ADDR 0xC170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define CP_MEC_ME1_UCODE_DATA 0xC174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define CP_MEC_ME2_UCODE_ADDR 0xC178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define CP_MEC_ME2_UCODE_DATA 0xC17C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define CP_INT_CNTL_RING0 0xC1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) # define CNTX_BUSY_INT_ENABLE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) # define CNTX_EMPTY_INT_ENABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) # define PRIV_INSTR_INT_ENABLE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) # define PRIV_REG_INT_ENABLE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) # define OPCODE_ERROR_INT_ENABLE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) # define TIME_STAMP_INT_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) # define CP_RINGID2_INT_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) # define CP_RINGID1_INT_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) # define CP_RINGID0_INT_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define CP_INT_STATUS_RING0 0xC1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) # define PRIV_INSTR_INT_STAT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) # define PRIV_REG_INT_STAT (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) # define TIME_STAMP_INT_STAT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) # define CP_RINGID2_INT_STAT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) # define CP_RINGID1_INT_STAT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) # define CP_RINGID0_INT_STAT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define CP_MEM_SLP_CNTL 0xC1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) # define CP_MEM_LS_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define CP_CPF_DEBUG 0xC200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define CP_PQ_WPTR_POLL_CNTL 0xC20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define WPTR_POLL_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define CP_ME1_PIPE0_INT_CNTL 0xC214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define CP_ME1_PIPE1_INT_CNTL 0xC218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define CP_ME1_PIPE2_INT_CNTL 0xC21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define CP_ME1_PIPE3_INT_CNTL 0xC220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define CP_ME2_PIPE0_INT_CNTL 0xC224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define CP_ME2_PIPE1_INT_CNTL 0xC228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define CP_ME2_PIPE2_INT_CNTL 0xC22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define CP_ME2_PIPE3_INT_CNTL 0xC230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) # define PRIV_REG_INT_ENABLE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) # define TIME_STAMP_INT_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) # define GENERIC2_INT_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) # define GENERIC1_INT_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) # define GENERIC0_INT_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define CP_ME1_PIPE0_INT_STATUS 0xC214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define CP_ME1_PIPE1_INT_STATUS 0xC218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define CP_ME1_PIPE2_INT_STATUS 0xC21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define CP_ME1_PIPE3_INT_STATUS 0xC220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define CP_ME2_PIPE0_INT_STATUS 0xC224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define CP_ME2_PIPE1_INT_STATUS 0xC228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define CP_ME2_PIPE2_INT_STATUS 0xC22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define CP_ME2_PIPE3_INT_STATUS 0xC230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) # define PRIV_REG_INT_STATUS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) # define TIME_STAMP_INT_STATUS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) # define GENERIC2_INT_STATUS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) # define GENERIC1_INT_STATUS (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) # define GENERIC0_INT_STATUS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define CP_MAX_CONTEXT 0xC2B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define CP_RB0_BASE_HI 0xC2C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define RLC_CNTL 0xC300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) # define RLC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define RLC_MC_CNTL 0xC30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define RLC_MEM_SLP_CNTL 0xC318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) # define RLC_MEM_LS_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define RLC_LB_CNTR_MAX 0xC348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define RLC_LB_CNTL 0xC364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) # define LOAD_BALANCE_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define RLC_LB_CNTR_INIT 0xC36C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define RLC_SAVE_AND_RESTORE_BASE 0xC374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define RLC_PG_DELAY_2 0xC37C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define RLC_GPM_UCODE_ADDR 0xC388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define RLC_GPM_UCODE_DATA 0xC38C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define RLC_GPU_CLOCK_COUNT_LSB 0xC390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define RLC_GPU_CLOCK_COUNT_MSB 0xC394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define RLC_UCODE_CNTL 0xC39C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define RLC_GPM_STAT 0xC400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) # define RLC_GPM_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) # define GFX_POWER_STATUS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) # define GFX_CLOCK_STATUS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define RLC_PG_CNTL 0xC40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) # define GFX_PG_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) # define GFX_PG_SRC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) # define DYN_PER_CU_PG_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) # define STATIC_PER_CU_PG_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) # define DISABLE_GDS_PG (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) # define DISABLE_CP_PG (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define RLC_CGTT_MGCG_OVERRIDE 0xC420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define RLC_CGCG_CGLS_CTRL 0xC424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) # define CGCG_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) # define CGLS_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define RLC_PG_DELAY 0xC434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define RLC_LB_INIT_CU_MASK 0xC43C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define RLC_LB_PARAMS 0xC444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define RLC_PG_AO_CU_MASK 0xC44C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define RLC_MAX_PG_CU 0xC450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) # define MAX_PU_CU(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) # define MAX_PU_CU_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define RLC_AUTO_PG_CTRL 0xC454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) # define AUTO_PG_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) # define GRBM_REG_SGIT(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) # define GRBM_REG_SGIT_MASK (0xffff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define RLC_SERDES_WR_CTRL 0xC47C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define BPM_ADDR(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define BPM_ADDR_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define CGLS_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define CGCG_OVERRIDE_0 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define MGCG_OVERRIDE_0 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define MGCG_OVERRIDE_1 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define RLC_SERDES_CU_MASTER_BUSY 0xC484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) # define SE_MASTER_BUSY_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) # define GC_MASTER_BUSY (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) # define TC0_MASTER_BUSY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) # define TC1_MASTER_BUSY (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define RLC_GPM_SCRATCH_ADDR 0xC4B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define RLC_GPM_SCRATCH_DATA 0xC4B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define RLC_GPR_REG2 0xC4E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define REQ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define MESSAGE(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define MESSAGE_MASK 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define MSG_ENTER_RLC_SAFE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define MSG_EXIT_RLC_SAFE_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define CP_HPD_EOP_BASE_ADDR 0xC904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define CP_HPD_EOP_BASE_ADDR_HI 0xC908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define CP_HPD_EOP_VMID 0xC90C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define CP_HPD_EOP_CONTROL 0xC910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define EOP_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define EOP_SIZE_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define CP_MQD_BASE_ADDR 0xC914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define CP_MQD_BASE_ADDR_HI 0xC918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define CP_HQD_ACTIVE 0xC91C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define CP_HQD_VMID 0xC920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define CP_HQD_PERSISTENT_STATE 0xC924u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define CP_HQD_PIPE_PRIORITY 0xC928u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define CP_HQD_QUEUE_PRIORITY 0xC92Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define CP_HQD_QUANTUM 0xC930u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define QUANTUM_EN 1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define QUANTUM_SCALE_1MS (1U << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define QUANTUM_DURATION(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define CP_HQD_PQ_BASE 0xC934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define CP_HQD_PQ_BASE_HI 0xC938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define CP_HQD_PQ_RPTR 0xC93C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define DOORBELL_OFFSET(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define DOORBELL_OFFSET_MASK (0x1fffff << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define DOORBELL_SOURCE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define DOORBELL_SCHD_HIT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define DOORBELL_EN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define DOORBELL_HIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define CP_HQD_PQ_WPTR 0xC954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define CP_HQD_PQ_CONTROL 0xC958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define QUEUE_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define QUEUE_SIZE_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define RPTR_BLOCK_SIZE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define PQ_VOLATILE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define NO_UPDATE_RPTR (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define UNORD_DISPATCH (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define ROQ_PQ_IB_FLIP (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define PRIV_STATE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define KMD_QUEUE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define CP_HQD_IB_BASE_ADDR 0xC95Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define CP_HQD_IB_BASE_ADDR_HI 0xC960u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define CP_HQD_IB_RPTR 0xC964u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define CP_HQD_IB_CONTROL 0xC968u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define IB_ATC_EN (1U << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define CP_HQD_DEQUEUE_REQUEST 0xC974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define DEQUEUE_REQUEST_DRAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define DEQUEUE_REQUEST_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define CP_MQD_CONTROL 0xC99C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define MQD_VMID(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define MQD_VMID_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define CP_HQD_SEMA_CMD 0xC97Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define CP_HQD_MSG_TYPE 0xC980u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define CP_HQD_HQ_SCHEDULER0 0xC994u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define CP_HQD_HQ_SCHEDULER1 0xC998u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define SH_STATIC_MEM_CONFIG 0x9604u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define DB_RENDER_CONTROL 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define PA_SC_RASTER_CONFIG 0x28350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) # define RASTER_CONFIG_RB_MAP_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) # define RASTER_CONFIG_RB_MAP_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) # define RASTER_CONFIG_RB_MAP_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) # define RASTER_CONFIG_RB_MAP_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define PKR_MAP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define VGT_EVENT_INITIATOR 0x28a90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) # define CACHE_FLUSH_TS (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) # define CACHE_FLUSH (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) # define CS_PARTIAL_FLUSH (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) # define VGT_STREAMOUT_RESET (10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) # define END_OF_PIPE_INCR_DE (11 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) # define END_OF_PIPE_IB_END (12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) # define RST_PIX_CNT (13 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) # define VS_PARTIAL_FLUSH (15 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) # define PS_PARTIAL_FLUSH (16 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) # define ZPASS_DONE (21 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) # define PERFCOUNTER_START (23 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) # define PERFCOUNTER_STOP (24 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) # define PIPELINESTAT_START (25 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) # define PIPELINESTAT_STOP (26 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) # define PERFCOUNTER_SAMPLE (27 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) # define SAMPLE_PIPELINESTAT (30 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) # define SO_VGT_STREAMOUT_FLUSH (31 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) # define SAMPLE_STREAMOUTSTATS (32 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) # define RESET_VTX_CNT (33 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) # define VGT_FLUSH (36 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) # define BOTTOM_OF_PIPE_TS (40 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) # define DB_CACHE_FLUSH_AND_INV (42 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) # define FLUSH_AND_INV_DB_META (44 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) # define FLUSH_AND_INV_CB_META (46 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) # define CS_DONE (47 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) # define PS_DONE (48 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) # define THREAD_TRACE_START (51 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) # define THREAD_TRACE_STOP (52 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) # define THREAD_TRACE_FLUSH (54 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) # define THREAD_TRACE_FINISH (55 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) # define PIXEL_PIPE_STAT_CONTROL (56 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) # define PIXEL_PIPE_STAT_DUMP (57 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) # define PIXEL_PIPE_STAT_RESET (58 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define SCRATCH_REG0 0x30100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define SCRATCH_REG1 0x30104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define SCRATCH_REG2 0x30108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define SCRATCH_REG3 0x3010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define SCRATCH_REG4 0x30110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define SCRATCH_REG5 0x30114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define SCRATCH_REG6 0x30118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define SCRATCH_REG7 0x3011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define SCRATCH_UMSK 0x30140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define SCRATCH_ADDR 0x30144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define CP_SEM_WAIT_TIMER 0x301BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define GRBM_GFX_INDEX 0x30800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define INSTANCE_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define SH_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define SE_INDEX(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define SH_BROADCAST_WRITES (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define INSTANCE_BROADCAST_WRITES (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define SE_BROADCAST_WRITES (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define VGT_ESGS_RING_SIZE 0x30900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define VGT_GSVS_RING_SIZE 0x30904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define VGT_PRIMITIVE_TYPE 0x30908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define VGT_INDEX_TYPE 0x3090C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define VGT_NUM_INDICES 0x30930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define VGT_NUM_INSTANCES 0x30934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define VGT_TF_RING_SIZE 0x30938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define VGT_HS_OFFCHIP_PARAM 0x3093C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define VGT_TF_MEMORY_BASE 0x30940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define PA_SU_LINE_STIPPLE_VALUE 0x30a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define PA_SC_LINE_STIPPLE_STATE 0x30a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define SQC_CACHES 0x30d20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define CP_PERFMON_CNTL 0x36020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define CGTS_SM_CTRL_REG 0x3c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define SM_MODE(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define SM_MODE_MASK (0x7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define SM_MODE_ENABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define CGTS_OVERRIDE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define CGTS_LS_OVERRIDE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define ON_MONITOR_ADD_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define ON_MONITOR_ADD(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define ON_MONITOR_ADD_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define CGTS_TCC_DISABLE 0x3c00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define CGTS_USER_TCC_DISABLE 0x3c010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define TCC_DISABLE_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define TCC_DISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define CB_CGTT_SCLK_CTRL 0x3c2a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * PM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define PACKET_TYPE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define PACKET_TYPE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define PACKET_TYPE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define PACKET_TYPE3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (((reg) >> 2) & 0xFFFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define CP_PACKET2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define PACKET2_PAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define PACKET2_PAD_MASK (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) (((op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ((n) & 0x3FFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* Packet 3 types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define PACKET3_NOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define PACKET3_SET_BASE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define PACKET3_BASE_INDEX(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define CE_PARTITION_BASE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define PACKET3_CLEAR_STATE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define PACKET3_INDEX_BUFFER_SIZE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define PACKET3_DISPATCH_DIRECT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define PACKET3_DISPATCH_INDIRECT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define PACKET3_ATOMIC_GDS 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define PACKET3_ATOMIC_MEM 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define PACKET3_OCCLUSION_QUERY 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define PACKET3_SET_PREDICATION 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define PACKET3_REG_RMW 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define PACKET3_COND_EXEC 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define PACKET3_PRED_EXEC 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define PACKET3_DRAW_INDIRECT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define PACKET3_DRAW_INDEX_INDIRECT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define PACKET3_INDEX_BASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define PACKET3_DRAW_INDEX_2 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define PACKET3_CONTEXT_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define PACKET3_INDEX_TYPE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define PACKET3_DRAW_INDEX_AUTO 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define PACKET3_NUM_INSTANCES 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define PACKET3_INDIRECT_BUFFER_CONST 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define PACKET3_DRAW_PREAMBLE 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define PACKET3_WRITE_DATA 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define WRITE_DATA_DST_SEL(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* 0 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) * 1 - memory (sync - via GRBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * 2 - gl2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * 3 - gds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * 4 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * 5 - memory (async - direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define WR_ONE_ADDR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define WR_CONFIRM (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* 0 - LRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * 1 - Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* 0 - me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * 1 - pfp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * 2 - ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define PACKET3_MEM_SEMAPHORE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define PACKET3_COPY_DW 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define PACKET3_WAIT_REG_MEM 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* 0 - always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * 1 - <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * 2 - <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * 3 - ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * 4 - !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * 5 - >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * 6 - >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* 0 - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * 1 - mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* 0 - wait_reg_mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * 1 - wr_wait_wr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* 0 - me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * 1 - pfp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define PACKET3_INDIRECT_BUFFER 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define INDIRECT_BUFFER_VALID (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* 0 - LRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * 1 - Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * 2 - Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define PACKET3_COPY_DATA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define PACKET3_PFP_SYNC_ME 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define PACKET3_SURFACE_SYNC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) # define PACKET3_DEST_BASE_0_ENA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) # define PACKET3_DEST_BASE_1_ENA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) # define PACKET3_DEST_BASE_2_ENA (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) # define PACKET3_DEST_BASE_3_ENA (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) # define PACKET3_TCL1_ACTION_ENA (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) # define PACKET3_CB_ACTION_ENA (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) # define PACKET3_DB_ACTION_ENA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define PACKET3_COND_WRITE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define PACKET3_EVENT_WRITE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define EVENT_TYPE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define EVENT_INDEX(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* 0 - any non-TS event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * 2 - SAMPLE_PIPELINESTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * 3 - SAMPLE_STREAMOUTSTAT*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * 4 - *S_PARTIAL_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * 5 - EOP events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * 6 - EOS events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define PACKET3_EVENT_WRITE_EOP 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define EOP_TCL1_ACTION_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define EOP_TCL2_VOLATILE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define EOP_CACHE_POLICY(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* 0 - LRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * 1 - Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * 2 - Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define DATA_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* 0 - discard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * 1 - send low 32bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * 2 - send 64bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * 3 - send 64bit GPU counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * 4 - send 64bit sys counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define INT_SEL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * 1 - interrupt only (DATA_SEL = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * 2 - interrupt when data write is confirmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define DST_SEL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* 0 - MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * 1 - TC/L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define PACKET3_EVENT_WRITE_EOS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define PACKET3_RELEASE_MEM 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define PACKET3_PREAMBLE_CNTL 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define PACKET3_DMA_DATA 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* 1. header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * 2. CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * 3. SRC_ADDR_LO or DATA [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * 4. SRC_ADDR_HI [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * 5. DST_ADDR_LO [31:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * 6. DST_ADDR_HI [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* 0 - ME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * 1 - PFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* 0 - LRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * 1 - Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * 2 - Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* 0 - DST_ADDR using DAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) * 1 - GDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * 3 - DST_ADDR using L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /* 0 - LRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * 1 - Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * 2 - Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* 0 - SRC_ADDR using SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * 1 - GDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * 2 - DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * 3 - SRC_ADDR using L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* 0 - none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * 1 - 8 in 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * 2 - 8 in 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * 3 - 8 in 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* 0 - memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * 1 - register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define PACKET3_AQUIRE_MEM 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define PACKET3_REWIND 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define PACKET3_LOAD_UCONFIG_REG 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define PACKET3_LOAD_SH_REG 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define PACKET3_LOAD_CONFIG_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define PACKET3_LOAD_CONTEXT_REG 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define PACKET3_SET_CONFIG_REG 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define PACKET3_SET_CONFIG_REG_START 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define PACKET3_SET_CONFIG_REG_END 0x0000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define PACKET3_SET_CONTEXT_REG 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define PACKET3_SET_CONTEXT_REG_START 0x00028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define PACKET3_SET_CONTEXT_REG_END 0x00029000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define PACKET3_SET_SH_REG 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define PACKET3_SET_SH_REG_START 0x0000b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define PACKET3_SET_SH_REG_END 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define PACKET3_SET_SH_REG_OFFSET 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define PACKET3_SET_QUEUE_REG 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define PACKET3_SET_UCONFIG_REG 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define PACKET3_SET_UCONFIG_REG_START 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define PACKET3_SET_UCONFIG_REG_END 0x00031000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define PACKET3_SCRATCH_RAM_WRITE 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define PACKET3_SCRATCH_RAM_READ 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define PACKET3_LOAD_CONST_RAM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define PACKET3_WRITE_CONST_RAM 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define PACKET3_DUMP_CONST_RAM 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define PACKET3_INCREMENT_CE_COUNTER 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define PACKET3_INCREMENT_DE_COUNTER 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define PACKET3_WAIT_ON_CE_COUNTER 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define PACKET3_SWITCH_BUFFER 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* SDMA - first instance at 0xd000, second at 0xd800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define SDMA0_UCODE_ADDR 0xD000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define SDMA0_UCODE_DATA 0xD004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define SDMA0_POWER_CNTL 0xD008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define SDMA0_CLK_CTRL 0xD00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define SDMA0_CNTL 0xD010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) # define TRAP_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) # define SEM_WAIT_INT_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) # define DATA_SWAP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) # define FENCE_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) # define AUTO_CTXSW_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) # define CTXEMPTY_INT_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define SDMA0_TILING_CONFIG 0xD018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define SDMA0_STATUS_REG 0xd034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) # define SDMA_IDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define SDMA0_ME_CNTL 0xD048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) # define SDMA_HALT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define SDMA0_GFX_RB_CNTL 0xD200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) # define SDMA_RB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define SDMA0_GFX_RB_BASE 0xD204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define SDMA0_GFX_RB_BASE_HI 0xD208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define SDMA0_GFX_RB_RPTR 0xD20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define SDMA0_GFX_RB_WPTR 0xD210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define SDMA0_GFX_IB_CNTL 0xD228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) # define SDMA_IB_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) # define SDMA_IB_SWAP_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) # define SDMA_SWITCH_INSIDE_IB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) # define SDMA_CMD_VMID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define SDMA0_GFX_APE1_CNTL 0xD2A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) (((sub_op) & 0xFF) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) (((op) & 0xFF) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* sDMA opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define SDMA_OPCODE_NOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #define SDMA_OPCODE_COPY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) # define SDMA_COPY_SUB_OPCODE_LINEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) # define SDMA_COPY_SUB_OPCODE_TILED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) # define SDMA_COPY_SUB_OPCODE_SOA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define SDMA_OPCODE_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) # define SDMA_WRITE_SUB_OPCODE_TILED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define SDMA_OPCODE_INDIRECT_BUFFER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #define SDMA_OPCODE_FENCE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #define SDMA_OPCODE_TRAP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define SDMA_OPCODE_SEMAPHORE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* 0 - increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * 1 - write 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /* 0 - wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * 1 - signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define SDMA_OPCODE_POLL_REG_MEM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) /* 0 - wait_reg_mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * 1 - wr_wait_wr_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* 0 - always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * 1 - <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) * 2 - <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) * 3 - ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * 4 - !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * 5 - >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) * 6 - >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* 0 = register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * 1 = memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define SDMA_OPCODE_COND_EXEC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define SDMA_OPCODE_CONSTANT_FILL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) /* 0 = byte fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) * 2 = DW fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define SDMA_OPCODE_GENERATE_PTE_PDE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define SDMA_OPCODE_TIMESTAMP 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define SDMA_OPCODE_SRBM_WRITE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* byte mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* UVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define UVD_UDEC_ADDR_CONFIG 0xef4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define UVD_NO_OP 0xeffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define UVD_LMI_EXT40_ADDR 0xf498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define UVD_GP_SCRATCH4 0xf4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define UVD_LMI_ADDR_EXT 0xf594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define UVD_VCPU_CACHE_OFFSET0 0xf608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define UVD_VCPU_CACHE_SIZE0 0xf60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define UVD_VCPU_CACHE_OFFSET1 0xf610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define UVD_VCPU_CACHE_SIZE1 0xf614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define UVD_VCPU_CACHE_OFFSET2 0xf618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define UVD_VCPU_CACHE_SIZE2 0xf61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define UVD_RBC_RB_RPTR 0xf690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define UVD_RBC_RB_WPTR 0xf694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define UVD_CGC_CTRL 0xF4B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) # define DCM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) # define CG_DT(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) # define CG_DT_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) # define CLK_OD(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) # define CLK_OD_MASK (0x1f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define UVD_STATUS 0xf6bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /* UVD clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define CG_DCLK_CNTL 0xC050009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) # define DCLK_DIVIDER_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) # define DCLK_DIR_CNTL_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define CG_DCLK_STATUS 0xC05000A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) # define DCLK_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define CG_VCLK_CNTL 0xC05000A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define CG_VCLK_STATUS 0xC05000A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* UVD CTX indirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define UVD_CGC_MEM_CTRL 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* VCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define VCE_VCPU_CACHE_OFFSET0 0x20024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define VCE_VCPU_CACHE_SIZE0 0x20028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define VCE_VCPU_CACHE_OFFSET1 0x2002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define VCE_VCPU_CACHE_SIZE1 0x20030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define VCE_VCPU_CACHE_OFFSET2 0x20034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define VCE_VCPU_CACHE_SIZE2 0x20038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define VCE_RB_RPTR2 0x20178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define VCE_RB_WPTR2 0x2017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define VCE_RB_RPTR 0x2018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define VCE_RB_WPTR 0x20190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define VCE_CLOCK_GATING_A 0x202f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) # define CGC_UENC_WAIT_AWAKE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define VCE_CLOCK_GATING_B 0x202fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define VCE_CGTT_CLK_OVERRIDE 0x207a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define VCE_UENC_CLOCK_GATING 0x207bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) # define CLOCK_ON_DELAY_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) # define CLOCK_ON_DELAY(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) # define CLOCK_OFF_DELAY_MASK (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) # define CLOCK_OFF_DELAY(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define VCE_UENC_REG_CLOCK_GATING 0x207c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define VCE_SYS_INT_EN 0x21300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define VCE_LMI_CTRL2 0x21474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define VCE_LMI_CTRL 0x21498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define VCE_LMI_VM_CTRL 0x214a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define VCE_LMI_SWAP_CNTL 0x214b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define VCE_LMI_SWAP_CNTL1 0x214b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define VCE_LMI_CACHE_CTRL 0x214f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define VCE_CMD_NO_OP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define VCE_CMD_END 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define VCE_CMD_IB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define VCE_CMD_FENCE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define VCE_CMD_TRAP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define VCE_CMD_IB_AUTO 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define VCE_CMD_SEMAPHORE 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define ATC_VMID0_PASID_MAPPING 0x339Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define ATC_VM_APERTURE0_CNTL 0x3310u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define ATS_ACCESS_MODE_NEVER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define ATS_ACCESS_MODE_ALWAYS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define ATC_VM_APERTURE0_CNTL2 0x3318u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define ATC_VM_APERTURE1_CNTL 0x3314u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define ATC_VM_APERTURE1_CNTL2 0x331Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define IH_VMID_0_LUT 0x3D40u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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