^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2012 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <drm/drm_vblank.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "cik_blit_shaders.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "cikd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "clearstate_ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "radeon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "radeon_asic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "radeon_audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "radeon_ucode.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SH_MEM_CONFIG_GFX_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_FIRMWARE("radeon/bonaire_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_FIRMWARE("radeon/bonaire_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_FIRMWARE("radeon/bonaire_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_FIRMWARE("radeon/bonaire_mc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_FIRMWARE("radeon/bonaire_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MODULE_FIRMWARE("radeon/HAWAII_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_FIRMWARE("radeon/hawaii_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_FIRMWARE("radeon/hawaii_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_FIRMWARE("radeon/hawaii_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_FIRMWARE("radeon/hawaii_mc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_FIRMWARE("radeon/hawaii_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_FIRMWARE("radeon/KAVERI_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_FIRMWARE("radeon/kaveri_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODULE_FIRMWARE("radeon/kaveri_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_FIRMWARE("radeon/kaveri_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_FIRMWARE("radeon/KABINI_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_FIRMWARE("radeon/KABINI_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_FIRMWARE("radeon/KABINI_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_FIRMWARE("radeon/kabini_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_FIRMWARE("radeon/kabini_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_FIRMWARE("radeon/kabini_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_FIRMWARE("radeon/kabini_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_FIRMWARE("radeon/kabini_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_FIRMWARE("radeon/kabini_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MODULE_FIRMWARE("radeon/MULLINS_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_FIRMWARE("radeon/mullins_pfp.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_FIRMWARE("radeon/mullins_me.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MODULE_FIRMWARE("radeon/mullins_ce.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MODULE_FIRMWARE("radeon/mullins_mec.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_FIRMWARE("radeon/mullins_rlc.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODULE_FIRMWARE("radeon/mullins_sdma.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern int r600_ih_ring_alloc(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern void r600_ih_ring_fini(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern bool evergreen_is_display_hung(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern void sumo_rlc_fini(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern int sumo_rlc_init(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern void si_rlc_reset(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern int cik_sdma_resume(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern void cik_sdma_fini(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void cik_rlc_stop(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void cik_pcie_gen3_enable(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void cik_program_aspm(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void cik_init_pg(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void cik_init_cg(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void cik_fini_pg(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void cik_fini_cg(struct radeon_device *rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * cik_get_allowed_info_register - fetch the register for the info ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @reg: register offset in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @val: register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Returns 0 for success or -EINVAL for an invalid register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int cik_get_allowed_info_register(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case GRBM_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case GRBM_STATUS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case GRBM_STATUS_SE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case GRBM_STATUS_SE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case GRBM_STATUS_SE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case GRBM_STATUS_SE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case SRBM_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case SRBM_STATUS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case UVD_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* TODO VCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *val = RREG32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Indirect registers accessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_lock_irqsave(&rdev->didt_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) WREG32(CIK_DIDT_IND_INDEX, (reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) r = RREG32(CIK_DIDT_IND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_irqsave(&rdev->didt_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WREG32(CIK_DIDT_IND_INDEX, (reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) WREG32(CIK_DIDT_IND_DATA, (v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* get temperature in millidegrees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ci_get_temp(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int actual_temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CTF_TEMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (temp & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) actual_temp = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) actual_temp = temp & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return actual_temp * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* get temperature in millidegrees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int kv_get_temp(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int actual_temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) temp = RREG32_SMC(0xC0300E0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) actual_temp = (temp / 8) - 49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) actual_temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return actual_temp * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Indirect registers accessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) WREG32(PCIE_INDEX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (void)RREG32(PCIE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) r = RREG32(PCIE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) WREG32(PCIE_INDEX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (void)RREG32(PCIE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) WREG32(PCIE_DATA, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (void)RREG32(PCIE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const u32 spectre_rlc_save_restore_register_list[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (0x0e00 << 16) | (0xc12c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (0x0e00 << 16) | (0xc140 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (0x0e00 << 16) | (0xc150 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (0x0e00 << 16) | (0xc15c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (0x0e00 << 16) | (0xc168 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (0x0e00 << 16) | (0xc170 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (0x0e00 << 16) | (0xc178 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (0x0e00 << 16) | (0xc204 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (0x0e00 << 16) | (0xc2b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (0x0e00 << 16) | (0xc2b8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) (0x0e00 << 16) | (0xc2bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (0x0e00 << 16) | (0xc2c0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (0x0e00 << 16) | (0x8228 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (0x0e00 << 16) | (0x829c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (0x0e00 << 16) | (0x869c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (0x0600 << 16) | (0x98f4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (0x0e00 << 16) | (0x98f8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (0x0e00 << 16) | (0x9900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) (0x0e00 << 16) | (0xc260 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (0x0e00 << 16) | (0x90e8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (0x0e00 << 16) | (0x3c000 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (0x0e00 << 16) | (0x3c00c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (0x0e00 << 16) | (0x8c1c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (0x0e00 << 16) | (0x9700 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (0x0e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) (0x4e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (0x5e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) (0x6e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (0x7e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (0x8e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (0x9e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (0xae00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (0xbe00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (0x0e00 << 16) | (0x89bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (0x0e00 << 16) | (0x8900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (0x0e00 << 16) | (0xc130 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (0x0e00 << 16) | (0xc134 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (0x0e00 << 16) | (0xc1fc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (0x0e00 << 16) | (0xc208 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (0x0e00 << 16) | (0xc264 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (0x0e00 << 16) | (0xc268 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (0x0e00 << 16) | (0xc26c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (0x0e00 << 16) | (0xc270 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (0x0e00 << 16) | (0xc274 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (0x0e00 << 16) | (0xc278 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (0x0e00 << 16) | (0xc27c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (0x0e00 << 16) | (0xc280 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (0x0e00 << 16) | (0xc284 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) (0x0e00 << 16) | (0xc288 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (0x0e00 << 16) | (0xc28c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (0x0e00 << 16) | (0xc290 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (0x0e00 << 16) | (0xc294 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (0x0e00 << 16) | (0xc298 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (0x0e00 << 16) | (0xc29c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (0x0e00 << 16) | (0xc2a0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (0x0e00 << 16) | (0xc2a4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (0x0e00 << 16) | (0xc2a8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) (0x0e00 << 16) | (0xc2ac >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (0x0e00 << 16) | (0xc2b0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (0x0e00 << 16) | (0x301d0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (0x0e00 << 16) | (0x30238 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (0x0e00 << 16) | (0x30250 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (0x0e00 << 16) | (0x30254 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) (0x0e00 << 16) | (0x30258 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (0x0e00 << 16) | (0x3025c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (0x4e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (0x5e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (0x6e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (0x7e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (0x8e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (0x9e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (0xae00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (0xbe00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (0x4e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (0x5e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) (0x6e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (0x7e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) (0x8e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (0x9e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (0xae00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (0xbe00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) (0x4e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) (0x5e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) (0x6e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) (0x7e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (0x8e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (0x9e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (0xae00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (0xbe00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (0x4e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (0x5e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (0x6e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) (0x7e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (0x8e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (0x9e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) (0xae00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (0xbe00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (0x4e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) (0x5e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (0x6e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (0x7e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) (0x8e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (0x9e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (0xae00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (0xbe00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (0x0e00 << 16) | (0xc99c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) (0x0e00 << 16) | (0x9834 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (0x0000 << 16) | (0x30f00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (0x0001 << 16) | (0x30f00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (0x0000 << 16) | (0x30f04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (0x0001 << 16) | (0x30f04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (0x0000 << 16) | (0x30f08 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) (0x0001 << 16) | (0x30f08 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (0x0000 << 16) | (0x30f0c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (0x0001 << 16) | (0x30f0c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (0x0600 << 16) | (0x9b7c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (0x0e00 << 16) | (0x8a14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (0x0e00 << 16) | (0x8a18 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (0x0600 << 16) | (0x30a00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (0x0e00 << 16) | (0x8bf0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (0x0e00 << 16) | (0x8bcc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (0x0e00 << 16) | (0x8b24 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (0x0e00 << 16) | (0x30a04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) (0x0600 << 16) | (0x30a10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) (0x0600 << 16) | (0x30a14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (0x0600 << 16) | (0x30a18 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (0x0600 << 16) | (0x30a2c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) (0x0e00 << 16) | (0xc700 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) (0x0e00 << 16) | (0xc704 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) (0x0e00 << 16) | (0xc708 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (0x0e00 << 16) | (0xc768 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (0x0400 << 16) | (0xc770 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (0x0400 << 16) | (0xc774 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (0x0400 << 16) | (0xc778 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) (0x0400 << 16) | (0xc77c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) (0x0400 << 16) | (0xc780 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) (0x0400 << 16) | (0xc784 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) (0x0400 << 16) | (0xc788 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) (0x0400 << 16) | (0xc78c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (0x0400 << 16) | (0xc798 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) (0x0400 << 16) | (0xc79c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) (0x0400 << 16) | (0xc7a0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) (0x0400 << 16) | (0xc7a4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) (0x0400 << 16) | (0xc7a8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (0x0400 << 16) | (0xc7ac >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) (0x0400 << 16) | (0xc7b0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (0x0400 << 16) | (0xc7b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (0x0e00 << 16) | (0x9100 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) (0x0e00 << 16) | (0x3c010 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (0x0e00 << 16) | (0x92a8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (0x0e00 << 16) | (0x92ac >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) (0x0e00 << 16) | (0x92b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) (0x0e00 << 16) | (0x92b8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) (0x0e00 << 16) | (0x92bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (0x0e00 << 16) | (0x92c0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) (0x0e00 << 16) | (0x92c4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (0x0e00 << 16) | (0x92c8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) (0x0e00 << 16) | (0x92cc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) (0x0e00 << 16) | (0x92d0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) (0x0e00 << 16) | (0x8c00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) (0x0e00 << 16) | (0x8c04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) (0x0e00 << 16) | (0x8c20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (0x0e00 << 16) | (0x8c38 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) (0x0e00 << 16) | (0x8c3c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) (0x0e00 << 16) | (0xae00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (0x0e00 << 16) | (0x9604 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (0x0e00 << 16) | (0xac08 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) (0x0e00 << 16) | (0xac0c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) (0x0e00 << 16) | (0xac10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (0x0e00 << 16) | (0xac14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) (0x0e00 << 16) | (0xac58 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (0x0e00 << 16) | (0xac68 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) (0x0e00 << 16) | (0xac6c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) (0x0e00 << 16) | (0xac70 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (0x0e00 << 16) | (0xac74 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) (0x0e00 << 16) | (0xac78 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) (0x0e00 << 16) | (0xac7c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) (0x0e00 << 16) | (0xac80 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (0x0e00 << 16) | (0xac84 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (0x0e00 << 16) | (0xac88 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (0x0e00 << 16) | (0xac8c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (0x0e00 << 16) | (0x970c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (0x0e00 << 16) | (0x9714 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) (0x0e00 << 16) | (0x9718 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) (0x0e00 << 16) | (0x971c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (0x0e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (0x4e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (0x5e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (0x6e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (0x7e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (0x8e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) (0x9e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (0xae00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (0xbe00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (0x0e00 << 16) | (0xcd10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) (0x0e00 << 16) | (0xcd14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (0x0e00 << 16) | (0x88b0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) (0x0e00 << 16) | (0x88b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (0x0e00 << 16) | (0x88b8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) (0x0e00 << 16) | (0x88bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) (0x0400 << 16) | (0x89c0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) (0x0e00 << 16) | (0x88c4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (0x0e00 << 16) | (0x88c8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) (0x0e00 << 16) | (0x88d0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) (0x0e00 << 16) | (0x88d4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (0x0e00 << 16) | (0x88d8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (0x0e00 << 16) | (0x8980 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) (0x0e00 << 16) | (0x30938 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) (0x0e00 << 16) | (0x3093c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (0x0e00 << 16) | (0x30940 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (0x0e00 << 16) | (0x89a0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) (0x0e00 << 16) | (0x30900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) (0x0e00 << 16) | (0x30904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (0x0e00 << 16) | (0x89b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (0x0e00 << 16) | (0x3c210 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) (0x0e00 << 16) | (0x3c214 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (0x0e00 << 16) | (0x3c218 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) (0x0e00 << 16) | (0x8904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) (0x0e00 << 16) | (0x8c28 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) (0x0e00 << 16) | (0x8c2c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (0x0e00 << 16) | (0x8c30 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (0x0e00 << 16) | (0x8c34 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) (0x0e00 << 16) | (0x9600 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const u32 kalindi_rlc_save_restore_register_list[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (0x0e00 << 16) | (0xc12c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (0x0e00 << 16) | (0xc140 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (0x0e00 << 16) | (0xc150 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (0x0e00 << 16) | (0xc15c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (0x0e00 << 16) | (0xc168 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (0x0e00 << 16) | (0xc170 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) (0x0e00 << 16) | (0xc204 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) (0x0e00 << 16) | (0xc2b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (0x0e00 << 16) | (0xc2b8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (0x0e00 << 16) | (0xc2bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (0x0e00 << 16) | (0xc2c0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (0x0e00 << 16) | (0x8228 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) (0x0e00 << 16) | (0x829c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) (0x0e00 << 16) | (0x869c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (0x0600 << 16) | (0x98f4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) (0x0e00 << 16) | (0x98f8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) (0x0e00 << 16) | (0x9900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (0x0e00 << 16) | (0xc260 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (0x0e00 << 16) | (0x90e8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) (0x0e00 << 16) | (0x3c000 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (0x0e00 << 16) | (0x3c00c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) (0x0e00 << 16) | (0x8c1c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) (0x0e00 << 16) | (0x9700 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (0x0e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (0x4e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) (0x5e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) (0x6e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (0x7e00 << 16) | (0xcd20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (0x0e00 << 16) | (0x89bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) (0x0e00 << 16) | (0x8900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) (0x0e00 << 16) | (0xc130 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) (0x0e00 << 16) | (0xc134 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) (0x0e00 << 16) | (0xc1fc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) (0x0e00 << 16) | (0xc208 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) (0x0e00 << 16) | (0xc264 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) (0x0e00 << 16) | (0xc268 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) (0x0e00 << 16) | (0xc26c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) (0x0e00 << 16) | (0xc270 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) (0x0e00 << 16) | (0xc274 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (0x0e00 << 16) | (0xc28c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) (0x0e00 << 16) | (0xc290 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) (0x0e00 << 16) | (0xc294 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) (0x0e00 << 16) | (0xc298 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) (0x0e00 << 16) | (0xc2a0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) (0x0e00 << 16) | (0xc2a4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) (0x0e00 << 16) | (0xc2a8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) (0x0e00 << 16) | (0xc2ac >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) (0x0e00 << 16) | (0x301d0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (0x0e00 << 16) | (0x30238 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (0x0e00 << 16) | (0x30250 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (0x0e00 << 16) | (0x30254 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (0x0e00 << 16) | (0x30258 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (0x0e00 << 16) | (0x3025c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) (0x4e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (0x5e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) (0x6e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) (0x7e00 << 16) | (0xc900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (0x4e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (0x5e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) (0x6e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) (0x7e00 << 16) | (0xc904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) (0x4e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (0x5e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (0x6e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) (0x7e00 << 16) | (0xc908 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (0x4e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (0x5e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) (0x6e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) (0x7e00 << 16) | (0xc90c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) (0x4e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) (0x5e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (0x6e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) (0x7e00 << 16) | (0xc910 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) (0x0e00 << 16) | (0xc99c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) (0x0e00 << 16) | (0x9834 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) (0x0000 << 16) | (0x30f00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) (0x0000 << 16) | (0x30f04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) (0x0000 << 16) | (0x30f08 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) (0x0000 << 16) | (0x30f0c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) (0x0600 << 16) | (0x9b7c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (0x0e00 << 16) | (0x8a14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) (0x0e00 << 16) | (0x8a18 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) (0x0600 << 16) | (0x30a00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) (0x0e00 << 16) | (0x8bf0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) (0x0e00 << 16) | (0x8bcc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) (0x0e00 << 16) | (0x8b24 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) (0x0e00 << 16) | (0x30a04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) (0x0600 << 16) | (0x30a10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) (0x0600 << 16) | (0x30a14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) (0x0600 << 16) | (0x30a18 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) (0x0600 << 16) | (0x30a2c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) (0x0e00 << 16) | (0xc700 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) (0x0e00 << 16) | (0xc704 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) (0x0e00 << 16) | (0xc708 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (0x0e00 << 16) | (0xc768 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (0x0400 << 16) | (0xc770 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) (0x0400 << 16) | (0xc774 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) (0x0400 << 16) | (0xc798 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) (0x0400 << 16) | (0xc79c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) (0x0e00 << 16) | (0x9100 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (0x0e00 << 16) | (0x3c010 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) (0x0e00 << 16) | (0x8c00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (0x0e00 << 16) | (0x8c04 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) (0x0e00 << 16) | (0x8c20 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) (0x0e00 << 16) | (0x8c38 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) (0x0e00 << 16) | (0x8c3c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) (0x0e00 << 16) | (0xae00 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (0x0e00 << 16) | (0x9604 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) (0x0e00 << 16) | (0xac08 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) (0x0e00 << 16) | (0xac0c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) (0x0e00 << 16) | (0xac10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) (0x0e00 << 16) | (0xac14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) (0x0e00 << 16) | (0xac58 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) (0x0e00 << 16) | (0xac68 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (0x0e00 << 16) | (0xac6c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) (0x0e00 << 16) | (0xac70 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (0x0e00 << 16) | (0xac74 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) (0x0e00 << 16) | (0xac78 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) (0x0e00 << 16) | (0xac7c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) (0x0e00 << 16) | (0xac80 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) (0x0e00 << 16) | (0xac84 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) (0x0e00 << 16) | (0xac88 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (0x0e00 << 16) | (0xac8c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (0x0e00 << 16) | (0x970c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (0x0e00 << 16) | (0x9714 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) (0x0e00 << 16) | (0x9718 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) (0x0e00 << 16) | (0x971c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) (0x0e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (0x4e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) (0x5e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (0x6e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) (0x7e00 << 16) | (0x31068 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) (0x0e00 << 16) | (0xcd10 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) (0x0e00 << 16) | (0xcd14 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) (0x0e00 << 16) | (0x88b0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) (0x0e00 << 16) | (0x88b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (0x0e00 << 16) | (0x88b8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) (0x0e00 << 16) | (0x88bc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) (0x0400 << 16) | (0x89c0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) (0x0e00 << 16) | (0x88c4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) (0x0e00 << 16) | (0x88c8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) (0x0e00 << 16) | (0x88d0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) (0x0e00 << 16) | (0x88d4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (0x0e00 << 16) | (0x88d8 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) (0x0e00 << 16) | (0x8980 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) (0x0e00 << 16) | (0x30938 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) (0x0e00 << 16) | (0x3093c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) (0x0e00 << 16) | (0x30940 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) (0x0e00 << 16) | (0x89a0 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) (0x0e00 << 16) | (0x30900 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (0x0e00 << 16) | (0x30904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) (0x0e00 << 16) | (0x89b4 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) (0x0e00 << 16) | (0x3e1fc >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) (0x0e00 << 16) | (0x3c210 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) (0x0e00 << 16) | (0x3c214 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) (0x0e00 << 16) | (0x3c218 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) (0x0e00 << 16) | (0x8904 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) (0x0e00 << 16) | (0x8c28 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) (0x0e00 << 16) | (0x8c2c >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) (0x0e00 << 16) | (0x8c30 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) (0x0e00 << 16) | (0x8c34 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) (0x0e00 << 16) | (0x9600 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const u32 bonaire_golden_spm_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) 0x30800, 0xe0ffffff, 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const u32 bonaire_golden_common_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) 0xc770, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) 0xc774, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) 0xc798, 0xffffffff, 0x00007fbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) 0xc79c, 0xffffffff, 0x00007faf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const u32 bonaire_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) 0x3354, 0x00000333, 0x00000333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) 0x3350, 0x000c0fc0, 0x00040200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) 0x9a10, 0x00010000, 0x00058208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) 0x3c000, 0xffff1fff, 0x00140000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) 0x3c200, 0xfdfc0fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) 0x3c234, 0x40000000, 0x40000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) 0x9830, 0xffffffff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) 0x9834, 0xf00fffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) 0x9838, 0x0002021c, 0x00020200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) 0xc78, 0x00000080, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) 0x5bb0, 0x000000f0, 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) 0x5bc0, 0xf0311fff, 0x80300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) 0x98f8, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) 0x350c, 0x00810000, 0x408af000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) 0x7030, 0x31000111, 0x00000011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) 0x2f48, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) 0x220c, 0x00007fb6, 0x0021a1b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) 0x2210, 0x00007fb6, 0x002021b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) 0x2180, 0x00007fb6, 0x00002191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) 0x2218, 0x00007fb6, 0x002121b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) 0x221c, 0x00007fb6, 0x002021b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) 0x21dc, 0x00007fb6, 0x00002191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) 0x21e0, 0x00007fb6, 0x00002191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) 0x3628, 0x0000003f, 0x0000000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) 0x362c, 0x0000003f, 0x0000000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) 0x2ae4, 0x00073ffe, 0x000022a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) 0x240c, 0x000007ff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) 0x8a14, 0xf000003f, 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) 0x8bf0, 0x00002001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) 0x8b24, 0xffffffff, 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) 0x30a04, 0x0000ff0f, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) 0x28a4c, 0x07ffffff, 0x06000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) 0x4d8, 0x00000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) 0x3e78, 0x00000001, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) 0x9100, 0x03000000, 0x0362c688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) 0x8c00, 0x000000ff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) 0xe40, 0x00001fff, 0x00001fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) 0x9060, 0x0000007f, 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) 0x9508, 0x00010000, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) 0xac14, 0x000003ff, 0x000000f3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) 0xac0c, 0xffffffff, 0x00001032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const u32 bonaire_mgcg_cgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) 0xc420, 0xffffffff, 0xfffffffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) 0x3c2a0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) 0x3c208, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) 0x3c2c0, 0xffffffff, 0xc0000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) 0x3c2c8, 0xffffffff, 0xc0000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) 0x3c2c4, 0xffffffff, 0xc0000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) 0x55e4, 0xffffffff, 0x00600100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) 0x3c280, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) 0x3c214, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) 0x3c220, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) 0x3c218, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) 0x3c204, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) 0x3c2e0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) 0x3c224, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) 0x3c200, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) 0x3c230, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) 0x3c234, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) 0x3c250, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) 0x3c254, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) 0x3c258, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) 0x3c25c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 0x3c260, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) 0x3c27c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) 0x3c278, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) 0x3c210, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) 0x3c290, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) 0x3c274, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) 0x3c2b4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) 0x3c2b0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) 0x3c270, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) 0x3c020, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) 0x3c024, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) 0x3c028, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) 0x3c02c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) 0x3c030, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) 0x3c034, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) 0x3c038, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) 0x3c03c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) 0x3c040, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) 0x3c044, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) 0x3c048, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) 0x3c04c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) 0x3c050, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) 0x3c054, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) 0x3c058, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) 0x3c05c, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) 0x3c060, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) 0x3c064, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) 0x3c068, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) 0x3c06c, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) 0x3c070, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) 0x3c074, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) 0x3c078, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) 0x3c07c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 0x3c080, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 0x3c084, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 0x3c088, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) 0x3c08c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) 0x3c090, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 0x3c094, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) 0x3c098, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) 0x3c09c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) 0x3c0a0, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) 0x3c0a4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) 0x3c0a8, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) 0x3c000, 0xffffffff, 0x96e00200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) 0x8708, 0xffffffff, 0x00900100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) 0xc424, 0xffffffff, 0x0020003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) 0x38, 0xffffffff, 0x0140001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) 0x3c, 0x000f0000, 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) 0x220, 0xffffffff, 0xC060000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) 0x224, 0xc0000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) 0xf90, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) 0xf98, 0x00000101, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) 0x20a8, 0xffffffff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) 0x55e4, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) 0x30cc, 0xc0000fff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) 0xc1e4, 0x00000001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) 0xd00c, 0xff000ff0, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) 0xd80c, 0xff000ff0, 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const u32 spectre_golden_spm_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) 0x30800, 0xe0ffffff, 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static const u32 spectre_golden_common_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) 0xc770, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) 0xc774, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) 0xc798, 0xffffffff, 0x00007fbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) 0xc79c, 0xffffffff, 0x00007faf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const u32 spectre_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) 0x3c000, 0xffff1fff, 0x96940200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) 0x3c00c, 0xffff0001, 0xff000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) 0x3c200, 0xfffc0fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) 0x6ed8, 0x00010101, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) 0x9834, 0xf00fffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) 0x9838, 0xfffffffc, 0x00020200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) 0x5bb0, 0x000000f0, 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 0x5bc0, 0xf0311fff, 0x80300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) 0x98f8, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) 0x9b7c, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) 0x2f48, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) 0x8a14, 0xf000003f, 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) 0x8b24, 0xffffffff, 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) 0x28350, 0x3f3f3fff, 0x00000082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) 0x28354, 0x0000003f, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) 0x3e78, 0x00000001, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) 0x913c, 0xffff03df, 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) 0xc768, 0x00000008, 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) 0x8c00, 0x000008ff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) 0x9508, 0x00010000, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) 0xac0c, 0xffffffff, 0x54763210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) 0x214f8, 0x01ff01ff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) 0x21498, 0x007ff800, 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) 0x2015c, 0xffffffff, 0x00000f40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) 0x30934, 0xffffffff, 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static const u32 spectre_mgcg_cgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) 0xc420, 0xffffffff, 0xfffffffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) 0x3c2a0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) 0x3c208, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) 0x3c2c0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) 0x3c2c8, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) 0x3c2c4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) 0x55e4, 0xffffffff, 0x00600100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) 0x3c280, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) 0x3c214, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 0x3c220, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) 0x3c218, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) 0x3c204, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) 0x3c2e0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 0x3c224, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) 0x3c200, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) 0x3c230, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) 0x3c234, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) 0x3c250, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) 0x3c254, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) 0x3c258, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) 0x3c25c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 0x3c260, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) 0x3c27c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) 0x3c278, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) 0x3c210, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 0x3c290, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) 0x3c274, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) 0x3c2b4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) 0x3c2b0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) 0x3c270, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) 0x3c020, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) 0x3c024, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) 0x3c028, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) 0x3c02c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 0x3c030, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) 0x3c034, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) 0x3c038, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) 0x3c03c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) 0x3c040, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) 0x3c044, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) 0x3c048, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) 0x3c04c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) 0x3c050, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) 0x3c054, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) 0x3c058, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) 0x3c05c, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) 0x3c060, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) 0x3c064, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) 0x3c068, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) 0x3c06c, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) 0x3c070, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) 0x3c074, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) 0x3c078, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) 0x3c07c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) 0x3c080, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) 0x3c084, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) 0x3c088, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) 0x3c08c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) 0x3c090, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) 0x3c094, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) 0x3c098, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) 0x3c09c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) 0x3c0a0, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) 0x3c0a4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) 0x3c0a8, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) 0x3c0ac, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) 0x3c0b0, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) 0x3c0b4, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) 0x3c0b8, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) 0x3c0bc, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) 0x3c000, 0xffffffff, 0x96e00200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) 0x8708, 0xffffffff, 0x00900100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 0xc424, 0xffffffff, 0x0020003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) 0x38, 0xffffffff, 0x0140001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) 0x3c, 0x000f0000, 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) 0x220, 0xffffffff, 0xC060000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) 0x224, 0xc0000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) 0xf90, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) 0xf98, 0x00000101, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) 0x20a8, 0xffffffff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) 0x55e4, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) 0x30cc, 0xc0000fff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) 0xc1e4, 0x00000001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) 0xd00c, 0xff000ff0, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) 0xd80c, 0xff000ff0, 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const u32 kalindi_golden_spm_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) 0x30800, 0xe0ffffff, 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const u32 kalindi_golden_common_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) 0xc770, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) 0xc774, 0xffffffff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) 0xc798, 0xffffffff, 0x00007fbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) 0xc79c, 0xffffffff, 0x00007faf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const u32 kalindi_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) 0x3c000, 0xffffdfff, 0x6e944040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) 0x55e4, 0xff607fff, 0xfc000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) 0x3c220, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) 0x3c224, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) 0x3c200, 0xfffc0fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) 0x6ed8, 0x00010101, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) 0x9830, 0xffffffff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) 0x9834, 0xf00fffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) 0x5bb0, 0x000000f0, 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) 0x5bc0, 0xf0311fff, 0x80300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) 0x98f8, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) 0x98fc, 0xffffffff, 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) 0x9b7c, 0x00ff0000, 0x00fc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) 0x8030, 0x00001f0f, 0x0000100a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) 0x2f48, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) 0x2408, 0x000fffff, 0x000c007f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) 0x8a14, 0xf000003f, 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) 0x8b24, 0x3fff3fff, 0x00ffcfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) 0x30a04, 0x0000ff0f, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) 0x28a4c, 0x07ffffff, 0x06000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) 0x4d8, 0x00000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) 0x3e78, 0x00000001, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) 0xc768, 0x00000008, 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) 0x8c00, 0x000000ff, 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) 0x214f8, 0x01ff01ff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) 0x21498, 0x007ff800, 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) 0x2015c, 0xffffffff, 0x00000f40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) 0x88c4, 0x001f3ae3, 0x00000082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) 0x88d4, 0x0000001f, 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) 0x30934, 0xffffffff, 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const u32 kalindi_mgcg_cgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) 0xc420, 0xffffffff, 0xfffffffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) 0x3c2a0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) 0x3c208, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) 0x3c2c0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) 0x3c2c8, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) 0x3c2c4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) 0x55e4, 0xffffffff, 0x00600100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) 0x3c280, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) 0x3c214, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) 0x3c220, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) 0x3c218, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) 0x3c204, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) 0x3c2e0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) 0x3c224, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) 0x3c200, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) 0x3c230, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) 0x3c234, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) 0x3c250, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) 0x3c254, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) 0x3c258, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) 0x3c25c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 0x3c260, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) 0x3c27c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) 0x3c278, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) 0x3c210, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) 0x3c290, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) 0x3c274, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) 0x3c2b4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) 0x3c2b0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) 0x3c270, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) 0x3c020, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) 0x3c024, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) 0x3c028, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) 0x3c02c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) 0x3c030, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) 0x3c034, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) 0x3c038, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) 0x3c03c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) 0x3c040, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) 0x3c044, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) 0x3c000, 0xffffffff, 0x96e00200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) 0x8708, 0xffffffff, 0x00900100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) 0xc424, 0xffffffff, 0x0020003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) 0x38, 0xffffffff, 0x0140001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) 0x3c, 0x000f0000, 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) 0x220, 0xffffffff, 0xC060000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) 0x224, 0xc0000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) 0x20a8, 0xffffffff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) 0x55e4, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) 0x30cc, 0xc0000fff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) 0xc1e4, 0x00000001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) 0xd00c, 0xff000ff0, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) 0xd80c, 0xff000ff0, 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const u32 hawaii_golden_spm_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) 0x30800, 0xe0ffffff, 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const u32 hawaii_golden_common_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) 0x28350, 0xffffffff, 0x3a00161a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) 0x28354, 0xffffffff, 0x0000002e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) 0x9a10, 0xffffffff, 0x00018208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) 0x98f8, 0xffffffff, 0x12011003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const u32 hawaii_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) 0x3354, 0x00000333, 0x00000333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) 0x9a10, 0x00010000, 0x00058208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) 0x9830, 0xffffffff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) 0x9834, 0xf00fffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) 0x9838, 0x0002021c, 0x00020200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) 0xc78, 0x00000080, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) 0x5bb0, 0x000000f0, 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) 0x5bc0, 0xf0311fff, 0x80300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) 0x350c, 0x00810000, 0x408af000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) 0x7030, 0x31000111, 0x00000011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) 0x2f48, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) 0x2120, 0x0000007f, 0x0000001b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) 0x21dc, 0x00007fb6, 0x00002191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) 0x3628, 0x0000003f, 0x0000000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) 0x362c, 0x0000003f, 0x0000000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) 0x2ae4, 0x00073ffe, 0x000022a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) 0x240c, 0x000007ff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) 0x8bf0, 0x00002001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) 0x8b24, 0xffffffff, 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) 0x30a04, 0x0000ff0f, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) 0x28a4c, 0x07ffffff, 0x06000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) 0x3e78, 0x00000001, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) 0xc768, 0x00000008, 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) 0xc770, 0x00000f00, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) 0xc774, 0x00000f00, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) 0xc798, 0x00ffffff, 0x00ff7fbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) 0xc79c, 0x00ffffff, 0x00ff7faf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) 0x8c00, 0x000000ff, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) 0xe40, 0x00001fff, 0x00001fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) 0x9060, 0x0000007f, 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) 0x9508, 0x00010000, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) 0xae00, 0x00100000, 0x000ff07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 0xac14, 0x000003ff, 0x0000000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) 0xac10, 0xffffffff, 0x7564fdec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) 0xac0c, 0xffffffff, 0x3120b9a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) 0xac08, 0x20000000, 0x0f9c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const u32 hawaii_mgcg_cgcg_init[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) 0xc420, 0xffffffff, 0xfffffffd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) 0x3c2a0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) 0x3c208, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) 0x3c2c0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) 0x3c2c8, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) 0x3c2c4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) 0x55e4, 0xffffffff, 0x00200100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) 0x3c280, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) 0x3c214, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) 0x3c220, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) 0x3c218, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) 0x3c204, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) 0x3c2e0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) 0x3c224, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) 0x3c200, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) 0x3c230, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) 0x3c234, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) 0x3c250, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) 0x3c254, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) 0x3c258, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 0x3c25c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 0x3c260, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) 0x3c27c, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) 0x3c278, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) 0x3c210, 0xffffffff, 0x06000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) 0x3c290, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) 0x3c274, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) 0x3c2b4, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) 0x3c2b0, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) 0x3c270, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) 0x30800, 0xffffffff, 0xe0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) 0x3c020, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) 0x3c024, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 0x3c028, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) 0x3c02c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) 0x3c030, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) 0x3c034, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) 0x3c038, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) 0x3c03c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) 0x3c040, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) 0x3c044, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) 0x3c048, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) 0x3c04c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 0x3c050, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) 0x3c054, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) 0x3c058, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) 0x3c05c, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) 0x3c060, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) 0x3c064, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) 0x3c068, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) 0x3c06c, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) 0x3c070, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) 0x3c074, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 0x3c078, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) 0x3c07c, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) 0x3c080, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) 0x3c084, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) 0x3c088, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) 0x3c08c, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) 0x3c090, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) 0x3c094, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) 0x3c098, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) 0x3c09c, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) 0x3c0a0, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) 0x3c0a4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) 0x3c0a8, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) 0x3c0ac, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) 0x3c0b0, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) 0x3c0b4, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) 0x3c0b8, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) 0x3c0bc, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) 0x3c0c0, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) 0x3c0c4, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) 0x3c0c8, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) 0x3c0cc, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) 0x3c0d0, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) 0x3c0d4, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) 0x3c0d8, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) 0x3c0dc, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) 0x3c0e0, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) 0x3c0e4, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) 0x3c0e8, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) 0x3c0ec, 0xffffffff, 0x00030002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) 0x3c0f0, 0xffffffff, 0x00040007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) 0x3c0f4, 0xffffffff, 0x00060005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) 0x3c0f8, 0xffffffff, 0x00090008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) 0xc318, 0xffffffff, 0x00020200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) 0x3350, 0xffffffff, 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) 0x15c0, 0xffffffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) 0x55e8, 0xffffffff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) 0x2f50, 0xffffffff, 0x00000902,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) 0x3c000, 0xffffffff, 0x96940200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) 0x8708, 0xffffffff, 0x00900100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) 0xc424, 0xffffffff, 0x0020003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) 0x38, 0xffffffff, 0x0140001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) 0x3c, 0x000f0000, 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) 0x220, 0xffffffff, 0xc060000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) 0x224, 0xc0000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) 0xf90, 0xffffffff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) 0xf98, 0x00000101, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) 0x20a8, 0xffffffff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) 0x55e4, 0xff000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) 0x30cc, 0xc0000fff, 0x00000104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) 0xc1e4, 0x00000001, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) 0xd00c, 0xff000ff0, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) 0xd80c, 0xff000ff0, 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const u32 godavari_golden_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) 0x55e4, 0xff607fff, 0xfc000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) 0x6ed8, 0x00010101, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) 0x9830, 0xffffffff, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) 0x98302, 0xf00fffff, 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) 0x6130, 0xffffffff, 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) 0x5bb0, 0x000000f0, 0x00000070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) 0x5bc0, 0xf0311fff, 0x80300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) 0x98f8, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) 0x98fc, 0xffffffff, 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) 0x8030, 0x00001f0f, 0x0000100a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) 0x2f48, 0x73773777, 0x12010001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) 0x2408, 0x000fffff, 0x000c007f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) 0x8a14, 0xf000003f, 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) 0x8b24, 0xffffffff, 0x00ff0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) 0x30a04, 0x0000ff0f, 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) 0x28a4c, 0x07ffffff, 0x06000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) 0x4d8, 0x00000fff, 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) 0xd014, 0x00010000, 0x00810001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) 0xd814, 0x00010000, 0x00810001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) 0x3e78, 0x00000001, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) 0xc768, 0x00000008, 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) 0xc770, 0x00000f00, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) 0xc774, 0x00000f00, 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 0xc798, 0x00ffffff, 0x00ff7fbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) 0xc79c, 0x00ffffff, 0x00ff7faf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) 0x8c00, 0x000000ff, 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) 0x214f8, 0x01ff01ff, 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) 0x21498, 0x007ff800, 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) 0x2015c, 0xffffffff, 0x00000f40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) 0x88c4, 0x001f3ae3, 0x00000082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) 0x88d4, 0x0000001f, 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) 0x30934, 0xffffffff, 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static void cik_init_golden_registers(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) bonaire_mgcg_cgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) bonaire_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) (const u32)ARRAY_SIZE(bonaire_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) bonaire_golden_common_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) bonaire_golden_spm_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) case CHIP_KABINI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) kalindi_mgcg_cgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) kalindi_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) (const u32)ARRAY_SIZE(kalindi_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) kalindi_golden_common_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) kalindi_golden_spm_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) case CHIP_MULLINS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) kalindi_mgcg_cgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) godavari_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) (const u32)ARRAY_SIZE(godavari_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) kalindi_golden_common_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) kalindi_golden_spm_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case CHIP_KAVERI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) spectre_mgcg_cgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) spectre_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) (const u32)ARRAY_SIZE(spectre_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) spectre_golden_common_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) (const u32)ARRAY_SIZE(spectre_golden_common_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) spectre_golden_spm_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) hawaii_mgcg_cgcg_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hawaii_golden_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) (const u32)ARRAY_SIZE(hawaii_golden_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) hawaii_golden_common_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) radeon_program_register_sequence(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) hawaii_golden_spm_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * cik_get_xclk - get the xclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * Returns the reference clock used by the gfx engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) u32 cik_get_xclk(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) u32 reference_clock = rdev->clock.spll.reference_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (rdev->flags & RADEON_IS_IGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return reference_clock / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return reference_clock / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return reference_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * cik_mm_rdoorbell - read a doorbell dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * @index: doorbell index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * Returns the value in the doorbell aperture at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * requested doorbell index (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (index < rdev->doorbell.num_doorbells) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return readl(rdev->doorbell.ptr + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * cik_mm_wdoorbell - write a doorbell dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * @index: doorbell index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * @v: value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * Writes @v to the doorbell aperture at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * requested doorbell index (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (index < rdev->doorbell.num_doorbells) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) writel(v, rdev->doorbell.ptr + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define BONAIRE_IO_MC_REGS_SIZE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) {0x00000070, 0x04400000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {0x00000071, 0x80c01803},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {0x00000072, 0x00004004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {0x00000073, 0x00000100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {0x00000074, 0x00ff0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {0x00000075, 0x34000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {0x00000076, 0x08000014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {0x00000077, 0x00cc08ec},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {0x00000078, 0x00000400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {0x00000079, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {0x0000007a, 0x04090000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {0x0000007c, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {0x0000007e, 0x4408a8e8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {0x0000007f, 0x00000304},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) {0x00000080, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) {0x00000082, 0x00000001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {0x00000083, 0x00000002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {0x00000084, 0xf3e4f400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {0x00000085, 0x052024e3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {0x00000087, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) {0x00000088, 0x01000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {0x0000008a, 0x1c0a0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) {0x0000008b, 0xff010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {0x0000008d, 0xffffefff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {0x0000008e, 0xfff3efff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {0x0000008f, 0xfff3efbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {0x00000092, 0xf7ffffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {0x00000093, 0xffffff7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) {0x00000095, 0x00101101},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {0x00000096, 0x00000fff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {0x00000097, 0x00116fff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {0x00000098, 0x60010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {0x00000099, 0x10010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {0x0000009a, 0x00006000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {0x0000009b, 0x00001000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {0x0000009f, 0x00b48000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define HAWAII_IO_MC_REGS_SIZE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {0x0000007d, 0x40000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) {0x0000007e, 0x40180304},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) {0x0000007f, 0x0000ff00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {0x00000081, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {0x00000083, 0x00000800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) {0x00000086, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {0x00000087, 0x00000100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) {0x00000088, 0x00020100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {0x00000089, 0x00000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {0x0000008b, 0x00040000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {0x0000008c, 0x00000100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {0x0000008e, 0xff010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {0x00000090, 0xffffefff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {0x00000091, 0xfff3efff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {0x00000092, 0xfff3efbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {0x00000093, 0xf7ffffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {0x00000094, 0xffffff7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {0x00000095, 0x00000fff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {0x00000096, 0x00116fff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {0x00000097, 0x60010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {0x00000098, 0x10010000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {0x0000009f, 0x00c79000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * cik_srbm_select - select specific register instances
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * @me: selected ME (micro engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * @pipe: pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * @queue: queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * @vmid: VMID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * Switches the currently active registers instances. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * registers are instanced per VMID, others are instanced per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * me/pipe/queue combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static void cik_srbm_select(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) u32 me, u32 pipe, u32 queue, u32 vmid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) MEID(me & 0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) VMID(vmid & 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) QUEUEID(queue & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* ucode loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * ci_mc_load_microcode - load MC ucode into the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * Load the GDDR MC ucode into the hw (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * Returns 0 on success, error on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) int ci_mc_load_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) const __be32 *fw_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) const __le32 *new_fw_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) u32 running, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) u32 *io_mc_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) const __le32 *new_io_mc_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) int i, regs_size, ucode_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (!rdev->mc_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) const struct mc_firmware_header_v1_0 *hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) radeon_ucode_print_mc_hdr(&hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) new_io_mc_regs = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) new_fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ucode_size = rdev->mc_fw->size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) io_mc_regs = (u32 *)&bonaire_io_mc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) regs_size = BONAIRE_IO_MC_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) io_mc_regs = (u32 *)&hawaii_io_mc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) regs_size = HAWAII_IO_MC_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) fw_data = (const __be32 *)rdev->mc_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (running == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* reset the engine and set to writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* load mc io regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) for (i = 0; i < regs_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) tmp = RREG32(MC_SEQ_MISC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /* load the MC ucode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) for (i = 0; i < ucode_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (rdev->new_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* put the engine back into the active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* wait for training to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * cik_init_microcode - load ucode images from disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * Use the firmware interface to load the ucode images into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * the driver (not loaded into hw).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * Returns 0 on success, error on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static int cik_init_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) const char *chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) const char *new_chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) size_t pfp_req_size, me_req_size, ce_req_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) mec_req_size, rlc_req_size, mc_req_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) char fw_name[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) int new_fw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int num_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) bool new_smc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) DRM_DEBUG("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) chip_name = "BONAIRE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if ((rdev->pdev->revision == 0x80) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) (rdev->pdev->revision == 0x81) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) (rdev->pdev->device == 0x665f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) new_smc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) new_chip_name = "bonaire";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) me_req_size = CIK_ME_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ce_req_size = CIK_CE_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) mec_req_size = CIK_MEC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) num_fw = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) chip_name = "HAWAII";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (rdev->pdev->revision == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) new_smc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) new_chip_name = "hawaii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) me_req_size = CIK_ME_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ce_req_size = CIK_CE_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) mec_req_size = CIK_MEC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) num_fw = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) case CHIP_KAVERI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) chip_name = "KAVERI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) new_chip_name = "kaveri";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) me_req_size = CIK_ME_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ce_req_size = CIK_CE_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) mec_req_size = CIK_MEC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) rlc_req_size = KV_RLC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) num_fw = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) case CHIP_KABINI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) chip_name = "KABINI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) new_chip_name = "kabini";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) me_req_size = CIK_ME_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ce_req_size = CIK_CE_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) mec_req_size = CIK_MEC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) rlc_req_size = KB_RLC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) num_fw = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) case CHIP_MULLINS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) chip_name = "MULLINS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) new_chip_name = "mullins";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) me_req_size = CIK_ME_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ce_req_size = CIK_CE_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) mec_req_size = CIK_MEC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) rlc_req_size = ML_RLC_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) num_fw = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) default: BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) DRM_INFO("Loading %s Microcode\n", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (rdev->pfp_fw->size != pfp_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) rdev->pfp_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) err = radeon_ucode_validate(rdev->pfp_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (rdev->me_fw->size != me_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) rdev->me_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) err = radeon_ucode_validate(rdev->me_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (rdev->ce_fw->size != ce_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) rdev->ce_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) err = radeon_ucode_validate(rdev->ce_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (rdev->mec_fw->size != mec_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) rdev->mec_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) err = radeon_ucode_validate(rdev->mec_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (rdev->family == CHIP_KAVERI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) err = radeon_ucode_validate(rdev->mec2_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (rdev->rlc_fw->size != rlc_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) pr_err("cik_rlc: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) rdev->rlc_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) err = radeon_ucode_validate(rdev->rlc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (rdev->sdma_fw->size != sdma_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) pr_err("cik_sdma: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) rdev->sdma_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) err = radeon_ucode_validate(rdev->sdma_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* No SMC, MC ucode on APUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (!(rdev->flags & RADEON_IS_IGP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if ((rdev->mc_fw->size != mc_req_size) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) (rdev->mc_fw->size != mc2_req_size)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) pr_err("cik_mc: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) rdev->mc_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) err = radeon_ucode_validate(rdev->mc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (new_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) pr_err("smc: error loading firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) release_firmware(rdev->smc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) rdev->smc_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) } else if (rdev->smc_fw->size != smc_req_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) pr_err("cik_smc: Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) rdev->smc_fw->size, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) err = radeon_ucode_validate(rdev->smc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) pr_err("cik_fw: validation failed for firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) new_fw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (new_fw == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) rdev->new_fw = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) } else if (new_fw < num_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) pr_err("ci_fw: mixing new and old firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) rdev->new_fw = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (err != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) pr_err("cik_cp: Failed to load firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) release_firmware(rdev->pfp_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) rdev->pfp_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) release_firmware(rdev->me_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) rdev->me_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) release_firmware(rdev->ce_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) rdev->ce_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) release_firmware(rdev->mec_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) rdev->mec_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) release_firmware(rdev->mec2_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) rdev->mec2_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) release_firmware(rdev->rlc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rdev->rlc_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) release_firmware(rdev->sdma_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) rdev->sdma_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) release_firmware(rdev->mc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) rdev->mc_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) release_firmware(rdev->smc_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) rdev->smc_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) * Core functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) * cik_tiling_mode_table_init - init the hw tiling table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * Starting with SI, the tiling setup is done globally in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) * set of 32 tiling modes. Rather than selecting each set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * parameters per surface as on older asics, we just select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) * which index in the tiling table we want to use, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * surface uses those parameters (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static void cik_tiling_mode_table_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) u32 *tile = rdev->config.cik.tile_mode_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) u32 *macrotile = rdev->config.cik.macrotile_mode_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) const u32 num_tile_mode_states =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ARRAY_SIZE(rdev->config.cik.tile_mode_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) const u32 num_secondary_tile_mode_states =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) u32 reg_offset, split_equal_to_row_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) u32 num_pipe_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) u32 num_rbs = rdev->config.cik.max_backends_per_se *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) rdev->config.cik.max_shader_engines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) switch (rdev->config.cik.mem_row_size_in_kb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) num_pipe_configs = rdev->config.cik.max_tile_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (num_pipe_configs > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) num_pipe_configs = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) tile[reg_offset] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) macrotile[reg_offset] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) switch(num_pipe_configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) NUM_BANKS(ADDR_SURF_2_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) NUM_BANKS(ADDR_SURF_2_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) NUM_BANKS(ADDR_SURF_2_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) NUM_BANKS(ADDR_SURF_2_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) NUM_BANKS(ADDR_SURF_2_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (num_rbs == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) PIPE_CONFIG(ADDR_SURF_P4_16x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) PIPE_CONFIG(ADDR_SURF_P4_16x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) } else if (num_rbs < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) PIPE_CONFIG(ADDR_SURF_P4_8x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) PIPE_CONFIG(ADDR_SURF_P4_8x16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) NUM_BANKS(ADDR_SURF_4_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) TILE_SPLIT(split_equal_to_row_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) PIPE_CONFIG(ADDR_SURF_P2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) PIPE_CONFIG(ADDR_SURF_P2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) PIPE_CONFIG(ADDR_SURF_P2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) PIPE_CONFIG(ADDR_SURF_P2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) NUM_BANKS(ADDR_SURF_16_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) NUM_BANKS(ADDR_SURF_8_BANK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) * cik_select_se_sh - select which SE, SH to address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) * @se_num: shader engine to address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) * @sh_num: sh block to address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) * Select which SE, SH combinations to address. Certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) * registers are instanced per SE or SH. 0xffffffff means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) * broadcast to all SEs or SHs (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) static void cik_select_se_sh(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) u32 se_num, u32 sh_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) u32 data = INSTANCE_BROADCAST_WRITES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) else if (se_num == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) else if (sh_num == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) WREG32(GRBM_GFX_INDEX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * cik_create_bitmask - create a bitmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) * @bit_width: length of the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) * create a variable length bit mask (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) * Returns the bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) static u32 cik_create_bitmask(u32 bit_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) u32 i, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) for (i = 0; i < bit_width; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) mask |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) * cik_get_rb_disabled - computes the mask of disabled RBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * @max_rb_num: max RBs (render backends) for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * @se_num: number of SEs (shader engines) for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * @sh_per_se: number of SH blocks per SE for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) * Calculates the bitmask of disabled RBs (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) * Returns the disabled RB bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) static u32 cik_get_rb_disabled(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) u32 max_rb_num_per_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) u32 sh_per_se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) u32 data, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) data = RREG32(CC_RB_BACKEND_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) if (data & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) data &= BACKEND_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) data >>= BACKEND_DISABLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) return data & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) * cik_setup_rb - setup the RBs on the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) * @se_num: number of SEs (shader engines) for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) * @sh_per_se: number of SH blocks per SE for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) * @max_rb_num: max RBs (render backends) for the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) * Configures per-SE/SH RB registers (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static void cik_setup_rb(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) u32 se_num, u32 sh_per_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) u32 max_rb_num_per_se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) u32 data, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) u32 disabled_rbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) u32 enabled_rbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) for (i = 0; i < se_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) for (j = 0; j < sh_per_se; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) cik_select_se_sh(rdev, i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (rdev->family == CHIP_HAWAII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) for (i = 0; i < max_rb_num_per_se * se_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (!(disabled_rbs & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) enabled_rbs |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) rdev->config.cik.backend_enable_mask = enabled_rbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) for (i = 0; i < se_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) cik_select_se_sh(rdev, i, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) for (j = 0; j < sh_per_se; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) switch (enabled_rbs & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) if (j == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) enabled_rbs >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) WREG32(PA_SC_RASTER_CONFIG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) * cik_gpu_init - setup the 3D engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) * Configures the 3D engine and tiling configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) * registers so that the 3D engine is usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) static void cik_gpu_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) u32 mc_shared_chmap, mc_arb_ramcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) u32 hdp_host_path_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) rdev->config.cik.max_shader_engines = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) rdev->config.cik.max_tile_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) rdev->config.cik.max_cu_per_sh = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) rdev->config.cik.max_sh_per_se = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) rdev->config.cik.max_backends_per_se = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) rdev->config.cik.max_texture_channel_caches = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) rdev->config.cik.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) rdev->config.cik.max_gs_threads = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) rdev->config.cik.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) rdev->config.cik.max_shader_engines = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) rdev->config.cik.max_tile_pipes = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) rdev->config.cik.max_cu_per_sh = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) rdev->config.cik.max_sh_per_se = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) rdev->config.cik.max_backends_per_se = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) rdev->config.cik.max_texture_channel_caches = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) rdev->config.cik.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) rdev->config.cik.max_gs_threads = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) rdev->config.cik.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) case CHIP_KAVERI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) rdev->config.cik.max_shader_engines = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) rdev->config.cik.max_tile_pipes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) rdev->config.cik.max_cu_per_sh = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) rdev->config.cik.max_backends_per_se = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) rdev->config.cik.max_sh_per_se = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) rdev->config.cik.max_texture_channel_caches = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) rdev->config.cik.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) rdev->config.cik.max_gs_threads = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) rdev->config.cik.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) case CHIP_KABINI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) case CHIP_MULLINS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) rdev->config.cik.max_shader_engines = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) rdev->config.cik.max_tile_pipes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) rdev->config.cik.max_cu_per_sh = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) rdev->config.cik.max_sh_per_se = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) rdev->config.cik.max_backends_per_se = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) rdev->config.cik.max_texture_channel_caches = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) rdev->config.cik.max_gprs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) rdev->config.cik.max_gs_threads = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) rdev->config.cik.max_hw_contexts = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* Initialize HDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) for (i = 0, j = 0; i < 32; i++, j += 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) WREG32((0x2c14 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) WREG32((0x2c18 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) WREG32((0x2c1c + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) WREG32((0x2c20 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) WREG32((0x2c24 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) WREG32(SRBM_INT_CNTL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) WREG32(SRBM_INT_ACK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) rdev->config.cik.mem_max_burst_length_bytes = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) if (rdev->config.cik.mem_row_size_in_kb > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) rdev->config.cik.mem_row_size_in_kb = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) /* XXX use MC settings? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) rdev->config.cik.shader_engine_tile_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) rdev->config.cik.num_gpus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) rdev->config.cik.multi_gpu_tile_size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /* fix up row size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) gb_addr_config &= ~ROW_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) switch (rdev->config.cik.mem_row_size_in_kb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) gb_addr_config |= ROW_SIZE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) gb_addr_config |= ROW_SIZE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) gb_addr_config |= ROW_SIZE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) /* setup tiling info dword. gb_addr_config is not adequate since it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) * not have bank info, so create a custom tiling dword.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) * bits 3:0 num_pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) * bits 7:4 num_banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) * bits 11:8 group_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) * bits 15:12 row_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) rdev->config.cik.tile_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) switch (rdev->config.cik.num_tile_pipes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) rdev->config.cik.tile_config |= (0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) rdev->config.cik.tile_config |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) rdev->config.cik.tile_config |= (2 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) /* XXX what about 12? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) rdev->config.cik.tile_config |= (3 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) rdev->config.cik.tile_config |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) rdev->config.cik.tile_config |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) rdev->config.cik.tile_config |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) WREG32(GB_ADDR_CONFIG, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) WREG32(HDP_ADDR_CONFIG, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) WREG32(DMIF_ADDR_CALC, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) cik_tiling_mode_table_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) rdev->config.cik.max_sh_per_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) rdev->config.cik.max_backends_per_se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) rdev->config.cik.active_cus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) rdev->config.cik.active_cus +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) hweight32(cik_get_cu_active_bitmap(rdev, i, j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* set HW defaults for 3D engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) WREG32(SX_DEBUG_1, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) WREG32(TA_CNTL_AUX, 0x00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) tmp = RREG32(SPI_CONFIG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) tmp |= 0x03000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) WREG32(SPI_CONFIG_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) WREG32(SQ_CONFIG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) WREG32(DB_DEBUG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) tmp |= 0x00000400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) WREG32(DB_DEBUG2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) tmp |= 0x00020200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) WREG32(DB_DEBUG3, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) tmp |= 0x00018208;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) WREG32(CB_HW_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) WREG32(VGT_NUM_INSTANCES, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) WREG32(CP_PERFMON_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) WREG32(SQ_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) FORCE_EOV_MAX_REZ_CNT(255)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) AUTO_INVLD_EN(ES_AND_GS_AUTO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) WREG32(VGT_GS_VERTEX_REUSE, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) tmp = RREG32(HDP_MISC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) tmp |= HDP_FLUSH_INVALIDATE_CACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) WREG32(HDP_MISC_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) * GPU scratch registers helpers function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) * cik_scratch_init - setup driver info for CP scratch regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) * Set up the number and offset of the CP scratch registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) * NOTE: use of CP scratch registers is a legacy inferface and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) * is not used by default on newer asics (r6xx+). On newer asics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) * memory buffers are used for fences rather than scratch regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) static void cik_scratch_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) rdev->scratch.num_reg = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) rdev->scratch.reg_base = SCRATCH_REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) for (i = 0; i < rdev->scratch.num_reg; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) rdev->scratch.free[i] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) * cik_ring_test - basic gfx ring test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) * @ring: radeon_ring structure holding ring information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) * Allocate a scratch register and write to it using the gfx ring (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) * Provides a basic gfx ring test to verify that the ring is working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) * Used by cik_cp_gfx_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * Returns 0 on success, error on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) uint32_t scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) uint32_t tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) r = radeon_scratch_get(rdev, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) WREG32(scratch, 0xCAFEDEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) r = radeon_ring_lock(rdev, ring, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) radeon_ring_write(ring, 0xDEADBEEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) tmp = RREG32(scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) if (tmp == 0xDEADBEEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) if (i < rdev->usec_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) ring->idx, scratch, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) * @ridx: radeon ring index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) * Emits an hdp flush on the cp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) int ridx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) struct radeon_ring *ring = &rdev->ring[ridx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) u32 ref_and_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) switch (ring->idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) case CAYMAN_RING_TYPE_CP1_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) case CAYMAN_RING_TYPE_CP2_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) switch (ring->me) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) ref_and_mask = CP2 << ring->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) ref_and_mask = CP6 << ring->pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) case RADEON_RING_TYPE_GFX_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) ref_and_mask = CP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) WAIT_REG_MEM_FUNCTION(3) | /* == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) WAIT_REG_MEM_ENGINE(1))); /* pfp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) radeon_ring_write(ring, ref_and_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) radeon_ring_write(ring, ref_and_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) radeon_ring_write(ring, 0x20); /* poll interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) * @fence: radeon fence object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) * Emits a fence sequnce number on the gfx ring and flushes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) * GPU caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) struct radeon_fence *fence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) struct radeon_ring *ring = &rdev->ring[fence->ring];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) /* Workaround for cache flush problems. First send a dummy EOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) * event down the pipe with seq one below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) EOP_TC_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) EVENT_INDEX(5)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) radeon_ring_write(ring, addr & 0xfffffffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) DATA_SEL(1) | INT_SEL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) radeon_ring_write(ring, fence->seq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) /* Then send the real EOP event down the pipe. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) EOP_TC_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) EVENT_INDEX(5)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) radeon_ring_write(ring, addr & 0xfffffffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) radeon_ring_write(ring, fence->seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) * cik_fence_compute_ring_emit - emit a fence on the compute ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) * @fence: radeon fence object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) * Emits a fence sequnce number on the compute ring and flushes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) * GPU caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) void cik_fence_compute_ring_emit(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) struct radeon_fence *fence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) struct radeon_ring *ring = &rdev->ring[fence->ring];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* RELEASE_MEM - flush caches, send int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) EOP_TC_ACTION_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) EVENT_INDEX(5)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) radeon_ring_write(ring, addr & 0xfffffffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) radeon_ring_write(ring, upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) radeon_ring_write(ring, fence->seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) * cik_semaphore_ring_emit - emit a semaphore on the CP ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) * @ring: radeon ring buffer object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) * @semaphore: radeon semaphore object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) * @emit_wait: Is this a sempahore wait?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) * from running ahead of semaphore waits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) bool cik_semaphore_ring_emit(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) struct radeon_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) struct radeon_semaphore *semaphore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) bool emit_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) uint64_t addr = semaphore->gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) radeon_ring_write(ring, lower_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /* Prevent the PFP from running ahead of the semaphore wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) radeon_ring_write(ring, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) * cik_copy_cpdma - copy pages using the CP DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) * @src_offset: src GPU address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) * @dst_offset: dst GPU address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) * @num_gpu_pages: number of GPU pages to xfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) * @resv: reservation object to sync to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) * Copy GPU paging using the CP DMA engine (CIK+).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) * Used by the radeon ttm implementation to move pages if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) * registered as the asic copy callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) uint64_t src_offset, uint64_t dst_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) unsigned num_gpu_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) struct dma_resv *resv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) struct radeon_fence *fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) struct radeon_sync sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) int ring_index = rdev->asic->copy.blit_ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) struct radeon_ring *ring = &rdev->ring[ring_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) u32 size_in_bytes, cur_size_in_bytes, control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) int i, num_loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) radeon_sync_create(&sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) DRM_ERROR("radeon: moving bo (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) radeon_sync_free(rdev, &sync, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) return ERR_PTR(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) radeon_sync_resv(rdev, &sync, resv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) radeon_sync_rings(rdev, &sync, ring->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) for (i = 0; i < num_loops; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) cur_size_in_bytes = size_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if (cur_size_in_bytes > 0x1fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) cur_size_in_bytes = 0x1fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) size_in_bytes -= cur_size_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) if (size_in_bytes == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) control |= PACKET3_DMA_DATA_CP_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) radeon_ring_write(ring, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) radeon_ring_write(ring, lower_32_bits(src_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) radeon_ring_write(ring, upper_32_bits(src_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) radeon_ring_write(ring, lower_32_bits(dst_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) radeon_ring_write(ring, upper_32_bits(dst_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) radeon_ring_write(ring, cur_size_in_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) src_offset += cur_size_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) dst_offset += cur_size_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) r = radeon_fence_emit(rdev, &fence, ring->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) radeon_ring_unlock_undo(rdev, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) radeon_sync_free(rdev, &sync, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) return ERR_PTR(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) radeon_sync_free(rdev, &sync, fence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) return fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) * IB stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) * @ib: radeon indirect buffer object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) * Emits a DE (drawing engine) or CE (constant engine) IB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) * on the gfx ring. IBs are usually generated by userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) * acceleration drivers and submitted to the kernel for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) * scheduling on the ring. This function schedules the IB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) * on the gfx ring for execution by the GPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) struct radeon_ring *ring = &rdev->ring[ib->ring];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) u32 header, control = INDIRECT_BUFFER_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) if (ib->is_const_ib) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) /* set switch buffer packet before const IB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) u32 next_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) if (ring->rptr_save_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) next_rptr = ring->wptr + 3 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) radeon_ring_write(ring, ((ring->rptr_save_reg -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) PACKET3_SET_UCONFIG_REG_START) >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) radeon_ring_write(ring, next_rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) } else if (rdev->wb.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) next_rptr = ring->wptr + 5 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) radeon_ring_write(ring, next_rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) control |= ib->length_dw | (vm_id << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) radeon_ring_write(ring, header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) radeon_ring_write(ring, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) * cik_ib_test - basic gfx ring IB test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) * @ring: radeon_ring structure holding ring information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) * Allocate an IB and execute it on the gfx ring (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) * Provides a basic gfx ring test to verify that IBs are working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) * Returns 0 on success, error on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) struct radeon_ib ib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) uint32_t scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) uint32_t tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) r = radeon_scratch_get(rdev, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) WREG32(scratch, 0xCAFEDEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) DRM_ERROR("radeon: failed to get ib (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) ib.ptr[2] = 0xDEADBEEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) ib.length_dw = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) r = radeon_ib_schedule(rdev, &ib, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) radeon_ib_free(rdev, &ib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) RADEON_USEC_IB_TEST_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) DRM_ERROR("radeon: fence wait failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) radeon_ib_free(rdev, &ib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) } else if (r == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) DRM_ERROR("radeon: fence wait timed out.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) radeon_ib_free(rdev, &ib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) tmp = RREG32(scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) if (tmp == 0xDEADBEEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) if (i < rdev->usec_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) scratch, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) radeon_scratch_free(rdev, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) radeon_ib_free(rdev, &ib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) * CP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * On CIK, gfx and compute now have independant command processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) * GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) * Gfx consists of a single ring and can process both gfx jobs and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) * compute jobs. The gfx CP consists of three microengines (ME):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) * PFP - Pre-Fetch Parser
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) * ME - Micro Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) * CE - Constant Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) * The PFP and ME make up what is considered the Drawing Engine (DE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) * The CE is an asynchronous engine used for updating buffer desciptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) * used by the DE so that they can be loaded into cache in parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) * while the DE is processing state update packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) * Compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) * The compute CP consists of two microengines (ME):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) * MEC1 - Compute MicroEngine 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) * MEC2 - Compute MicroEngine 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) * The queues are exposed to userspace and are programmed directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) * by the compute runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) * cik_cp_gfx_enable - enable/disable the gfx CP MEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) * @enable: enable or disable the MEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) * Halts or unhalts the gfx MEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) WREG32(CP_ME_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) * Loads the gfx PFP, ME, and CE ucode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) * Returns 0 for success, -EINVAL if the ucode is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) cik_cp_gfx_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) const struct gfx_firmware_header_v1_0 *pfp_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) const struct gfx_firmware_header_v1_0 *ce_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) const struct gfx_firmware_header_v1_0 *me_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) const __le32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) u32 fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) radeon_ucode_print_gfx_hdr(&ce_hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) radeon_ucode_print_gfx_hdr(&me_hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) /* PFP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) for (i = 0; i < fw_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) /* CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) WREG32(CP_CE_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) for (i = 0; i < fw_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) /* ME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) fw_data = (const __be32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) WREG32(CP_ME_RAM_WADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) for (i = 0; i < fw_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) const __be32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) /* PFP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) fw_data = (const __be32 *)rdev->pfp_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) WREG32(CP_PFP_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) /* CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) fw_data = (const __be32 *)rdev->ce_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) WREG32(CP_CE_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) WREG32(CP_CE_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) /* ME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) fw_data = (const __be32 *)rdev->me_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) WREG32(CP_ME_RAM_WADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) WREG32(CP_ME_RAM_WADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) * cik_cp_gfx_start - start the gfx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) * Enables the ring and loads the clear state context and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) * packets required to init the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) static int cik_cp_gfx_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) /* init the CP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) WREG32(CP_ENDIAN_SWAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) WREG32(CP_DEVICE_ID, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) cik_cp_gfx_enable(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) /* init the CE partitions. CE only used for gfx on CIK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) radeon_ring_write(ring, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) radeon_ring_write(ring, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) /* setup clear context state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) radeon_ring_write(ring, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) radeon_ring_write(ring, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) for (i = 0; i < cik_default_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) radeon_ring_write(ring, cik_default_state[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) /* set clear context state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) radeon_ring_write(ring, 0x00000316);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) radeon_ring_unlock_commit(rdev, ring, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) * cik_cp_gfx_fini - stop the gfx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) * Stop the gfx ring and tear down the driver ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) * info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) static void cik_cp_gfx_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) cik_cp_gfx_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) * cik_cp_gfx_resume - setup the gfx ring buffer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) * Program the location and size of the gfx ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) * and test it to make sure it's working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) static int cik_cp_gfx_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) u32 rb_bufsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) u64 rb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) WREG32(CP_SEM_WAIT_TIMER, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) if (rdev->family != CHIP_HAWAII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) /* Set the write pointer delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) WREG32(CP_RB_WPTR_DELAY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) /* set the RB to use vmid 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) WREG32(CP_RB_VMID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) /* ring 0 - compute and gfx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) /* Set ring buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) rb_bufsz = order_base_2(ring->ring_size / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) tmp |= BUF_SWAP_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) WREG32(CP_RB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) /* Initialize the ring buffer's read and write pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) ring->wptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) WREG32(CP_RB0_WPTR, ring->wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) /* set the wb address wether it's enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) /* scratch register shadowing is no longer supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) WREG32(SCRATCH_UMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) if (!rdev->wb.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) tmp |= RB_NO_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) WREG32(CP_RB0_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) rb_addr = ring->gpu_addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) WREG32(CP_RB0_BASE, rb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) /* start the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) cik_cp_gfx_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) u32 cik_gfx_get_rptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) u32 rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) if (rdev->wb.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) rptr = rdev->wb.wb[ring->rptr_offs/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) rptr = RREG32(CP_RB0_RPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) return rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) u32 cik_gfx_get_wptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) return RREG32(CP_RB0_WPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) void cik_gfx_set_wptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) WREG32(CP_RB0_WPTR, ring->wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) (void)RREG32(CP_RB0_WPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) u32 cik_compute_get_rptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) u32 rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) if (rdev->wb.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) rptr = rdev->wb.wb[ring->rptr_offs/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) rptr = RREG32(CP_HQD_PQ_RPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) return rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) u32 cik_compute_get_wptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) u32 wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) if (rdev->wb.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) /* XXX check if swapping is necessary on BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) wptr = rdev->wb.wb[ring->wptr_offs/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) wptr = RREG32(CP_HQD_PQ_WPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) return wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) void cik_compute_set_wptr(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) /* XXX check if swapping is necessary on BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) WDOORBELL32(ring->doorbell_index, ring->wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) static void cik_compute_stop(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) u32 j, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) /* Disable wptr polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) tmp &= ~WPTR_POLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) /* Disable HQD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) if (RREG32(CP_HQD_ACTIVE) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) for (j = 0; j < rdev->usec_timeout; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) if (!(RREG32(CP_HQD_ACTIVE) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) WREG32(CP_HQD_PQ_RPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) WREG32(CP_HQD_PQ_WPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) * cik_cp_compute_enable - enable/disable the compute CP MEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) * @enable: enable or disable the MEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) * Halts or unhalts the compute MEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) WREG32(CP_MEC_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) * To make hibernation reliable we need to clear compute ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) * configuration before halting the compute ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) * cik_cp_compute_load_microcode - load the compute CP ME ucode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) * Loads the compute MEC1&2 ucode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) * Returns 0 for success, -EINVAL if the ucode is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) if (!rdev->mec_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) cik_cp_compute_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) const struct gfx_firmware_header_v1_0 *mec_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) const __le32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) u32 fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) radeon_ucode_print_gfx_hdr(&mec_hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) /* MEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) for (i = 0; i < fw_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) /* MEC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) if (rdev->family == CHIP_KAVERI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) const struct gfx_firmware_header_v1_0 *mec2_hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) (rdev->mec2_fw->data +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) for (i = 0; i < fw_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) const __be32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) /* MEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) fw_data = (const __be32 *)rdev->mec_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) if (rdev->family == CHIP_KAVERI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) /* MEC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) fw_data = (const __be32 *)rdev->mec_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) * cik_cp_compute_start - start the compute queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) * Enable the compute queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) static int cik_cp_compute_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) cik_cp_compute_enable(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) * cik_cp_compute_fini - stop the compute queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) * Stop the compute queues and tear down the driver queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) * info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) static void cik_cp_compute_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) int i, idx, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) cik_cp_compute_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) idx = CAYMAN_RING_TYPE_CP1_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) idx = CAYMAN_RING_TYPE_CP2_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) if (rdev->ring[idx].mqd_obj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) if (unlikely(r != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) radeon_bo_unpin(rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) radeon_bo_unref(&rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) rdev->ring[idx].mqd_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) static void cik_mec_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) if (rdev->mec.hpd_eop_obj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) if (unlikely(r != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) radeon_bo_unpin(rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) radeon_bo_unref(&rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) rdev->mec.hpd_eop_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) #define MEC_HPD_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) static int cik_mec_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) u32 *hpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) if (rdev->family == CHIP_KAVERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) rdev->mec.num_mec = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) rdev->mec.num_mec = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) rdev->mec.num_pipe = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) if (rdev->mec.hpd_eop_obj == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) r = radeon_bo_create(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) PAGE_SIZE, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) &rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) if (unlikely(r != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) cik_mec_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) &rdev->mec.hpd_eop_gpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) cik_mec_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) cik_mec_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) /* clear memory. Not sure if this is required or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) struct hqd_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) u32 cp_mqd_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) u32 cp_mqd_base_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) u32 cp_hqd_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) u32 cp_hqd_vmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) u32 cp_hqd_persistent_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) u32 cp_hqd_pipe_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) u32 cp_hqd_queue_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) u32 cp_hqd_quantum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) u32 cp_hqd_pq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) u32 cp_hqd_pq_base_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) u32 cp_hqd_pq_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) u32 cp_hqd_pq_rptr_report_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) u32 cp_hqd_pq_rptr_report_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) u32 cp_hqd_pq_wptr_poll_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) u32 cp_hqd_pq_wptr_poll_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) u32 cp_hqd_pq_doorbell_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) u32 cp_hqd_pq_wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) u32 cp_hqd_pq_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) u32 cp_hqd_ib_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) u32 cp_hqd_ib_base_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) u32 cp_hqd_ib_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) u32 cp_hqd_ib_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) u32 cp_hqd_iq_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) u32 cp_hqd_iq_rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) u32 cp_hqd_dequeue_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) u32 cp_hqd_dma_offload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) u32 cp_hqd_sema_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) u32 cp_hqd_msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) u32 cp_hqd_atomic0_preop_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) u32 cp_hqd_atomic0_preop_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) u32 cp_hqd_atomic1_preop_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) u32 cp_hqd_atomic1_preop_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) u32 cp_hqd_hq_scheduler0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) u32 cp_hqd_hq_scheduler1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) u32 cp_mqd_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) struct bonaire_mqd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) u32 dispatch_initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) u32 dimensions[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) u32 start_idx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) u32 num_threads[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) u32 pipeline_stat_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) u32 perf_counter_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) u32 pgm[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) u32 tba[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) u32 tma[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) u32 pgm_rsrc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) u32 vmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) u32 resource_limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) u32 static_thread_mgmt01[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) u32 tmp_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) u32 static_thread_mgmt23[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) u32 restart[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) u32 thread_trace_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) u32 user_data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) u32 vgtcs_invoke_count[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) struct hqd_registers queue_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) u32 dequeue_cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) u32 interrupt_queue[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) * cik_cp_compute_resume - setup the compute queue registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) * Program the compute queues and test them to make sure they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) * are working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) static int cik_cp_compute_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) int r, i, j, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) bool use_doorbell = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) u64 hqd_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) u64 mqd_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) u64 eop_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) u64 wb_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) struct bonaire_mqd *mqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) r = cik_cp_compute_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) /* fix up chicken bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) tmp = RREG32(CP_CPF_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) tmp |= (1 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) WREG32(CP_CPF_DEBUG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) /* init the pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) int me = (i < 4) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) int pipe = (i < 4) ? i : (i - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) cik_srbm_select(rdev, me, pipe, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) /* write the EOP addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) /* set the VMID assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) WREG32(CP_HPD_EOP_VMID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) tmp = RREG32(CP_HPD_EOP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) tmp &= ~EOP_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) tmp |= order_base_2(MEC_HPD_SIZE / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) WREG32(CP_HPD_EOP_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) /* init the queues. Just two for now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) idx = CAYMAN_RING_TYPE_CP1_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) idx = CAYMAN_RING_TYPE_CP2_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) if (rdev->ring[idx].mqd_obj == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) r = radeon_bo_create(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) sizeof(struct bonaire_mqd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) PAGE_SIZE, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) RADEON_GEM_DOMAIN_GTT, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) NULL, &rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) if (unlikely(r != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) cik_cp_compute_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) &mqd_gpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) cik_cp_compute_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) cik_cp_compute_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) /* init the mqd struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) memset(buf, 0, sizeof(struct bonaire_mqd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) mqd = (struct bonaire_mqd *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) mqd->header = 0xC0310800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) mqd->static_thread_mgmt01[0] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) mqd->static_thread_mgmt01[1] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) mqd->static_thread_mgmt23[0] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) mqd->static_thread_mgmt23[1] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) cik_srbm_select(rdev, rdev->ring[idx].me,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) rdev->ring[idx].pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) rdev->ring[idx].queue, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) /* disable wptr polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) tmp &= ~WPTR_POLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) /* enable doorbell? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) mqd->queue_state.cp_hqd_pq_doorbell_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) if (use_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) mqd->queue_state.cp_hqd_pq_doorbell_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) /* disable the queue if it's active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) mqd->queue_state.cp_hqd_dequeue_request = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) mqd->queue_state.cp_hqd_pq_rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) mqd->queue_state.cp_hqd_pq_wptr= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) if (RREG32(CP_HQD_ACTIVE) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) for (j = 0; j < rdev->usec_timeout; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) if (!(RREG32(CP_HQD_ACTIVE) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) /* set the pointer to the MQD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) /* set MQD vmid to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) /* set up the HQD, this is similar to CP_RB0_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) mqd->queue_state.cp_hqd_pq_control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) ~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) mqd->queue_state.cp_hqd_pq_control |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) order_base_2(rdev->ring[idx].ring_size / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) mqd->queue_state.cp_hqd_pq_control |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) mqd->queue_state.cp_hqd_pq_control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) ~(UNORD_DISPATCH | ROQ_PQ_IB_FLIP | PQ_VOLATILE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) mqd->queue_state.cp_hqd_pq_control |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) /* set the wb address wether it's enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) upper_32_bits(wb_gpu_addr) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) mqd->queue_state.cp_hqd_pq_rptr_report_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) /* enable the doorbell if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) if (use_doorbell) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) mqd->queue_state.cp_hqd_pq_doorbell_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) mqd->queue_state.cp_hqd_pq_doorbell_control |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) DOORBELL_OFFSET(rdev->ring[idx].doorbell_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) mqd->queue_state.cp_hqd_pq_doorbell_control &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) ~(DOORBELL_SOURCE | DOORBELL_HIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) mqd->queue_state.cp_hqd_pq_doorbell_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) rdev->ring[idx].wptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) /* set the vmid for the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) mqd->queue_state.cp_hqd_vmid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) /* activate the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) mqd->queue_state.cp_hqd_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) rdev->ring[idx].ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) r = radeon_ring_test(rdev, idx, &rdev->ring[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) rdev->ring[idx].ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) static void cik_cp_enable(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) cik_cp_gfx_enable(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) cik_cp_compute_enable(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) static int cik_cp_load_microcode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) r = cik_cp_gfx_load_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) r = cik_cp_compute_load_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) static void cik_cp_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) cik_cp_gfx_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) cik_cp_compute_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) static int cik_cp_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) cik_enable_gui_idle_interrupt(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) r = cik_cp_load_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) r = cik_cp_gfx_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) r = cik_cp_compute_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) cik_enable_gui_idle_interrupt(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) static void cik_print_gpu_status_regs(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) RREG32(GRBM_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) RREG32(GRBM_STATUS2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) RREG32(GRBM_STATUS_SE0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) RREG32(GRBM_STATUS_SE1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) RREG32(GRBM_STATUS_SE2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) RREG32(GRBM_STATUS_SE3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) RREG32(SRBM_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) RREG32(SRBM_STATUS2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) dev_info(rdev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) RREG32(CP_STALLED_STAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) dev_info(rdev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) RREG32(CP_STALLED_STAT2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) dev_info(rdev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) RREG32(CP_STALLED_STAT3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) dev_info(rdev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) RREG32(CP_CPF_BUSY_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) dev_info(rdev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) RREG32(CP_CPF_STALLED_STAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) dev_info(rdev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) RREG32(CP_CPC_STALLED_STAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) * cik_gpu_check_soft_reset - check which blocks are busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) * Check which blocks are busy and return the relevant reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) * mask to be used by cik_gpu_soft_reset().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) * Returns a mask of the blocks to be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) u32 reset_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) /* GRBM_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) tmp = RREG32(GRBM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) if (tmp & (PA_BUSY | SC_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) BCI_BUSY | SX_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) TA_BUSY | VGT_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) DB_BUSY | CB_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) GDS_BUSY | SPI_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) IA_BUSY | IA_BUSY_NO_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) reset_mask |= RADEON_RESET_GFX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) reset_mask |= RADEON_RESET_CP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) /* GRBM_STATUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) tmp = RREG32(GRBM_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) if (tmp & RLC_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) reset_mask |= RADEON_RESET_RLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) /* SDMA0_STATUS_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) if (!(tmp & SDMA_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) reset_mask |= RADEON_RESET_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) /* SDMA1_STATUS_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) if (!(tmp & SDMA_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) reset_mask |= RADEON_RESET_DMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) /* SRBM_STATUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) tmp = RREG32(SRBM_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) if (tmp & SDMA_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) reset_mask |= RADEON_RESET_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) if (tmp & SDMA1_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) reset_mask |= RADEON_RESET_DMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) /* SRBM_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) tmp = RREG32(SRBM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) if (tmp & IH_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) reset_mask |= RADEON_RESET_IH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) if (tmp & SEM_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) reset_mask |= RADEON_RESET_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) if (tmp & GRBM_RQ_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) reset_mask |= RADEON_RESET_GRBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) if (tmp & VMC_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) reset_mask |= RADEON_RESET_VMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) MCC_BUSY | MCD_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) reset_mask |= RADEON_RESET_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) if (evergreen_is_display_hung(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) reset_mask |= RADEON_RESET_DISPLAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) /* Skip MC reset as it's mostly likely not hung, just busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) if (reset_mask & RADEON_RESET_MC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) reset_mask &= ~RADEON_RESET_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) return reset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) * cik_gpu_soft_reset - soft reset GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) * @reset_mask: mask of which blocks to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) * Soft reset the blocks specified in @reset_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) struct evergreen_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) if (reset_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) cik_print_gpu_status_regs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) /* disable CG/PG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) cik_fini_pg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) cik_fini_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) /* stop the rlc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) cik_rlc_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) /* Disable GFX parsing/prefetching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) /* Disable MEC parsing/prefetching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) if (reset_mask & RADEON_RESET_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) /* sdma0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) tmp |= SDMA_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) if (reset_mask & RADEON_RESET_DMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) /* sdma1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) tmp |= SDMA_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) evergreen_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) if (evergreen_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) if (reset_mask & RADEON_RESET_CP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) grbm_soft_reset |= SOFT_RESET_CP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) srbm_soft_reset |= SOFT_RESET_GRBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) if (reset_mask & RADEON_RESET_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) srbm_soft_reset |= SOFT_RESET_SDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) if (reset_mask & RADEON_RESET_DMA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) srbm_soft_reset |= SOFT_RESET_SDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) if (reset_mask & RADEON_RESET_DISPLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) srbm_soft_reset |= SOFT_RESET_DC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) if (reset_mask & RADEON_RESET_RLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) grbm_soft_reset |= SOFT_RESET_RLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) if (reset_mask & RADEON_RESET_SEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) srbm_soft_reset |= SOFT_RESET_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) if (reset_mask & RADEON_RESET_IH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) srbm_soft_reset |= SOFT_RESET_IH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) if (reset_mask & RADEON_RESET_GRBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) srbm_soft_reset |= SOFT_RESET_GRBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) if (reset_mask & RADEON_RESET_VMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) srbm_soft_reset |= SOFT_RESET_VMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) if (!(rdev->flags & RADEON_IS_IGP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) if (reset_mask & RADEON_RESET_MC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) srbm_soft_reset |= SOFT_RESET_MC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) if (grbm_soft_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) tmp = RREG32(GRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) tmp |= grbm_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) WREG32(GRBM_SOFT_RESET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) tmp = RREG32(GRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) tmp &= ~grbm_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) WREG32(GRBM_SOFT_RESET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) tmp = RREG32(GRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) if (srbm_soft_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) tmp = RREG32(SRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) tmp |= srbm_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) WREG32(SRBM_SOFT_RESET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) tmp = RREG32(SRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) tmp &= ~srbm_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) WREG32(SRBM_SOFT_RESET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) tmp = RREG32(SRBM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) /* Wait a little for things to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) evergreen_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) cik_print_gpu_status_regs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) struct kv_reset_save_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) u32 gmcon_reng_execute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) u32 gmcon_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) u32 gmcon_misc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) static void kv_save_regs_for_reset(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) struct kv_reset_save_regs *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) save->gmcon_misc = RREG32(GMCON_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) save->gmcon_misc3 = RREG32(GMCON_MISC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) STCTRL_STUTTER_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) static void kv_restore_regs_for_reset(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) struct kv_reset_save_regs *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) WREG32(GMCON_PGFSM_WRITE, 0x210000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) WREG32(GMCON_PGFSM_WRITE, 0x21003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) WREG32(GMCON_PGFSM_WRITE, 0x2b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) WREG32(GMCON_PGFSM_WRITE, 0x420000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) WREG32(GMCON_PGFSM_WRITE, 0x120202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) WREG32(GMCON_PGFSM_WRITE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) WREG32(GMCON_MISC3, save->gmcon_misc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) WREG32(GMCON_MISC, save->gmcon_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) struct evergreen_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) struct kv_reset_save_regs kv_save = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) u32 tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) dev_info(rdev->dev, "GPU pci config reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) /* disable dpm? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) /* disable cg/pg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) cik_fini_pg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) cik_fini_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) /* Disable GFX parsing/prefetching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) /* Disable MEC parsing/prefetching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) /* sdma0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) tmp |= SDMA_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) /* sdma1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) tmp |= SDMA_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) /* XXX other engines? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) /* halt the rlc, disable cp internal ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) cik_rlc_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) /* disable mem access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) evergreen_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) if (evergreen_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) kv_save_regs_for_reset(rdev, &kv_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) /* disable BM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) pci_clear_master(rdev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) radeon_pci_config_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) /* wait for asic to come out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) /* does asic init need to be run first??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) kv_restore_regs_for_reset(rdev, &kv_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) * cik_asic_reset - soft reset GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) * @hard: force hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) * Look up which blocks are hung and attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) * to reset them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) int cik_asic_reset(struct radeon_device *rdev, bool hard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) u32 reset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) if (hard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) cik_gpu_pci_config_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) reset_mask = cik_gpu_check_soft_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) if (reset_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) r600_set_bios_scratch_engine_hung(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) /* try soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) cik_gpu_soft_reset(rdev, reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) reset_mask = cik_gpu_check_soft_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) /* try pci config reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) if (reset_mask && radeon_hard_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) cik_gpu_pci_config_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) reset_mask = cik_gpu_check_soft_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) if (!reset_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) r600_set_bios_scratch_engine_hung(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) * cik_gfx_is_lockup - check if the 3D engine is locked up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) * @ring: radeon_ring structure holding ring information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) * Check if the 3D engine is locked up (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) * Returns true if the engine is locked, false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) u32 reset_mask = cik_gpu_check_soft_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) if (!(reset_mask & (RADEON_RESET_GFX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) RADEON_RESET_COMPUTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) RADEON_RESET_CP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) radeon_ring_lockup_update(rdev, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) return radeon_ring_test_lockup(rdev, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) /* MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) * cik_mc_program - program the GPU memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) * Set the location of vram, gart, and AGP in the GPU's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) * physical address space (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) static void cik_mc_program(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) struct evergreen_mc_save save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) /* Initialize HDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) for (i = 0, j = 0; i < 32; i++, j += 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) WREG32((0x2c14 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) WREG32((0x2c18 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) WREG32((0x2c1c + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) WREG32((0x2c20 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) WREG32((0x2c24 + j), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) evergreen_mc_stop(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) if (radeon_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) /* Lockout access through VGA aperture*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) /* Update configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) rdev->mc.vram_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) rdev->mc.vram_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) rdev->vram_scratch.gpu_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) WREG32(MC_VM_FB_LOCATION, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) /* XXX double check these! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) WREG32(MC_VM_AGP_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) if (radeon_mc_wait_for_idle(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) evergreen_mc_resume(rdev, &save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) /* we need to own VRAM, so turn off the VGA renderer here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) * to stop it overwriting our objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) rv515_vga_render_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) * cik_mc_init - initialize the memory controller driver params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) * Look up the amount of vram, vram width, and decide how to place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) * vram and gart within the GPU's physical address space (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) static int cik_mc_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) int chansize, numchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) /* Get VRAM informations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) rdev->mc.vram_is_ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) tmp = RREG32(MC_ARB_RAMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) if (tmp & CHANSIZE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) chansize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) chansize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) tmp = RREG32(MC_SHARED_CHMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) numchan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) numchan = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) numchan = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) numchan = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) numchan = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) numchan = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) numchan = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) numchan = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) numchan = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) rdev->mc.vram_width = numchan * chansize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) /* Could aper size report 0 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) /* size in MB on si */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) rdev->mc.visible_vram_size = rdev->mc.aper_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) si_vram_gtt_location(rdev, &rdev->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) radeon_update_bandwidth_info(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) * GART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) * VMID 0 is the physical GPU addresses as used by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) * VMIDs 1-15 are used for userspace clients and are handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) * by the radeon vm/hsa code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) * cik_pcie_gart_tlb_flush - gart tlb flush callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) * Flush the TLB for the VMID 0 page table (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) /* flush hdp cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) /* bits 0-15 are the VM contexts0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) WREG32(VM_INVALIDATE_REQUEST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) * cik_pcie_gart_enable - gart enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) * This sets up the TLBs, programs the page tables for VMID0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) * sets up the hw for VMIDs 1-15 which are allocated on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) * demand, and sets up the global locations for the LDS, GDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) * and GPUVM for FSA64 clients (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) * Returns 0 for success, errors for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) static int cik_pcie_gart_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) if (rdev->gart.robj == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) r = radeon_gart_table_vram_pin(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) /* Setup TLB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) WREG32(MC_VM_MX_L1_TLB_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) (0xA << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) ENABLE_L1_TLB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) ENABLE_L1_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) SYSTEM_ACCESS_MODE_NOT_IN_SYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) ENABLE_ADVANCED_DRIVER_MODEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) /* Setup L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) ENABLE_L2_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) EFFECTIVE_L2_QUEUE_SIZE(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) CONTEXT1_IDENTITY_ACCESS_MODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) BANK_SELECT(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) L2_CACHE_BIGK_FRAGMENT_SIZE(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) /* setup context0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) (u32)(rdev->dummy_page.addr >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) WREG32(VM_CONTEXT0_CNTL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) WREG32(0x15D4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) WREG32(0x15D8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) WREG32(0x15DC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) /* restore context1-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) /* set vm size, must be a multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) for (i = 1; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) if (i < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) rdev->vm_manager.saved_table_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) rdev->vm_manager.saved_table_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) /* enable context1-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) (u32)(rdev->dummy_page.addr >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) WREG32(VM_CONTEXT1_CNTL2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) READ_PROTECTION_FAULT_ENABLE_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) if (rdev->family == CHIP_KAVERI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) u32 tmp = RREG32(CHUB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) tmp &= ~BYPASS_VM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) WREG32(CHUB_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) /* XXX SH_MEM regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) /* where to put LDS, scratch, GPUVM in FSA64 space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) mutex_lock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) cik_srbm_select(rdev, 0, 0, 0, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) /* CP and shaders */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) WREG32(SH_MEM_APE1_BASE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) WREG32(SH_MEM_APE1_LIMIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) WREG32(SH_MEM_BASES, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) /* SDMA GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) /* XXX SDMA RLC - todo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) cik_srbm_select(rdev, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) mutex_unlock(&rdev->srbm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) cik_pcie_gart_tlb_flush(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) (unsigned)(rdev->mc.gtt_size >> 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) (unsigned long long)rdev->gart.table_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) rdev->gart.ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) * cik_pcie_gart_disable - gart disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) * This disables all VM page table (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) static void cik_pcie_gart_disable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) for (i = 1; i < 16; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) if (i < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) /* Disable all tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) WREG32(VM_CONTEXT0_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) WREG32(VM_CONTEXT1_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) /* Setup TLB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) /* Setup L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) WREG32(VM_L2_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) ENABLE_L2_FRAGMENT_PROCESSING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) EFFECTIVE_L2_QUEUE_SIZE(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) CONTEXT1_IDENTITY_ACCESS_MODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) WREG32(VM_L2_CNTL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) L2_CACHE_BIGK_FRAGMENT_SIZE(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) radeon_gart_table_vram_unpin(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) * cik_pcie_gart_fini - vm fini callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) * Tears down the driver GART/VM setup (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) static void cik_pcie_gart_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) cik_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) radeon_gart_table_vram_free(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) radeon_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) /* vm parser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) * cik_ib_parse - vm ib_parse callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) * @ib: indirect buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) * CIK uses hw IB checking so this is a nop (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) * vm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) * VMID 0 is the physical GPU addresses as used by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) * VMIDs 1-15 are used for userspace clients and are handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) * by the radeon vm/hsa code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) * cik_vm_init - cik vm init callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) * Inits cik specific vm parameters (number of VMs, base of vram for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) * VMIDs 1-15) (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) int cik_vm_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) * number of VMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) * VMID 0 is reserved for System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) * radeon graphics/compute will use VMIDs 1-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) rdev->vm_manager.nvm = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) /* base offset of vram pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) if (rdev->flags & RADEON_IS_IGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) u64 tmp = RREG32(MC_VM_FB_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) tmp <<= 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) rdev->vm_manager.vram_base_offset = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) rdev->vm_manager.vram_base_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) * cik_vm_fini - cik vm fini callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) * Tear down any asic specific VM setup (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) void cik_vm_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) * cik_vm_decode_fault - print human readable fault info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) * Print human readable fault information (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) static void cik_vm_decode_fault(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) u32 status, u32 addr, u32 mc_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) u32 mc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) if (rdev->family == CHIP_HAWAII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) protections, vmid, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) block, mc_client, mc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) * cik_vm_flush - cik vm flush using the CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) * Update the page table base and flush the VM TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) * using the CP (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) unsigned vm_id, uint64_t pd_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) WRITE_DATA_DST_SEL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) if (vm_id < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) radeon_ring_write(ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) radeon_ring_write(ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) radeon_ring_write(ring, pd_addr >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) /* update SH_MEM_* regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) WRITE_DATA_DST_SEL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) radeon_ring_write(ring, VMID(vm_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) WRITE_DATA_DST_SEL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) radeon_ring_write(ring, SH_MEM_BASES >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) radeon_ring_write(ring, 0); /* SH_MEM_BASES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) WRITE_DATA_DST_SEL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) radeon_ring_write(ring, VMID(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) /* HDP flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) cik_hdp_flush_cp_ring_emit(rdev, ring->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) /* bits 0-15 are the VM contexts0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) WRITE_DATA_DST_SEL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) radeon_ring_write(ring, 1 << vm_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) /* wait for the invalidate to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) WAIT_REG_MEM_FUNCTION(0) | /* always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) WAIT_REG_MEM_ENGINE(0))); /* me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) radeon_ring_write(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) radeon_ring_write(ring, 0); /* ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) radeon_ring_write(ring, 0); /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) radeon_ring_write(ring, 0x20); /* poll interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) /* compute doesn't have PFP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) if (usepfp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) /* sync PFP to ME, otherwise we might get invalid PFP reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) radeon_ring_write(ring, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) * RLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) * The RLC is a multi-purpose microengine that handles a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) * variety of functions, the most important of which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) * the interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) u32 tmp = RREG32(CP_INT_CNTL_RING0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) WREG32(CP_INT_CNTL_RING0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) tmp = RREG32(RLC_LB_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) tmp |= LOAD_BALANCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) tmp &= ~LOAD_BALANCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) WREG32(RLC_LB_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) u32 i, j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) cik_select_se_sh(rdev, i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) for (k = 0; k < rdev->usec_timeout; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) for (k = 0; k < rdev->usec_timeout; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) tmp = RREG32(RLC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) if (tmp != rlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) WREG32(RLC_CNTL, rlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) static u32 cik_halt_rlc(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) orig = data = RREG32(RLC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) if (data & RLC_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) data &= ~RLC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) WREG32(RLC_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) cik_wait_for_rlc_serdes(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) return orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) u32 tmp, i, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) WREG32(RLC_GPR_REG2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) if ((RREG32(RLC_GPM_STAT) & mask) == mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) WREG32(RLC_GPR_REG2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) * cik_rlc_stop - stop the RLC ME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) * Halt the RLC ME (MicroEngine) (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) static void cik_rlc_stop(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) WREG32(RLC_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) cik_enable_gui_idle_interrupt(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) cik_wait_for_rlc_serdes(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) * cik_rlc_start - start the RLC ME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) * Unhalt the RLC ME (MicroEngine) (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) static void cik_rlc_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) WREG32(RLC_CNTL, RLC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) cik_enable_gui_idle_interrupt(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) * cik_rlc_resume - setup the RLC hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) * Initialize the RLC registers, load the ucode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) * and start the RLC (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) * Returns 0 for success, -EINVAL if the ucode is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) static int cik_rlc_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) u32 i, size, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) if (!rdev->rlc_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) cik_rlc_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) /* disable CG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) WREG32(RLC_CGCG_CGLS_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) si_rlc_reset(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) cik_init_pg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) cik_init_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) WREG32(RLC_LB_CNTR_INIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) WREG32(RLC_LB_CNTR_MAX, 0x00008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) WREG32(RLC_LB_PARAMS, 0x00600408);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) WREG32(RLC_LB_CNTL, 0x80000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) WREG32(RLC_MC_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) WREG32(RLC_UCODE_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) const struct rlc_firmware_header_v1_0 *hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) const __le32 *fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) radeon_ucode_print_rlc_hdr(&hdr->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) WREG32(RLC_GPM_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) const __be32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) size = BONAIRE_RLC_UCODE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) case CHIP_KAVERI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) size = KV_RLC_UCODE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) case CHIP_KABINI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) size = KB_RLC_UCODE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) case CHIP_MULLINS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) size = ML_RLC_UCODE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) fw_data = (const __be32 *)rdev->rlc_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) WREG32(RLC_GPM_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) WREG32(RLC_GPM_UCODE_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) /* XXX - find out what chips support lbpw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) cik_enable_lbpw(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) if (rdev->family == CHIP_BONAIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) WREG32(RLC_DRIVER_DMA_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) cik_rlc_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) u32 data, orig, tmp, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) cik_enable_gui_idle_interrupt(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) tmp = cik_halt_rlc(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) WREG32(RLC_SERDES_WR_CTRL, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) cik_update_rlc(rdev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) data |= CGCG_EN | CGLS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) cik_enable_gui_idle_interrupt(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) RREG32(CB_CGTT_SCLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) RREG32(CB_CGTT_SCLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) RREG32(CB_CGTT_SCLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) RREG32(CB_CGTT_SCLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) data &= ~(CGCG_EN | CGLS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) WREG32(RLC_CGCG_CGLS_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) u32 data, orig, tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) orig = data = RREG32(CP_MEM_SLP_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) data |= CP_MEM_LS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) WREG32(CP_MEM_SLP_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) data |= 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) data &= 0xfffffffd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) tmp = cik_halt_rlc(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) WREG32(RLC_SERDES_WR_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) cik_update_rlc(rdev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) orig = data = RREG32(CGTS_SM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) data &= ~SM_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) data |= SM_MODE(0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) data |= SM_MODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) data &= ~CGTS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) if ((rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS_LS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) data &= ~CGTS_LS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) data &= ~ON_MONITOR_ADD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) data |= ON_MONITOR_ADD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) data |= ON_MONITOR_ADD(0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) WREG32(CGTS_SM_CTRL_REG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) data |= 0x00000003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) data = RREG32(RLC_MEM_SLP_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) if (data & RLC_MEM_LS_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) data &= ~RLC_MEM_LS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) WREG32(RLC_MEM_SLP_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) data = RREG32(CP_MEM_SLP_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) if (data & CP_MEM_LS_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) data &= ~CP_MEM_LS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) WREG32(CP_MEM_SLP_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) orig = data = RREG32(CGTS_SM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) WREG32(CGTS_SM_CTRL_REG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) tmp = cik_halt_rlc(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) WREG32(RLC_SERDES_WR_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) cik_update_rlc(rdev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) static const u32 mc_cg_registers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) MC_HUB_MISC_HUB_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) MC_HUB_MISC_SIP_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) MC_HUB_MISC_VM_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) MC_XPB_CLK_GAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) ATC_MISC_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) MC_CITF_MISC_WR_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) MC_CITF_MISC_RD_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) MC_CITF_MISC_VM_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) VM_L2_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) static void cik_enable_mc_ls(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) orig = data = RREG32(mc_cg_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) data |= MC_LS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) data &= ~MC_LS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) if (data != orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) WREG32(mc_cg_registers[i], data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) static void cik_enable_mc_mgcg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) orig = data = RREG32(mc_cg_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) data |= MC_CG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) data &= ~MC_CG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) if (data != orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) WREG32(mc_cg_registers[i], data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) data |= 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) if (data != orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) data |= 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) if (data != orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) static void cik_enable_sdma_mgls(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) data |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) data |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) data &= ~0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) data &= ~0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) data = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) orig = data = RREG32(UVD_CGC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) data |= DCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) WREG32(UVD_CGC_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) data &= ~0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) orig = data = RREG32(UVD_CGC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) data &= ~DCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) WREG32(UVD_CGC_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) static void cik_enable_bif_mgls(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) WREG32_PCIE_PORT(PCIE_CNTL2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) orig = data = RREG32(HDP_HOST_PATH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) data &= ~CLOCK_GATING_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) data |= CLOCK_GATING_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) WREG32(HDP_HOST_PATH_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) static void cik_enable_hdp_ls(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) u32 orig, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) orig = data = RREG32(HDP_MEM_POWER_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) data |= HDP_LS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) data &= ~HDP_LS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) WREG32(HDP_MEM_POWER_LS, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) void cik_update_cg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) u32 block, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) if (block & RADEON_CG_BLOCK_GFX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) cik_enable_gui_idle_interrupt(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) /* order matters! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) cik_enable_mgcg(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) cik_enable_cgcg(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) cik_enable_cgcg(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) cik_enable_mgcg(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) cik_enable_gui_idle_interrupt(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) if (block & RADEON_CG_BLOCK_MC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) if (!(rdev->flags & RADEON_IS_IGP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) cik_enable_mc_mgcg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) cik_enable_mc_ls(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) if (block & RADEON_CG_BLOCK_SDMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) cik_enable_sdma_mgcg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) cik_enable_sdma_mgls(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) if (block & RADEON_CG_BLOCK_BIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) cik_enable_bif_mgls(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) if (block & RADEON_CG_BLOCK_UVD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) if (rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) cik_enable_uvd_mgcg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) if (block & RADEON_CG_BLOCK_HDP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) cik_enable_hdp_mgcg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) cik_enable_hdp_ls(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) if (block & RADEON_CG_BLOCK_VCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) vce_v2_0_enable_mgcg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) static void cik_init_cg(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) if (rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) si_init_uvd_internal_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) RADEON_CG_BLOCK_SDMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) RADEON_CG_BLOCK_BIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) RADEON_CG_BLOCK_UVD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) RADEON_CG_BLOCK_HDP), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) static void cik_fini_cg(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) RADEON_CG_BLOCK_SDMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) RADEON_CG_BLOCK_BIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) RADEON_CG_BLOCK_UVD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) RADEON_CG_BLOCK_HDP), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) data &= ~DISABLE_CP_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) data |= DISABLE_CP_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) data &= ~DISABLE_GDS_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) data |= DISABLE_GDS_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) #define CP_ME_TABLE_SIZE 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) #define CP_ME_TABLE_OFFSET 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) #define CP_MEC_TABLE_OFFSET 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) void cik_init_cp_pg_table(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) volatile u32 *dst_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) int me, i, max_me = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) u32 bo_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) u32 table_offset, table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) if (rdev->family == CHIP_KAVERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) max_me = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) if (rdev->rlc.cp_table_ptr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) /* write the cp table buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) dst_ptr = rdev->rlc.cp_table_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) for (me = 0; me < max_me; me++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) if (rdev->new_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) const __le32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) const struct gfx_firmware_header_v1_0 *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) if (me == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) hdr = (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) (rdev->ce_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) table_offset = le32_to_cpu(hdr->jt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) table_size = le32_to_cpu(hdr->jt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) } else if (me == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) hdr = (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) (rdev->pfp_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) table_offset = le32_to_cpu(hdr->jt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) table_size = le32_to_cpu(hdr->jt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) } else if (me == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) hdr = (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) (rdev->me_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) table_offset = le32_to_cpu(hdr->jt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) table_size = le32_to_cpu(hdr->jt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) } else if (me == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) (rdev->mec_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) table_offset = le32_to_cpu(hdr->jt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) table_size = le32_to_cpu(hdr->jt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) fw_data = (const __le32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) (rdev->mec2_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) table_offset = le32_to_cpu(hdr->jt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) table_size = le32_to_cpu(hdr->jt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) for (i = 0; i < table_size; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) dst_ptr[bo_offset + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) bo_offset += table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) const __be32 *fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) table_size = CP_ME_TABLE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) if (me == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) fw_data = (const __be32 *)rdev->ce_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) table_offset = CP_ME_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) } else if (me == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) fw_data = (const __be32 *)rdev->pfp_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) table_offset = CP_ME_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) } else if (me == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) fw_data = (const __be32 *)rdev->me_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) table_offset = CP_ME_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) fw_data = (const __be32 *)rdev->mec_fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) table_offset = CP_MEC_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) for (i = 0; i < table_size; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) dst_ptr[bo_offset + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) bo_offset += table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) data |= GFX_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) orig = data = RREG32(RLC_AUTO_PG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) data |= AUTO_PG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) WREG32(RLC_AUTO_PG_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) data &= ~GFX_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) orig = data = RREG32(RLC_AUTO_PG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) data &= ~AUTO_PG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) WREG32(RLC_AUTO_PG_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) data = RREG32(DB_RENDER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) u32 mask = 0, tmp, tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) cik_select_se_sh(rdev, se, sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) tmp &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) tmp |= tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) tmp >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) mask |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) return (~tmp) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) static void cik_init_ao_cu_mask(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) u32 i, j, k, active_cu_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) u32 mask, counter, cu_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) cu_bitmap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) if (counter < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) cu_bitmap |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) counter ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) active_cu_number += counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) tmp |= (cu_bitmap << (i * 16 + j * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) WREG32(RLC_PG_AO_CU_MASK, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) tmp = RREG32(RLC_MAX_PG_CU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) tmp &= ~MAX_PU_CU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) tmp |= MAX_PU_CU(active_cu_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) WREG32(RLC_MAX_PG_CU, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) data |= STATIC_PER_CU_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) data &= ~STATIC_PER_CU_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) data |= DYN_PER_CU_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) data &= ~DYN_PER_CU_PG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) static void cik_init_gfx_cgpg(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) if (rdev->rlc.cs_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) WREG32(RLC_GPM_SCRATCH_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) if (rdev->rlc.reg_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) for (i = 0; i < rdev->rlc.reg_list_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) orig = data = RREG32(RLC_PG_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) data |= GFX_PG_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) WREG32(RLC_PG_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) data = RREG32(CP_RB_WPTR_POLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) data &= ~IDLE_POLL_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) data |= IDLE_POLL_COUNT(0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) WREG32(CP_RB_WPTR_POLL_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) data = 0x10101010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) WREG32(RLC_PG_DELAY, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) data = RREG32(RLC_PG_DELAY_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) data &= ~0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) data |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) WREG32(RLC_PG_DELAY_2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) data = RREG32(RLC_AUTO_PG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) data &= ~GRBM_REG_SGIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) data |= GRBM_REG_SGIT(0x700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) WREG32(RLC_AUTO_PG_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) cik_enable_gfx_cgpg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) cik_enable_gfx_static_mgpg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) cik_enable_gfx_dynamic_mgpg(rdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) u32 cik_get_csb_size(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) u32 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) const struct cs_section_def *sect = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) const struct cs_extent_def *ext = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) if (rdev->rlc.cs_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) /* begin clear state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) count += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) /* context control state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) count += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) for (ext = sect->section; ext->extent != NULL; ++ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) if (sect->id == SECT_CONTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) count += 2 + ext->reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) /* pa_sc_raster_config/pa_sc_raster_config1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) count += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) /* end clear state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) count += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) /* clear state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) count += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) u32 count = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) const struct cs_section_def *sect = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) const struct cs_extent_def *ext = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) if (rdev->rlc.cs_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) if (buffer == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) buffer[count++] = cpu_to_le32(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) buffer[count++] = cpu_to_le32(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) for (ext = sect->section; ext->extent != NULL; ++ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) if (sect->id == SECT_CONTEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) buffer[count++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) for (i = 0; i < ext->reg_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) buffer[count++] = cpu_to_le32(ext->extent[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) switch (rdev->family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) case CHIP_BONAIRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) buffer[count++] = cpu_to_le32(0x16000012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) buffer[count++] = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) case CHIP_KAVERI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) buffer[count++] = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) case CHIP_KABINI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) case CHIP_MULLINS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) buffer[count++] = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) case CHIP_HAWAII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) buffer[count++] = cpu_to_le32(0x3a00161a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) buffer[count++] = cpu_to_le32(0x0000002e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) buffer[count++] = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) buffer[count++] = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) buffer[count++] = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) static void cik_init_pg(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) if (rdev->pg_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) cik_enable_sck_slowdown_on_pu(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) cik_enable_sck_slowdown_on_pd(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) cik_init_gfx_cgpg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) cik_enable_cp_pg(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) cik_enable_gds_pg(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) cik_init_ao_cu_mask(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) cik_update_gfx_pg(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) static void cik_fini_pg(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) if (rdev->pg_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) cik_update_gfx_pg(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) cik_enable_cp_pg(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) cik_enable_gds_pg(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) * Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) * Starting with r6xx, interrupts are handled via a ring buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) * Ring buffers are areas of GPU accessible memory that the GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) * writes interrupt vectors into and the host reads vectors out of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) * There is a rptr (read pointer) that determines where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) * host is currently reading, and a wptr (write pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) * which determines where the GPU has written. When the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) * pointers are equal, the ring is idle. When the GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) * writes vectors to the ring buffer, it increments the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) * wptr. When there is an interrupt, the host then starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) * fetching commands and processing them until the pointers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) * equal again at which point it updates the rptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) * cik_enable_interrupts - Enable the interrupt ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) * Enable the interrupt ring buffer (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) static void cik_enable_interrupts(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) u32 ih_cntl = RREG32(IH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) ih_cntl |= ENABLE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) ih_rb_cntl |= IH_RB_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) WREG32(IH_CNTL, ih_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) WREG32(IH_RB_CNTL, ih_rb_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) rdev->ih.enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) * cik_disable_interrupts - Disable the interrupt ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) * Disable the interrupt ring buffer (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) static void cik_disable_interrupts(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) u32 ih_cntl = RREG32(IH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) ih_rb_cntl &= ~IH_RB_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) ih_cntl &= ~ENABLE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) WREG32(IH_RB_CNTL, ih_rb_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) WREG32(IH_CNTL, ih_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) /* set rptr, wptr to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) WREG32(IH_RB_RPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) WREG32(IH_RB_WPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) rdev->ih.enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) rdev->ih.rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) * cik_disable_interrupt_state - Disable all interrupt sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) * Clear all interrupt enable bits used by the driver (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) static void cik_disable_interrupt_state(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) /* gfx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) tmp = RREG32(CP_INT_CNTL_RING0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) WREG32(CP_INT_CNTL_RING0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) /* sdma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) /* compute queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) /* grbm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) WREG32(GRBM_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) /* SRBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) WREG32(SRBM_INT_CNTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) /* vline/vblank, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) /* pflip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) if (rdev->num_crtc >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) /* dac hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) /* digital hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) WREG32(DC_HPD1_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) WREG32(DC_HPD2_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) WREG32(DC_HPD3_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) WREG32(DC_HPD4_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) WREG32(DC_HPD5_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) WREG32(DC_HPD6_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) * cik_irq_init - init and enable the interrupt ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) * Allocate a ring buffer for the interrupt controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) * enable the RLC, disable interrupts, enable the IH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) * ring buffer and enable it (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) * Called at device load and reume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) * Returns 0 for success, errors for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) static int cik_irq_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) int rb_bufsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) /* allocate ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) ret = r600_ih_ring_alloc(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) /* disable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) cik_disable_interrupts(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) /* init rlc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) ret = cik_rlc_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) r600_ih_ring_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) /* setup interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) /* set dummy read address to dummy page address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) interrupt_cntl = RREG32(INTERRUPT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) WREG32(INTERRUPT_CNTL, interrupt_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) IH_WPTR_OVERFLOW_CLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) (rb_bufsz << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) if (rdev->wb.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) /* set the writeback address whether it's enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) WREG32(IH_RB_CNTL, ih_rb_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) /* set rptr, wptr to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) WREG32(IH_RB_RPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) WREG32(IH_RB_WPTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) /* Default settings for IH_CNTL (disabled at first) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) /* RPTR_REARM only works if msi's are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) if (rdev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) ih_cntl |= RPTR_REARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) WREG32(IH_CNTL, ih_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) /* force the active interrupt state to all disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) cik_disable_interrupt_state(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) pci_set_master(rdev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) /* enable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) cik_enable_interrupts(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) * cik_irq_set - enable/disable interrupt sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) * Enable interrupt sources on the GPU (vblanks, hpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) * etc.) (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) * Returns 0 for success, errors for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) int cik_irq_set(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) u32 cp_int_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) u32 grbm_int_cntl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) u32 dma_cntl, dma_cntl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) /* don't enable anything if the ih is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) if (!rdev->ih.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) cik_disable_interrupts(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) /* force the active interrupt state to all disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) cik_disable_interrupt_state(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) /* enable CP interrupts on all rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) DRM_DEBUG("cik_irq_set: sw int gfx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) cp_int_cntl |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) DRM_DEBUG("si_irq_set: sw int cp1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) if (ring->me == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) switch (ring->pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) cp_m1p0 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) cp_m1p1 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) cp_m1p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) cp_m1p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) } else if (ring->me == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) switch (ring->pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) cp_m2p0 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) cp_m2p1 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) cp_m2p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) cp_m2p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) DRM_DEBUG("si_irq_set: sw int cp2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) if (ring->me == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) switch (ring->pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) cp_m1p0 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) cp_m1p1 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) cp_m1p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) cp_m1p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) } else if (ring->me == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) switch (ring->pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) cp_m2p0 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) cp_m2p1 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) cp_m2p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) cp_m2p2 |= TIME_STAMP_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) DRM_DEBUG("cik_irq_set: sw int dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) dma_cntl |= TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) DRM_DEBUG("cik_irq_set: sw int dma1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) dma_cntl1 |= TRAP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) if (rdev->irq.crtc_vblank_int[0] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) atomic_read(&rdev->irq.pflip[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) DRM_DEBUG("cik_irq_set: vblank 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) crtc1 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) if (rdev->irq.crtc_vblank_int[1] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) atomic_read(&rdev->irq.pflip[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) DRM_DEBUG("cik_irq_set: vblank 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) crtc2 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) if (rdev->irq.crtc_vblank_int[2] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) atomic_read(&rdev->irq.pflip[2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) DRM_DEBUG("cik_irq_set: vblank 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) crtc3 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) if (rdev->irq.crtc_vblank_int[3] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) atomic_read(&rdev->irq.pflip[3])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) DRM_DEBUG("cik_irq_set: vblank 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) crtc4 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) if (rdev->irq.crtc_vblank_int[4] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) atomic_read(&rdev->irq.pflip[4])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) DRM_DEBUG("cik_irq_set: vblank 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) crtc5 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) if (rdev->irq.crtc_vblank_int[5] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) atomic_read(&rdev->irq.pflip[5])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) DRM_DEBUG("cik_irq_set: vblank 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) crtc6 |= VBLANK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) if (rdev->irq.hpd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) DRM_DEBUG("cik_irq_set: hpd 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) if (rdev->irq.hpd[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) DRM_DEBUG("cik_irq_set: hpd 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) if (rdev->irq.hpd[2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) DRM_DEBUG("cik_irq_set: hpd 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) if (rdev->irq.hpd[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) DRM_DEBUG("cik_irq_set: hpd 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) if (rdev->irq.hpd[4]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) DRM_DEBUG("cik_irq_set: hpd 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) if (rdev->irq.hpd[5]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) DRM_DEBUG("cik_irq_set: hpd 6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) WREG32(GRBM_INT_CNTL, grbm_int_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) if (rdev->num_crtc >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) GRPH_PFLIP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) WREG32(DC_HPD1_INT_CONTROL, hpd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) WREG32(DC_HPD2_INT_CONTROL, hpd2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) WREG32(DC_HPD3_INT_CONTROL, hpd3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) WREG32(DC_HPD4_INT_CONTROL, hpd4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) WREG32(DC_HPD5_INT_CONTROL, hpd5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) WREG32(DC_HPD6_INT_CONTROL, hpd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) /* posting read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) RREG32(SRBM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) * cik_irq_ack - ack interrupt sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) * Ack interrupt sources on the GPU (vblanks, hpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) * etc.) (CIK). Certain interrupts sources are sw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) * generated and do not require an explicit ack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) static inline void cik_irq_ack(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) EVERGREEN_CRTC0_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) EVERGREEN_CRTC1_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) EVERGREEN_CRTC2_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) EVERGREEN_CRTC3_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) EVERGREEN_CRTC4_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) EVERGREEN_CRTC5_REGISTER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) if (rdev->num_crtc >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) if (rdev->num_crtc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) GRPH_PFLIP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) tmp = RREG32(DC_HPD1_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) WREG32(DC_HPD1_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) tmp = RREG32(DC_HPD2_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) WREG32(DC_HPD2_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) tmp = RREG32(DC_HPD3_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) WREG32(DC_HPD3_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) tmp = RREG32(DC_HPD4_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) WREG32(DC_HPD4_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) tmp = RREG32(DC_HPD5_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) WREG32(DC_HPD5_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) tmp = RREG32(DC_HPD6_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) tmp |= DC_HPDx_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) WREG32(DC_HPD6_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) tmp = RREG32(DC_HPD1_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) WREG32(DC_HPD1_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) tmp = RREG32(DC_HPD2_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) WREG32(DC_HPD2_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) tmp = RREG32(DC_HPD3_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) WREG32(DC_HPD3_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) tmp = RREG32(DC_HPD4_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) WREG32(DC_HPD4_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) tmp = RREG32(DC_HPD5_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) WREG32(DC_HPD5_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) tmp = RREG32(DC_HPD6_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) tmp |= DC_HPDx_RX_INT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) WREG32(DC_HPD6_INT_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) * cik_irq_disable - disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) * Disable interrupts on the hw (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) static void cik_irq_disable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) cik_disable_interrupts(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) /* Wait and acknowledge irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) cik_irq_ack(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) cik_disable_interrupt_state(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) * cik_irq_disable - disable interrupts for suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) * Disable interrupts and stop the RLC (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) * Used for suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) static void cik_irq_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) cik_irq_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) cik_rlc_stop(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) * cik_irq_fini - tear down interrupt support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) * Disable interrupts on the hw and free the IH ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) * buffer (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) * Used for driver unload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) static void cik_irq_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) cik_irq_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) r600_ih_ring_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) * cik_get_ih_wptr - get the IH ring buffer wptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) * Get the IH ring buffer wptr from either the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) * or the writeback memory buffer (CIK). Also check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) * ring buffer overflow and deal with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) * Used by cik_irq_process().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) * Returns the value of the wptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) u32 wptr, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) if (rdev->wb.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) wptr = RREG32(IH_RB_WPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) if (wptr & RB_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) wptr &= ~RB_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) /* When a ring buffer overflow happen start parsing interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) * from the last not overwritten vector (wptr + 16). Hopefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) * this should allow us to catchup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) tmp = RREG32(IH_RB_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) tmp |= IH_WPTR_OVERFLOW_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) WREG32(IH_RB_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) return (wptr & rdev->ih.ptr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) /* CIK IV Ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) * Each IV ring entry is 128 bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) * [7:0] - interrupt source id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) * [31:8] - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) * [59:32] - interrupt source data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) * [63:60] - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) * [71:64] - RINGID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) * CP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) * PIPE_ID - ME0 0=3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) * - ME1&2 compute dispatcher (4 pipes each)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) * SDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) * INSTANCE_ID [1:0], QUEUE_ID[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) * INSTANCE_ID - 0 = sdma0, 1 = sdma1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) * [79:72] - VMID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) * [95:80] - PASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) * [127:96] - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) * cik_irq_process - interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) * Interrupt hander (CIK). Walk the IH ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) * ack interrupts and schedule work to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) * interrupt events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) * Returns irq process return code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) int cik_irq_process(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) u32 wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) u32 rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) u32 src_id, src_data, ring_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) u8 me_id, pipe_id, queue_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) u32 ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) bool queue_hotplug = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) bool queue_dp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) bool queue_reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) u32 addr, status, mc_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) bool queue_thermal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) if (!rdev->ih.enabled || rdev->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) wptr = cik_get_ih_wptr(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) restart_ih:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) /* is somebody else already processing irqs? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) if (atomic_xchg(&rdev->ih.lock, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) rptr = rdev->ih.rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) /* Order reading of wptr vs. reading of IH ring data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) /* display interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) cik_irq_ack(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) while (rptr != wptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) /* wptr/rptr are in bytes! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) ring_index = rptr / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591) switch (src_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) case 1: /* D1 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) case 0: /* D1 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) if (rdev->irq.crtc_vblank_int[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) drm_handle_vblank(rdev->ddev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) if (atomic_read(&rdev->irq.pflip[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) radeon_crtc_handle_vblank(rdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) DRM_DEBUG("IH: D1 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) case 1: /* D1 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) DRM_DEBUG("IH: D1 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) case 2: /* D2 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) case 0: /* D2 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) if (rdev->irq.crtc_vblank_int[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) drm_handle_vblank(rdev->ddev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) if (atomic_read(&rdev->irq.pflip[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) radeon_crtc_handle_vblank(rdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) DRM_DEBUG("IH: D2 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) case 1: /* D2 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) DRM_DEBUG("IH: D2 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) case 3: /* D3 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) case 0: /* D3 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) if (rdev->irq.crtc_vblank_int[2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) drm_handle_vblank(rdev->ddev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) if (atomic_read(&rdev->irq.pflip[2]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) radeon_crtc_handle_vblank(rdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) DRM_DEBUG("IH: D3 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) case 1: /* D3 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) DRM_DEBUG("IH: D3 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) case 4: /* D4 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) case 0: /* D4 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) if (rdev->irq.crtc_vblank_int[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) drm_handle_vblank(rdev->ddev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) if (atomic_read(&rdev->irq.pflip[3]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) radeon_crtc_handle_vblank(rdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) DRM_DEBUG("IH: D4 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) case 1: /* D4 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) DRM_DEBUG("IH: D4 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) case 5: /* D5 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) case 0: /* D5 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) if (rdev->irq.crtc_vblank_int[4]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) drm_handle_vblank(rdev->ddev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) if (atomic_read(&rdev->irq.pflip[4]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) radeon_crtc_handle_vblank(rdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) DRM_DEBUG("IH: D5 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) case 1: /* D5 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) DRM_DEBUG("IH: D5 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) case 6: /* D6 vblank/vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) case 0: /* D6 vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) if (rdev->irq.crtc_vblank_int[5]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) drm_handle_vblank(rdev->ddev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) rdev->pm.vblank_sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) wake_up(&rdev->irq.vblank_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) if (atomic_read(&rdev->irq.pflip[5]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) radeon_crtc_handle_vblank(rdev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) DRM_DEBUG("IH: D6 vblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) case 1: /* D6 vline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) DRM_DEBUG("IH: D6 vline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) case 8: /* D1 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) case 10: /* D2 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) case 12: /* D3 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) case 14: /* D4 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) case 16: /* D5 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) case 18: /* D6 page flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) if (radeon_use_pflipirq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) case 42: /* HPD hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) DRM_DEBUG("IH: HPD1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) DRM_DEBUG("IH: HPD2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) DRM_DEBUG("IH: HPD3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) DRM_DEBUG("IH: HPD4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) DRM_DEBUG("IH: HPD5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) queue_hotplug = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) DRM_DEBUG("IH: HPD6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) DRM_DEBUG("IH: HPD_RX 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) DRM_DEBUG("IH: HPD_RX 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) DRM_DEBUG("IH: HPD_RX 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871) DRM_DEBUG("IH: HPD_RX 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) DRM_DEBUG("IH: HPD_RX 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) queue_dp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) DRM_DEBUG("IH: HPD_RX 6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) case 96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) WREG32(SRBM_INT_ACK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901) case 124: /* UVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905) case 146:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) case 147:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909) mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) /* reset addr and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911) WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) if (addr == 0x0 && status == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917) dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) cik_vm_decode_fault(rdev, status, addr, mc_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) case 167: /* VCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) switch (src_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) case 176: /* GFX RB CP_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) case 177: /* GFX IB CP_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) case 181: /* CP EOP event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) DRM_DEBUG("IH: CP EOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) /* XXX check the bitfield order! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942) me_id = (ring_id & 0x60) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) pipe_id = (ring_id & 0x18) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) queue_id = (ring_id & 0x7) >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945) switch (me_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) case 184: /* CP Privileged reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) DRM_ERROR("Illegal register access in command stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) /* XXX check the bitfield order! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) me_id = (ring_id & 0x60) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) pipe_id = (ring_id & 0x18) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963) queue_id = (ring_id & 0x7) >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964) switch (me_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) /* This results in a full GPU reset, but all we need to do is soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) * reset the CP for gfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) case 185: /* CP Privileged inst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) DRM_ERROR("Illegal instruction in command stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) /* XXX check the bitfield order! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) me_id = (ring_id & 0x60) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) pipe_id = (ring_id & 0x18) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) queue_id = (ring_id & 0x7) >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987) switch (me_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) /* This results in a full GPU reset, but all we need to do is soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) * reset the CP for gfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) case 224: /* SDMA trap event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) /* XXX check the bitfield order! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) me_id = (ring_id & 0x3) >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) queue_id = (ring_id & 0xc) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008) DRM_DEBUG("IH: SDMA trap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) switch (me_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) switch (queue_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013) radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) switch (queue_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) case 230: /* thermal low to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) DRM_DEBUG("IH: thermal low to high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040) rdev->pm.dpm.thermal.high_to_low = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) queue_thermal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043) case 231: /* thermal high to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) DRM_DEBUG("IH: thermal high to low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045) rdev->pm.dpm.thermal.high_to_low = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) queue_thermal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) case 233: /* GUI IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049) DRM_DEBUG("IH: GUI idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051) case 241: /* SDMA Privileged inst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) case 247: /* SDMA Privileged inst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) DRM_ERROR("Illegal instruction in SDMA command stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054) /* XXX check the bitfield order! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055) me_id = (ring_id & 0x3) >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) queue_id = (ring_id & 0xc) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) switch (me_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) switch (queue_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074) switch (queue_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) /* XXX compute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084) queue_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091) DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) /* wptr/rptr are in bytes! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) rptr += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097) rptr &= rdev->ih.ptr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) WREG32(IH_RB_RPTR, rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) if (queue_dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101) schedule_work(&rdev->dp_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) if (queue_hotplug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103) schedule_delayed_work(&rdev->hotplug_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) if (queue_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) rdev->needs_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) wake_up_all(&rdev->fence_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) if (queue_thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) schedule_work(&rdev->pm.dpm.thermal.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110) rdev->ih.rptr = rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) atomic_set(&rdev->ih.lock, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) /* make sure wptr hasn't changed while processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114) wptr = cik_get_ih_wptr(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) if (wptr != rptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116) goto restart_ih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) * startup/shutdown callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124) static void cik_uvd_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) if (!rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131) r = radeon_uvd_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133) dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) * At this point rdev->uvd.vcpu_bo is NULL which trickles down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) * to early fails cik_uvd_start() and thus nothing happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137) * there. So it is pointless to try to go through that code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) * hence why we disable uvd here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) rdev->has_uvd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147) static void cik_uvd_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151) if (!rdev->has_uvd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154) r = radeon_uvd_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156) dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) r = uvd_v4_2_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161) dev_err(rdev->dev, "failed UVD 4.2 resume (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) static void cik_uvd_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180) if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183) ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184) r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189) r = uvd_v1_0_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196) static void cik_vce_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200) if (!rdev->has_vce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) r = radeon_vce_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205) dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) * At this point rdev->vce.vcpu_bo is NULL which trickles down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208) * to early fails cik_vce_start() and thus nothing happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209) * there. So it is pointless to try to go through that code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210) * hence why we disable vce here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212) rdev->has_vce = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217) rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221) static void cik_vce_start(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) if (!rdev->has_vce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228) r = radeon_vce_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) r = vce_v2_0_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240) dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243) r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245) dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252) rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255) static void cik_vce_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260) if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264) r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266) dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270) r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272) dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275) r = vce_v1_0_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277) dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) * cik_startup - program the asic to a functional state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) * Programs the asic to a functional state (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288) * Called by cik_init() and cik_resume().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) static int cik_startup(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294) u32 nop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) /* enable pcie gen2/3 link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) cik_pcie_gen3_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299) /* enable aspm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) cik_program_aspm(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302) /* scratch needs to be initialized before MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303) r = r600_vram_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307) cik_mc_program(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309) if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) r = ci_mc_load_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) DRM_ERROR("Failed to load MC firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317) r = cik_pcie_gart_enable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) cik_gpu_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) /* allocate rlc buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323) if (rdev->flags & RADEON_IS_IGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) if (rdev->family == CHIP_KAVERI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325) rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326) rdev->rlc.reg_list_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327) (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) rdev->rlc.reg_list_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331) (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) rdev->rlc.cs_data = ci_cs_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335) rdev->rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) rdev->rlc.cp_table_size += 64 * 1024; /* GDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) r = sumo_rlc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339) DRM_ERROR("Failed to init rlc BOs!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343) /* allocate wb buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) r = radeon_wb_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) /* allocate mec buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349) r = cik_mec_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351) DRM_ERROR("Failed to init MEC BOs!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355) r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367) r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373) r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375) dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379) r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381) dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385) cik_uvd_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) cik_vce_start(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388) /* Enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) if (!rdev->irq.installed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) r = radeon_irq_kms_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395) r = cik_irq_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) DRM_ERROR("radeon: IH init failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) cik_irq_set(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403) if (rdev->family == CHIP_HAWAII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404) if (rdev->new_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405) nop = PACKET3(PACKET3_NOP, 0x3FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407) nop = RADEON_CP_PACKET2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409) nop = PACKET3(PACKET3_NOP, 0x3FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412) ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414) nop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) /* set up the compute queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419) /* type-2 packets are deprecated on MEC, use type-3 instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422) nop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) ring->me = 1; /* first MEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426) ring->pipe = 0; /* first pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427) ring->queue = 0; /* first queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) /* type-2 packets are deprecated on MEC, use type-3 instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432) r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) nop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) /* dGPU only have 1 MEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) ring->me = 1; /* first MEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438) ring->pipe = 0; /* first pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439) ring->queue = 1; /* second queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440) ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442) ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444) SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450) SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) r = cik_cp_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458) r = cik_sdma_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462) cik_uvd_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463) cik_vce_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) r = radeon_ib_pool_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467) dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471) r = radeon_vm_manager_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) r = radeon_audio_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485) * cik_resume - resume the asic to a functional state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489) * Programs the asic to a functional state (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) * Called at resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491) * Returns 0 for success, error for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493) int cik_resume(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) /* post card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) /* init golden registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501) cik_init_golden_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) if (rdev->pm.pm_method == PM_METHOD_DPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) radeon_pm_resume(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) r = cik_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509) DRM_ERROR("cik startup failed on resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519) * cik_suspend - suspend the asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523) * Bring the chip into a state suitable for suspend (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) * Called at suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) int cik_suspend(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8529) radeon_pm_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8530) radeon_audio_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8531) radeon_vm_manager_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8532) cik_cp_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8533) cik_sdma_enable(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8534) if (rdev->has_uvd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8535) uvd_v1_0_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8536) radeon_uvd_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8538) if (rdev->has_vce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8539) radeon_vce_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8540) cik_fini_pg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8541) cik_fini_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8542) cik_irq_suspend(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8543) radeon_wb_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8544) cik_pcie_gart_disable(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8548) /* Plan is to move initialization in that function and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8549) * helper function so that radeon_device_init pretty much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8550) * do nothing more than calling asic specific function. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8551) * should also allow to remove a bunch of callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8552) * like vram_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8554) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8555) * cik_init - asic specific driver and hw init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8557) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8559) * Setup asic specific driver variables and program the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8560) * to a functional state (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8561) * Called at driver startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8562) * Returns 0 for success, errors for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8564) int cik_init(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8566) struct radeon_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8567) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8569) /* Read BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8570) if (!radeon_get_bios(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8571) if (ASIC_IS_AVIVO(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8574) /* Must be an ATOMBIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8575) if (!rdev->is_atom_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8576) dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8577) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8579) r = radeon_atombios_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8580) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8581) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8583) /* Post card if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8584) if (!radeon_card_posted(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8585) if (!rdev->bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8586) dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8589) DRM_INFO("GPU not posted. posting now...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8590) atom_asic_init(rdev->mode_info.atom_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8592) /* init golden registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8593) cik_init_golden_registers(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8594) /* Initialize scratch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8595) cik_scratch_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8596) /* Initialize surface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8597) radeon_surface_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8598) /* Initialize clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8599) radeon_get_clock_info(rdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8601) /* Fence driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8602) r = radeon_fence_driver_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8603) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8604) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8606) /* initialize memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8607) r = cik_mc_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8608) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8609) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8610) /* Memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8611) r = radeon_bo_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8612) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8613) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8615) if (rdev->flags & RADEON_IS_IGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8616) if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8617) !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8618) r = cik_init_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8619) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8620) DRM_ERROR("Failed to load firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8621) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8625) if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8626) !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8627) !rdev->mc_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8628) r = cik_init_microcode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8629) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8630) DRM_ERROR("Failed to load firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8631) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8636) /* Initialize power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8637) radeon_pm_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8639) ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8640) ring->ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8641) r600_ring_init(rdev, ring, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8643) ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8644) ring->ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8645) r600_ring_init(rdev, ring, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8646) r = radeon_doorbell_get(rdev, &ring->doorbell_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8647) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8648) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8650) ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8651) ring->ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8652) r600_ring_init(rdev, ring, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8653) r = radeon_doorbell_get(rdev, &ring->doorbell_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8654) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8655) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8657) ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8658) ring->ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8659) r600_ring_init(rdev, ring, 256 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8661) ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8662) ring->ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8663) r600_ring_init(rdev, ring, 256 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8665) cik_uvd_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8666) cik_vce_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8668) rdev->ih.ring_obj = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8669) r600_ih_ring_init(rdev, 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8671) r = r600_pcie_gart_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8672) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8673) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8675) rdev->accel_working = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8676) r = cik_startup(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8677) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8678) dev_err(rdev->dev, "disabling GPU acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8679) cik_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8680) cik_sdma_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8681) cik_irq_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8682) sumo_rlc_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8683) cik_mec_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8684) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8685) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8686) radeon_vm_manager_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8687) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8688) cik_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8689) rdev->accel_working = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8692) /* Don't start up if the MC ucode is missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8693) * The default clocks and voltages before the MC ucode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8694) * is loaded are not suffient for advanced operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8696) if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8697) DRM_ERROR("radeon: MC ucode required for NI+.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8704) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8705) * cik_fini - asic specific driver and hw fini
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8707) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8709) * Tear down the asic specific driver variables and program the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8710) * to an idle state (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8711) * Called at driver unload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8713) void cik_fini(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8715) radeon_pm_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8716) cik_cp_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8717) cik_sdma_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8718) cik_fini_pg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8719) cik_fini_cg(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8720) cik_irq_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8721) sumo_rlc_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8722) cik_mec_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8723) radeon_wb_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8724) radeon_vm_manager_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8725) radeon_ib_pool_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8726) radeon_irq_kms_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8727) uvd_v1_0_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8728) radeon_uvd_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8729) radeon_vce_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8730) cik_pcie_gart_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8731) r600_vram_scratch_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8732) radeon_gem_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8733) radeon_fence_driver_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8734) radeon_bo_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8735) radeon_atombios_fini(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8736) kfree(rdev->bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8737) rdev->bios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8740) void dce8_program_fmt(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8742) struct drm_device *dev = encoder->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8743) struct radeon_device *rdev = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8744) struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8745) struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8746) struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8747) int bpc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8748) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8749) enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8751) if (connector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8752) struct radeon_connector *radeon_connector = to_radeon_connector(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8753) bpc = radeon_get_monitor_bpc(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8754) dither = radeon_connector->dither;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8757) /* LVDS/eDP FMT is set up by atom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8758) if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8759) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8761) /* not needed for analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8762) if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8763) (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8764) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8766) if (bpc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8767) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8769) switch (bpc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8770) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8771) if (dither == RADEON_FMT_DITHER_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8772) /* XXX sort out optimal dither settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8773) tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8774) FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8776) tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8778) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8779) if (dither == RADEON_FMT_DITHER_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8780) /* XXX sort out optimal dither settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8781) tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8782) FMT_RGB_RANDOM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8783) FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8785) tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8787) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8788) if (dither == RADEON_FMT_DITHER_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8789) /* XXX sort out optimal dither settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8790) tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8791) FMT_RGB_RANDOM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8792) FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8794) tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8796) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8797) /* not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8801) WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8804) /* display watermark setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8805) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8806) * dce8_line_buffer_adjust - Set up the line buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8808) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8809) * @radeon_crtc: the selected display controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8810) * @mode: the current display mode on the selected display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8811) * controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8813) * Setup up the line buffer allocation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8814) * the selected display controller (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8815) * Returns the line buffer size in pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8817) static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8818) struct radeon_crtc *radeon_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8819) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8821) u32 tmp, buffer_alloc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8822) u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8824) * Line Buffer Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8825) * There are 6 line buffers, one for each display controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8826) * There are 3 partitions per LB. Select the number of partitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8827) * to enable based on the display width. For display widths larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8828) * than 4096, you need use to use 2 display controllers and combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8829) * them using the stereo blender.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8831) if (radeon_crtc->base.enabled && mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8832) if (mode->crtc_hdisplay < 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8833) tmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8834) buffer_alloc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8835) } else if (mode->crtc_hdisplay < 2560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8836) tmp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8837) buffer_alloc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8838) } else if (mode->crtc_hdisplay < 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8839) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8840) buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8842) DRM_DEBUG_KMS("Mode too big for LB!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8843) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8844) buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8846) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8847) tmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8848) buffer_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8851) WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8852) LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8854) WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8855) DMIF_BUFFERS_ALLOCATED(buffer_alloc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8856) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8857) if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8858) DMIF_BUFFERS_ALLOCATED_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8860) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8863) if (radeon_crtc->base.enabled && mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8864) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8865) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8866) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8867) return 4096 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8868) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8869) return 1920 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8870) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8871) return 2560 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8875) /* controller not enabled, so no lb used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8879) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8880) * cik_get_number_of_dram_channels - get the number of dram channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8882) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8884) * Look up the number of video ram channels (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8885) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8886) * Returns the number of dram channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8888) static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8890) u32 tmp = RREG32(MC_SHARED_CHMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8892) switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8893) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8894) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8895) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8896) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8897) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8898) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8899) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8900) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8901) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8902) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8903) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8904) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8905) return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8906) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8907) return 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8908) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8909) return 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8910) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8911) return 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8915) struct dce8_wm_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8916) u32 dram_channels; /* number of dram channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8917) u32 yclk; /* bandwidth per dram data pin in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8918) u32 sclk; /* engine clock in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8919) u32 disp_clk; /* display clock in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8920) u32 src_width; /* viewport width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8921) u32 active_time; /* active display time in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8922) u32 blank_time; /* blank time in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8923) bool interlaced; /* mode is interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8924) fixed20_12 vsc; /* vertical scale ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8925) u32 num_heads; /* number of active crtcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8926) u32 bytes_per_pixel; /* bytes per pixel display + overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8927) u32 lb_size; /* line buffer allocated to pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8928) u32 vtaps; /* vertical scaler taps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8931) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8932) * dce8_dram_bandwidth - get the dram bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8933) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8934) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8936) * Calculate the raw dram bandwidth (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8937) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8938) * Returns the dram bandwidth in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8940) static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8942) /* Calculate raw DRAM Bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8943) fixed20_12 dram_efficiency; /* 0.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8944) fixed20_12 yclk, dram_channels, bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8945) fixed20_12 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8947) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8948) yclk.full = dfixed_const(wm->yclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8949) yclk.full = dfixed_div(yclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8950) dram_channels.full = dfixed_const(wm->dram_channels * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8951) a.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8952) dram_efficiency.full = dfixed_const(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8953) dram_efficiency.full = dfixed_div(dram_efficiency, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8954) bandwidth.full = dfixed_mul(dram_channels, yclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8955) bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8957) return dfixed_trunc(bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8961) * dce8_dram_bandwidth_for_display - get the dram bandwidth for display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8963) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8964) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8965) * Calculate the dram bandwidth used for display (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8966) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8967) * Returns the dram bandwidth for display in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8969) static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8971) /* Calculate DRAM Bandwidth and the part allocated to display. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8972) fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8973) fixed20_12 yclk, dram_channels, bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8974) fixed20_12 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8976) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8977) yclk.full = dfixed_const(wm->yclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8978) yclk.full = dfixed_div(yclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8979) dram_channels.full = dfixed_const(wm->dram_channels * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8980) a.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8981) disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8982) disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8983) bandwidth.full = dfixed_mul(dram_channels, yclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8984) bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8986) return dfixed_trunc(bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8989) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8990) * dce8_data_return_bandwidth - get the data return bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8992) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8994) * Calculate the data return bandwidth used for display (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8995) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8996) * Returns the data return bandwidth in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8998) static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9000) /* Calculate the display Data return Bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9001) fixed20_12 return_efficiency; /* 0.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9002) fixed20_12 sclk, bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9003) fixed20_12 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9005) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9006) sclk.full = dfixed_const(wm->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9007) sclk.full = dfixed_div(sclk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9008) a.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9009) return_efficiency.full = dfixed_const(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9010) return_efficiency.full = dfixed_div(return_efficiency, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9011) a.full = dfixed_const(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9012) bandwidth.full = dfixed_mul(a, sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9013) bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9015) return dfixed_trunc(bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9018) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9019) * dce8_dmif_request_bandwidth - get the dmif bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9021) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9023) * Calculate the dmif bandwidth used for display (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9024) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9025) * Returns the dmif bandwidth in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9027) static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9029) /* Calculate the DMIF Request Bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9030) fixed20_12 disp_clk_request_efficiency; /* 0.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9031) fixed20_12 disp_clk, bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9032) fixed20_12 a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9034) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9035) disp_clk.full = dfixed_const(wm->disp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9036) disp_clk.full = dfixed_div(disp_clk, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9037) a.full = dfixed_const(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9038) b.full = dfixed_mul(a, disp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9040) a.full = dfixed_const(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9041) disp_clk_request_efficiency.full = dfixed_const(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9042) disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9044) bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9046) return dfixed_trunc(bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9049) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9050) * dce8_available_bandwidth - get the min available bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9052) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9054) * Calculate the min available bandwidth used for display (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9055) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9056) * Returns the min available bandwidth in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9058) static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9060) /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9061) u32 dram_bandwidth = dce8_dram_bandwidth(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9062) u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9063) u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9065) return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9068) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9069) * dce8_average_bandwidth - get the average available bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9070) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9071) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9073) * Calculate the average available bandwidth used for display (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9074) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9075) * Returns the average available bandwidth in MBytes/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9077) static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9079) /* Calculate the display mode Average Bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9080) * DisplayMode should contain the source and destination dimensions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9081) * timing, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9083) fixed20_12 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9084) fixed20_12 line_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9085) fixed20_12 src_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9086) fixed20_12 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9087) fixed20_12 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9089) a.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9090) line_time.full = dfixed_const(wm->active_time + wm->blank_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9091) line_time.full = dfixed_div(line_time, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9092) bpp.full = dfixed_const(wm->bytes_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9093) src_width.full = dfixed_const(wm->src_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9094) bandwidth.full = dfixed_mul(src_width, bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9095) bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9096) bandwidth.full = dfixed_div(bandwidth, line_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9098) return dfixed_trunc(bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9102) * dce8_latency_watermark - get the latency watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9104) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9106) * Calculate the latency watermark (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9107) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9108) * Returns the latency watermark in ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9110) static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9112) /* First calculate the latency in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9113) u32 mc_latency = 2000; /* 2000 ns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9114) u32 available_bandwidth = dce8_available_bandwidth(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9115) u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9116) u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9117) u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9118) u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9119) (wm->num_heads * cursor_line_pair_return_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9120) u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9121) u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9122) u32 tmp, dmif_size = 12288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9123) fixed20_12 a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9125) if (wm->num_heads == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9128) a.full = dfixed_const(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9129) b.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9130) if ((wm->vsc.full > a.full) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9131) ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9132) (wm->vtaps >= 5) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9133) ((wm->vsc.full >= a.full) && wm->interlaced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9134) max_src_lines_per_dst_line = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9136) max_src_lines_per_dst_line = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9138) a.full = dfixed_const(available_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9139) b.full = dfixed_const(wm->num_heads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9140) a.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9141) tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9142) tmp = min(dfixed_trunc(a), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9144) lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9146) a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9147) b.full = dfixed_const(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9148) c.full = dfixed_const(lb_fill_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9149) b.full = dfixed_div(c, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9150) a.full = dfixed_div(a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9151) line_fill_time = dfixed_trunc(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9153) if (line_fill_time < wm->active_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9154) return latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9156) return latency + (line_fill_time - wm->active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9161) * dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9162) * average and available dram bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9164) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9166) * Check if the display average bandwidth fits in the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9167) * dram bandwidth (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9168) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9169) * Returns true if the display fits, false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9171) static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9173) if (dce8_average_bandwidth(wm) <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9174) (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9175) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9177) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9181) * dce8_average_bandwidth_vs_available_bandwidth - check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9182) * average and available bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9184) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9186) * Check if the display average bandwidth fits in the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9187) * available bandwidth (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9188) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9189) * Returns true if the display fits, false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9191) static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9193) if (dce8_average_bandwidth(wm) <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9194) (dce8_available_bandwidth(wm) / wm->num_heads))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9195) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9197) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9200) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9201) * dce8_check_latency_hiding - check latency hiding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9203) * @wm: watermark calculation data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9205) * Check latency hiding (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9206) * Used for display watermark bandwidth calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9207) * Returns true if the display fits, false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9209) static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9211) u32 lb_partitions = wm->lb_size / wm->src_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9212) u32 line_time = wm->active_time + wm->blank_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9213) u32 latency_tolerant_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9214) u32 latency_hiding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9215) fixed20_12 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9217) a.full = dfixed_const(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9218) if (wm->vsc.full > a.full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9219) latency_tolerant_lines = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9220) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9221) if (lb_partitions <= (wm->vtaps + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9222) latency_tolerant_lines = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9224) latency_tolerant_lines = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9227) latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9229) if (dce8_latency_watermark(wm) <= latency_hiding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9230) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9232) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9235) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9236) * dce8_program_watermarks - program display watermarks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9238) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9239) * @radeon_crtc: the selected display controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9240) * @lb_size: line buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9241) * @num_heads: number of display controllers in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9243) * Calculate and program the display watermarks for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9244) * selected display controller (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9246) static void dce8_program_watermarks(struct radeon_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9247) struct radeon_crtc *radeon_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9248) u32 lb_size, u32 num_heads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9250) struct drm_display_mode *mode = &radeon_crtc->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9251) struct dce8_wm_params wm_low, wm_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9252) u32 active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9253) u32 line_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9254) u32 latency_watermark_a = 0, latency_watermark_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9255) u32 tmp, wm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9257) if (radeon_crtc->base.enabled && num_heads && mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9258) active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9259) (u32)mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9260) line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9261) (u32)mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9262) line_time = min(line_time, (u32)65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9264) /* watermark for high clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9265) if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9266) rdev->pm.dpm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9267) wm_high.yclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9268) radeon_dpm_get_mclk(rdev, false) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9269) wm_high.sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9270) radeon_dpm_get_sclk(rdev, false) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9272) wm_high.yclk = rdev->pm.current_mclk * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9273) wm_high.sclk = rdev->pm.current_sclk * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9276) wm_high.disp_clk = mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9277) wm_high.src_width = mode->crtc_hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9278) wm_high.active_time = active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9279) wm_high.blank_time = line_time - wm_high.active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9280) wm_high.interlaced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9281) if (mode->flags & DRM_MODE_FLAG_INTERLACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9282) wm_high.interlaced = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9283) wm_high.vsc = radeon_crtc->vsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9284) wm_high.vtaps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9285) if (radeon_crtc->rmx_type != RMX_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9286) wm_high.vtaps = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9287) wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9288) wm_high.lb_size = lb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9289) wm_high.dram_channels = cik_get_number_of_dram_channels(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9290) wm_high.num_heads = num_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9292) /* set for high clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9293) latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9295) /* possibly force display priority to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9296) /* should really do this at mode validation time... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9297) if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9298) !dce8_average_bandwidth_vs_available_bandwidth(&wm_high) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9299) !dce8_check_latency_hiding(&wm_high) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9300) (rdev->disp_priority == 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9301) DRM_DEBUG_KMS("force priority to high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9304) /* watermark for low clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9305) if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9306) rdev->pm.dpm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9307) wm_low.yclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9308) radeon_dpm_get_mclk(rdev, true) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9309) wm_low.sclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9310) radeon_dpm_get_sclk(rdev, true) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9312) wm_low.yclk = rdev->pm.current_mclk * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9313) wm_low.sclk = rdev->pm.current_sclk * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9316) wm_low.disp_clk = mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9317) wm_low.src_width = mode->crtc_hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9318) wm_low.active_time = active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9319) wm_low.blank_time = line_time - wm_low.active_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9320) wm_low.interlaced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9321) if (mode->flags & DRM_MODE_FLAG_INTERLACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9322) wm_low.interlaced = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9323) wm_low.vsc = radeon_crtc->vsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9324) wm_low.vtaps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9325) if (radeon_crtc->rmx_type != RMX_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9326) wm_low.vtaps = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9327) wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9328) wm_low.lb_size = lb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9329) wm_low.dram_channels = cik_get_number_of_dram_channels(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9330) wm_low.num_heads = num_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9332) /* set for low clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9333) latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9335) /* possibly force display priority to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9336) /* should really do this at mode validation time... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9337) if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9338) !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9339) !dce8_check_latency_hiding(&wm_low) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9340) (rdev->disp_priority == 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9341) DRM_DEBUG_KMS("force priority to high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9344) /* Save number of lines the linebuffer leads before the scanout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9345) radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9348) /* select wm A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9349) wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9350) tmp = wm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9351) tmp &= ~LATENCY_WATERMARK_MASK(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9352) tmp |= LATENCY_WATERMARK_MASK(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9353) WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9354) WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9355) (LATENCY_LOW_WATERMARK(latency_watermark_a) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9356) LATENCY_HIGH_WATERMARK(line_time)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9357) /* select wm B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9358) tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9359) tmp &= ~LATENCY_WATERMARK_MASK(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9360) tmp |= LATENCY_WATERMARK_MASK(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9361) WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9362) WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9363) (LATENCY_LOW_WATERMARK(latency_watermark_b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9364) LATENCY_HIGH_WATERMARK(line_time)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9365) /* restore original selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9366) WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9368) /* save values for DPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9369) radeon_crtc->line_time = line_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9370) radeon_crtc->wm_high = latency_watermark_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9371) radeon_crtc->wm_low = latency_watermark_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9375) * dce8_bandwidth_update - program display watermarks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9377) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9379) * Calculate and program the display watermarks and line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9380) * buffer allocation (CIK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9382) void dce8_bandwidth_update(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9384) struct drm_display_mode *mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9385) u32 num_heads = 0, lb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9386) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9388) if (!rdev->mode_info.mode_config_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9389) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9391) radeon_update_display_priority(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9393) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9394) if (rdev->mode_info.crtcs[i]->base.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9395) num_heads++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9397) for (i = 0; i < rdev->num_crtc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9398) mode = &rdev->mode_info.crtcs[i]->base.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9399) lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9400) dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9405) * cik_get_gpu_clock_counter - return GPU clock counter snapshot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9407) * @rdev: radeon_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9409) * Fetches a GPU clock counter snapshot (SI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9410) * Returns the 64 bit clock counter snapshot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9412) uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9414) uint64_t clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9416) mutex_lock(&rdev->gpu_clock_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9417) WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9418) clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9419) ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9420) mutex_unlock(&rdev->gpu_clock_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9421) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9424) static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9425) u32 cntl_reg, u32 status_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9427) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9428) struct atom_clock_dividers dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9429) uint32_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9431) r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9432) clock, false, ÷rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9433) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9434) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9436) tmp = RREG32_SMC(cntl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9437) tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9438) tmp |= dividers.post_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9439) WREG32_SMC(cntl_reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9441) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9442) if (RREG32_SMC(status_reg) & DCLK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9444) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9446) if (i == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9447) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9452) int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9454) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9456) r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9457) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9458) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9460) r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9461) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9464) int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9466) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9467) struct atom_clock_dividers dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9468) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9470) r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9471) ecclk, false, ÷rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9472) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9473) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9475) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9476) if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9478) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9480) if (i == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9481) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9483) tmp = RREG32_SMC(CG_ECLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9484) tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9485) tmp |= dividers.post_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9486) WREG32_SMC(CG_ECLK_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9488) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9489) if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9491) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9493) if (i == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9494) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9499) static void cik_pcie_gen3_enable(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9501) struct pci_dev *root = rdev->pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9502) enum pci_bus_speed speed_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9503) u32 speed_cntl, current_data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9504) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9505) u16 tmp16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9507) if (pci_is_root_bus(rdev->pdev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9508) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9510) if (radeon_pcie_gen2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9513) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9514) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9516) if (!(rdev->flags & RADEON_IS_PCIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9519) speed_cap = pcie_get_speed_cap(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9520) if (speed_cap == PCI_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9523) if ((speed_cap != PCIE_SPEED_8_0GT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9524) (speed_cap != PCIE_SPEED_5_0GT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9525) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9527) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9528) current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9529) LC_CURRENT_DATA_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9530) if (speed_cap == PCIE_SPEED_8_0GT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9531) if (current_data_rate == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9532) DRM_INFO("PCIE gen 3 link speeds already enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9533) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9535) DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9536) } else if (speed_cap == PCIE_SPEED_5_0GT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9537) if (current_data_rate == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9538) DRM_INFO("PCIE gen 2 link speeds already enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9541) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9544) if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9545) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9547) if (speed_cap == PCIE_SPEED_8_0GT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9548) /* re-try equalization if gen3 is not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9549) if (current_data_rate != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9550) u16 bridge_cfg, gpu_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9551) u16 bridge_cfg2, gpu_cfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9552) u32 max_lw, current_lw, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9554) pcie_capability_read_word(root, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9555) &bridge_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9556) pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9557) &gpu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9559) tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9560) pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9562) tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9563) pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9564) tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9566) tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9567) max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9568) current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9570) if (current_lw < max_lw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9571) tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9572) if (tmp & LC_RENEGOTIATION_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9573) tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9574) tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9575) tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9576) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9580) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9581) /* check status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9582) pcie_capability_read_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9583) PCI_EXP_DEVSTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9584) &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9585) if (tmp16 & PCI_EXP_DEVSTA_TRPND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9588) pcie_capability_read_word(root, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9589) &bridge_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9590) pcie_capability_read_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9591) PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9592) &gpu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9594) pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9595) &bridge_cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9596) pcie_capability_read_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9597) PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9598) &gpu_cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9600) tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9601) tmp |= LC_SET_QUIESCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9602) WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9604) tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9605) tmp |= LC_REDO_EQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9606) WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9608) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9610) /* linkctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9611) pcie_capability_read_word(root, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9612) &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9613) tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9614) tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9615) pcie_capability_write_word(root, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9616) tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9618) pcie_capability_read_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9619) PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9620) &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9621) tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9622) tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9623) pcie_capability_write_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9624) PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9625) tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9627) /* linkctl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9628) pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9629) &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9630) tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9631) PCI_EXP_LNKCTL2_TX_MARGIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9632) tmp16 |= (bridge_cfg2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9633) (PCI_EXP_LNKCTL2_ENTER_COMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9634) PCI_EXP_LNKCTL2_TX_MARGIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9635) pcie_capability_write_word(root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9636) PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9637) tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9639) pcie_capability_read_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9640) PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9641) &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9642) tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9643) PCI_EXP_LNKCTL2_TX_MARGIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9644) tmp16 |= (gpu_cfg2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9645) (PCI_EXP_LNKCTL2_ENTER_COMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9646) PCI_EXP_LNKCTL2_TX_MARGIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9647) pcie_capability_write_word(rdev->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9648) PCI_EXP_LNKCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9649) tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9651) tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9652) tmp &= ~LC_SET_QUIESCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9653) WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9658) /* set the link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9659) speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9660) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9661) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9663) pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9664) tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9665) if (speed_cap == PCIE_SPEED_8_0GT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9666) tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9667) else if (speed_cap == PCIE_SPEED_5_0GT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9668) tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9670) tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9671) pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9673) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9674) speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9675) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9677) for (i = 0; i < rdev->usec_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9678) speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9679) if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9681) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9685) static void cik_program_aspm(struct radeon_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9687) u32 data, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9688) bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9689) bool disable_clkreq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9691) if (radeon_aspm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9694) /* XXX double check IGPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9695) if (rdev->flags & RADEON_IS_IGP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9698) if (!(rdev->flags & RADEON_IS_PCIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9699) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9701) orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9702) data &= ~LC_XMIT_N_FTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9703) data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9704) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9705) WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9707) orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9708) data |= LC_GO_TO_RECOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9709) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9710) WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9712) orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9713) data |= P_IGNORE_EDB_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9714) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9715) WREG32_PCIE_PORT(PCIE_P_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9717) orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9718) data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9719) data |= LC_PMI_TO_L1_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9720) if (!disable_l0s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9721) data |= LC_L0S_INACTIVITY(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9723) if (!disable_l1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9724) data |= LC_L1_INACTIVITY(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9725) data &= ~LC_PMI_TO_L1_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9726) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9727) WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9729) if (!disable_plloff_in_l1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9730) bool clk_req_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9732) orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9733) data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9734) data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9735) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9736) WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9738) orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9739) data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9740) data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9741) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9742) WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9744) orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9745) data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9746) data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9747) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9748) WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9750) orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9751) data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9752) data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9753) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9754) WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9756) orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9757) data &= ~LC_DYN_LANES_PWR_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9758) data |= LC_DYN_LANES_PWR_STATE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9759) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9760) WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9762) if (!disable_clkreq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9763) !pci_is_root_bus(rdev->pdev->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9764) struct pci_dev *root = rdev->pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9765) u32 lnkcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9767) clk_req_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9768) pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9769) if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9770) clk_req_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9772) clk_req_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9775) if (clk_req_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9776) orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9777) data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9778) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9779) WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9781) orig = data = RREG32_SMC(THM_CLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9782) data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9783) data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9784) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9785) WREG32_SMC(THM_CLK_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9787) orig = data = RREG32_SMC(MISC_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9788) data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9789) data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9790) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9791) WREG32_SMC(MISC_CLK_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9793) orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9794) data &= ~BCLK_AS_XCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9795) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9796) WREG32_SMC(CG_CLKPIN_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9798) orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9799) data &= ~FORCE_BIF_REFCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9800) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9801) WREG32_SMC(CG_CLKPIN_CNTL_2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9803) orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9804) data &= ~MPLL_CLKOUT_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9805) data |= MPLL_CLKOUT_SEL(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9806) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9807) WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9811) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9812) WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9815) orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9816) data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9817) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9818) WREG32_PCIE_PORT(PCIE_CNTL2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9820) if (!disable_l0s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9821) data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9822) if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9823) data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9824) if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9825) orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9826) data &= ~LC_L0S_INACTIVITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9827) if (orig != data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9828) WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9832) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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