^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2010 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Authors: Alex Deucher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef _BTCD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _BTCD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* pm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GENERAL_PWRMGT 0x63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # define GLOBAL_PWRMGT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define STATIC_PM_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define THERMAL_PROTECTION_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define THERMAL_PROTECTION_TYPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define ENABLE_GEN2PCIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define ENABLE_GEN2XSP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define SW_SMIO_INDEX(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define SW_SMIO_INDEX_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define SW_SMIO_INDEX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define LOW_VOLT_D2_ACPI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define LOW_VOLT_D3_ACPI (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define VOLT_PWRMGT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define BACKBIAS_PAD_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define BACKBIAS_VALUE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define AC_DC_SW (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define CURRENT_PROFILE_INDEX_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define CURRENT_PROFILE_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CG_BIF_REQ_AND_RSP 0x7f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CG_CLIENT_REQ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CG_CLIENT_REQ_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CG_CLIENT_REQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CG_CLIENT_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CG_CLIENT_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CG_CLIENT_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLIENT_CG_REQ(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLIENT_CG_REQ_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLIENT_CG_REQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLIENT_CG_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLIENT_CG_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLIENT_CG_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCLK_PSKIP_CNTL 0x8c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CG_ULV_CONTROL 0x8c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CG_ULV_PARAMETER 0x8cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC_ARB_DRAM_TIMING 0x2774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MC_ARB_DRAM_TIMING2 0x2778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MC_ARB_RFSH_RATE 0x27b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define POWERMODE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define POWERMODE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define POWERMODE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define POWERMODE1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define POWERMODE1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define POWERMODE1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define POWERMODE2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define POWERMODE2_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define POWERMODE2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define POWERMODE3(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define POWERMODE3_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define POWERMODE3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MC_ARB_BURST_TIME 0x2808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STATE0(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STATE0_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STATE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STATE1(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STATE1_MASK (0x1f << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STATE1_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STATE2(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATE2_MASK (0x1f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STATE2_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STATE3(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATE3_MASK (0x1f << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STATE3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MC_SEQ_RAS_TIMING 0x28a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MC_SEQ_CAS_TIMING 0x28a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MC_SEQ_MISC_TIMING 0x28a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MC_SEQ_MISC_TIMING2 0x28ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MC_SEQ_RD_CTL_D0 0x28b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MC_SEQ_RD_CTL_D1 0x28b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MC_SEQ_WR_CTL_D0 0x28bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MC_SEQ_WR_CTL_D1 0x28c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MC_PMG_AUTO_CFG 0x28d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MC_SEQ_STATUS_M 0x29f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define PMG_PWRSTATE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MC_SEQ_MISC0 0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MC_SEQ_MISC0_GDDR5_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MC_SEQ_MISC0_GDDR5_VALUE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MC_SEQ_MISC1 0x2a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MC_SEQ_RESERVE_M 0x2a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MC_PMG_CMD_EMRS 0x2a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MC_SEQ_MISC3 0x2a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MC_SEQ_MISC5 0x2a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MC_SEQ_MISC6 0x2a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MC_SEQ_MISC7 0x2a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MC_SEQ_CG 0x2a68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CG_SEQ_REQ(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CG_SEQ_REQ_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CG_SEQ_REQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CG_SEQ_RESP(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CG_SEQ_RESP_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CG_SEQ_RESP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SEQ_CG_REQ(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SEQ_CG_REQ_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SEQ_CG_REQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SEQ_CG_RESP(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SEQ_CG_RESP_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SEQ_CG_RESP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MC_SEQ_RAS_TIMING_LP 0x2a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MC_SEQ_CAS_TIMING_LP 0x2a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MC_SEQ_MISC_TIMING_LP 0x2a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MC_SEQ_MISC_TIMING2_LP 0x2a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MC_SEQ_WR_CTL_D1_LP 0x2a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MC_PMG_CMD_MRS 0x2aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MC_SEQ_RD_CTL_D1_LP 0x2b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MC_PMG_CMD_MRS1 0x2b44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LB_SYNC_RESET_SEL 0x6b28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LB_SYNC_RESET_SEL_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LB_SYNC_RESET_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* PCIE link stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define LC_GEN2_EN_STRAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define LC_CURRENT_DATA_RATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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