^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2006-2007 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*Portion I: Definitions shared between VBIOS and Driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifndef _ATOMBIOS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _ATOMBIOS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ATOM_VERSION_MAJOR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATOM_VERSION_MINOR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Endianness should be specified before inclusion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * default to little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifndef ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #error Endian not specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef _H2INC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef ULONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) typedef unsigned long ULONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #ifndef UCHAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) typedef unsigned char UCHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifndef USHORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) typedef unsigned short USHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATOM_DAC_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATOM_DAC_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATOM_EXT_DAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATOM_CRTC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATOM_CRTC2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATOM_CRTC3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ATOM_CRTC4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ATOM_CRTC5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ATOM_CRTC6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ATOM_CRTC_INVALID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ATOM_DIGA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ATOM_DIGB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ATOM_PPLL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATOM_PPLL2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ATOM_DCPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ATOM_PPLL0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ATOM_PPLL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ATOM_EXT_PLL1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ATOM_EXT_PLL2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ATOM_EXT_CLOCK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ATOM_PPLL_INVALID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ENCODER_REFCLK_SRC_P1PLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ENCODER_REFCLK_SRC_P2PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ENCODER_REFCLK_SRC_DCPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ENCODER_REFCLK_SRC_EXTCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ENCODER_REFCLK_SRC_INVALID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ATOM_SCALER1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ATOM_SCALER2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ATOM_SCALER_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ATOM_SCALER_CENTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ATOM_SCALER_EXPANSION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ATOM_SCALER_MULTI_EX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ATOM_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ATOM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ATOM_LCD_BLON (ATOM_ENABLE+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ATOM_INIT (ATOM_DISABLE+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ATOM_GET_STATUS (ATOM_DISABLE+8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ATOM_BLANKING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ATOM_BLANKING_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ATOM_CURSOR1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ATOM_CURSOR2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ATOM_ICON1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ATOM_ICON2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ATOM_CRT1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ATOM_CRT2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ATOM_TV_NTSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ATOM_TV_NTSCJ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ATOM_TV_PAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ATOM_TV_PALM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ATOM_TV_PALCN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ATOM_TV_PALN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ATOM_TV_PAL60 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATOM_TV_SECAM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ATOM_TV_CV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ATOM_DAC1_PS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ATOM_DAC1_CV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ATOM_DAC1_NTSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ATOM_DAC1_PAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATOM_DAC2_PS2 ATOM_DAC1_PS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ATOM_DAC2_CV ATOM_DAC1_CV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATOM_DAC2_PAL ATOM_DAC1_PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ATOM_PM_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ATOM_PM_STANDBY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ATOM_PM_SUSPEND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ATOM_PM_OFF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Bit0:{=0:single, =1:dual},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) Bit1 {=0:666RGB, =1:888RGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Bit2:3:{Grey level}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ATOM_PANEL_MISC_DUAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ATOM_PANEL_MISC_888RGB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ATOM_PANEL_MISC_FPDI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ATOM_PANEL_MISC_SPATIAL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ATOM_PANEL_MISC_TEMPORAL 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ATOM_PANEL_MISC_API_ENABLED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MEMTYPE_DDR1 "DDR1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MEMTYPE_DDR2 "DDR2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MEMTYPE_DDR3 "DDR3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MEMTYPE_DDR4 "DDR4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ASIC_BUS_TYPE_PCI "PCI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ASIC_BUS_TYPE_AGP "AGP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Maximum size of that FireGL flag string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HW_ASSISTED_I2C_STATUS_FAILURE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #pragma pack(1) /* BIOS data must use byte alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Define offset to location of ROM header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Common header for all ROM Data tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) And the pointer actually points to this header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) typedef struct _ATOM_COMMON_TABLE_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) USHORT usStructureSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*Image can't be updated, while Driver needs to carry the new table! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }ATOM_COMMON_TABLE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) // Structure stores the ROM header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) typedef struct _ATOM_ROM_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) atombios should init it as "ATOM", don't change the position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) USHORT usBiosRuntimeSegmentAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) USHORT usProtectedModeInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) USHORT usConfigFilenameOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) USHORT usCRC_BlockOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) USHORT usBIOS_BootupMessageOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) USHORT usInt10Offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) USHORT usPciBusDevInitCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) USHORT usIoBaseAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) USHORT usSubsystemVendorID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) USHORT usSubsystemID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) USHORT usPCI_InfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) UCHAR ucExtendedFunctionCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }ATOM_ROM_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*==============================Command Table Portion==================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef UEFI_BUILD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define UTEMP USHORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define USHORT void*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) // Structures used in Command.mtb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) USHORT DIGxEncoderControl; //Only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) USHORT GPIOPinControl; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) USHORT MemoryPLLInit; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) USHORT SetUniphyInstance; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) USHORT GetConditionalGoldenSetting; //Only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) USHORT PatchMCSetting; //only used by BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) USHORT MC_SEQ_Control; //only used by BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) USHORT EnableScaler; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) USHORT LUT_AutoFill; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) USHORT MemoryCleanUp; //Atomic Table, only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) USHORT MemoryTraining; //Atomic Table, used only by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) USHORT DPEncoderService; //Function Table,only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) // For backward compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DPTranslatorControl DIG2EncoderControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define UNIPHYTransmitterControl DIG1TransmitterControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define LVTMATransmitterControl DIG2TransmitterControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SetCRTC_DPM_State GetConditionalGoldenSetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HPDInterruptService ReadHWAssistedI2CStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define EnableVGA_Access GetSCLKOverMCLKRatio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define EnableYUV GetDispObjectInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DynamicClockGating EnableDispPowerGating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SetupHWAssistedI2CStatus ComputeMemoryClockParam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TMDSAEncoderControl PatchMCSetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define LVDSEncoderControl MC_SEQ_Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define LCD1OutputControl HW_Misc_Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TV1OutputControl Gfx_Harvesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) typedef struct _ATOM_MASTER_COMMAND_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }ATOM_MASTER_COMMAND_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) // Structures used in every command table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) typedef struct _ATOM_TABLE_ATTRIBUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }ATOM_TABLE_ATTRIBUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ATOM_TABLE_ATTRIBUTE sbfAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) USHORT susAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }ATOM_TABLE_ATTRIBUTE_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) // Common header for all command tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) // And the pointer actually points to this header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ATOM_COMMON_TABLE_HEADER CommonHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ATOM_TABLE_ATTRIBUTE TableAttribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) // Structures used by ComputeMemoryEnginePLLTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define COMPUTE_MEMORY_PLL_PARAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define COMPUTE_ENGINE_PLL_PARAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ADJUST_MC_SETTING_PARAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) // Structures used by AdjustMemoryControllerTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ULONG ulClockFreq:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ULONG ulClockFreq:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define POINTER_RETURN_FLAG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) UCHAR ucAction; //0:reserved //1:Memory //2:Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) UCHAR ucReserved; //may expand to return larger Fbdiv later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) UCHAR ucFbDiv; //return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) UCHAR ucPostDiv; //return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ULONG ulClock; //When return, [23:0] return real clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) USHORT usFbDiv; //return Feedback value to be written to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) UCHAR ucPostDiv; //return post div to be written to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) typedef struct _ATOM_COMPUTE_CLOCK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ULONG ulClockFreq:24; // in unit of 10kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ULONG ulClockFreq:24; // in unit of 10kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }ATOM_COMPUTE_CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) typedef struct _ATOM_S_MPLL_FB_DIVIDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) USHORT usFbDivFrac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) USHORT usFbDiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }ATOM_S_MPLL_FB_DIVIDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ULONG ulClockParams; //ULONG access for BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) UCHAR ucRefDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) UCHAR ucPostDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) UCHAR ucCntlFlag; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) // ucCntlFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) // V4 are only used for APU which PLL outside GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ULONG ulClock:24; //Input= target clock, output = actual clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ULONG ulClock:24; //Input= target clock, output = actual clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ULONG ulClockParams; //ULONG access for BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) UCHAR ucRefDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) UCHAR ucPostDiv; //Output Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) UCHAR ucCntlFlag; //Output Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ULONG ulReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) UCHAR ucPllCntlFlag; //Output Flags: control flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) //ucPllCntlFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) // ucInputFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) // use for ComputeMemoryClockParamTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ULONG ulClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) UCHAR ucDllSpeed; //Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) UCHAR ucPostDiv; //Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) UCHAR ucPllCntlFlag; //Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) UCHAR ucBWCntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) // definition of ucInputFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) // definition of ucPllCntlFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ATOM_COMPUTE_CLOCK_FREQ ulClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ULONG ulReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ATOM_COMPUTE_CLOCK_FREQ ulClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ULONG ulMemoryClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) // Structures used by SetEngineClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) typedef struct _SET_ENGINE_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ULONG ulTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }SET_ENGINE_CLOCK_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ULONG ulTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }SET_ENGINE_CLOCK_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) // Structures used by SetMemoryClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) typedef struct _SET_MEMORY_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ULONG ulTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }SET_MEMORY_CLOCK_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ULONG ulTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }SET_MEMORY_CLOCK_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) // Structures used by ASIC_Init.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) typedef struct _ASIC_INIT_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }ASIC_INIT_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) typedef struct _ASIC_INIT_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ASIC_INIT_PARAMETERS sASICInitClocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }ASIC_INIT_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) // Structure used by DynamicClockGatingTable.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }DYNAMIC_CLOCK_GATING_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) // Structure used by EnableDispPowerGatingTable.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) // Structure used by EnableASIC_StaticPwrMgtTable.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) // Structures used by DAC_LoadDetectionTable.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) typedef struct _DAC_LOAD_DETECTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) UCHAR ucMisc; //Valid only when table revision =1.3 and above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }DAC_LOAD_DETECTION_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DAC_LOAD_MISC_YPrPb 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) DAC_LOAD_DETECTION_PARAMETERS sDacload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }DAC_LOAD_DETECTION_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) UCHAR ucAction; // 0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) // 1: setup and turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) // 7: ATOM_ENCODER_INIT Initialize DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }DAC_ENCODER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) // Structures used by DIG1EncoderControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) // DIG2EncoderControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) // ExternalEncoderControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) // [2] Link Select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) // =0: PHY linkA if bfLane<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) // =1: PHY linkB if bfLanes<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) // =0: PHY linkA+B if bfLanes=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) // [3] Transmitter Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) // =0: UNIPHY or PCIEPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) // =1: LVTMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) UCHAR ucAction; // =0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) // =1: turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) UCHAR ucEncoderMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) // =0: DP encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) // =1: LVDS encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) // =2: DVI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) // =3: HDMI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) // =4: SDVO encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) UCHAR ucLaneNum; // how many lanes to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }DIG_ENCODER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define ATOM_ENCODER_CONFIG_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define ATOM_ENCODER_CONFIG_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define ATOM_ENCODER_CONFIG_UNIPHY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define ATOM_ENCODER_CONFIG_LVTMA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) // ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) // ATOM_ENABLE: Enable Encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) // ATOM_DISABLE: Disable Encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) //ucEncoderMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ATOM_ENCODER_MODE_DP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define ATOM_ENCODER_MODE_LVDS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define ATOM_ENCODER_MODE_DVI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define ATOM_ENCODER_MODE_HDMI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define ATOM_ENCODER_MODE_SDVO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define ATOM_ENCODER_MODE_DP_AUDIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define ATOM_ENCODER_MODE_TV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define ATOM_ENCODER_MODE_CV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define ATOM_ENCODER_MODE_CRT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define ATOM_ENCODER_MODE_DVO 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) UCHAR ucReserved1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) UCHAR ucReserved1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }ATOM_DIG_ENCODER_CONFIG_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) UCHAR ucEncoderMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) // =0: DP encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) // =1: LVDS encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) // =2: DVI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) // =3: HDMI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) // =4: SDVO encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) UCHAR ucLaneNum; // how many lanes to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }DIG_ENCODER_CONTROL_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) // ucAction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) // ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) // ATOM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define ATOM_ENCODER_CMD_SETUP 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) // ucStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) //ucTableContentRevision=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) UCHAR ucReserved1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) UCHAR ucReserved:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) UCHAR ucReserved:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) UCHAR ucReserved1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }ATOM_DIG_ENCODER_CONFIG_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) UCHAR ucEncoderMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) // =0: DP encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) // =1: LVDS encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) // =2: DVI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) // =3: HDMI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) // =4: SDVO encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) // =5: DP audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) // =0: external DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) // =1: internal DP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) // =0x11: internal DP1 for NutMeg/Travis DP translator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) UCHAR ucLaneNum; // how many lanes to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }DIG_ENCODER_CONTROL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) //ucTableContentRevision=4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) // start from NI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) UCHAR ucReserved1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) UCHAR ucReserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) UCHAR ucReserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) UCHAR ucReserved1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }ATOM_DIG_ENCODER_CONFIG_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) UCHAR ucEncoderMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) // =0: DP encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) // =1: LVDS encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) // =2: DVI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) // =3: HDMI encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) // =4: SDVO encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) // =5: DP audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) // =0: external DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) // =1: internal DP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) // =0x11: internal DP1 for NutMeg/Travis DP translator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) UCHAR ucLaneNum; // how many lanes to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }DIG_ENCODER_CONTROL_PARAMETERS_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) // define ucBitPerColor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define PANEL_BPC_UNDEFINE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define PANEL_6BIT_PER_COLOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define PANEL_8BIT_PER_COLOR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define PANEL_10BIT_PER_COLOR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define PANEL_12BIT_PER_COLOR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define PANEL_16BIT_PER_COLOR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) //define ucPanelMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) // Structures used by UNIPHYTransmitterControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) // LVTMATransmitterControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) // DVOOutputControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) typedef struct _ATOM_DP_VS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) UCHAR ucLaneSel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) UCHAR ucLaneSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }ATOM_DP_VS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) // [0]=0: 4 lane Link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) // =1: 8 lane Link ( Dual Links TMDS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) // [1]=0: InCoherent mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) // =1: Coherent Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) // [2] Link Select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) // =0: PHY linkA if bfLane<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) // =1: PHY linkB if bfLanes<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) // =0: PHY linkA+B if bfLanes=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) // [5:4]PCIE lane Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) // =0: lane 0~3 or 0~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) // =1: lane 4~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) // =2: lane 8~11 or 8~15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) // =3: lane 12~15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) UCHAR ucAction; // =0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) // =1: turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) UCHAR ucReserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }DIG_TRANSMITTER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) //ucInitInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) //ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define ATOM_TRANSMITTER_ACTION_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define ATOM_TRANSMITTER_ACTION_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define ATOM_TRANSMITTER_ACTION_INIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define ATOM_TRANSMITTER_ACTION_SETUP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define ATOM_TRANSMITTER_ACTION_POWER_ON 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) // Following are used for DigTransmitterControlTable ver1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }ATOM_DIG_TRANSMITTER_CONFIG_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) //Bit0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) //Bit1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) //Bit2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) // Bit3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) // Bit4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) // Bit7:6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) UCHAR ucReserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }ATOM_DIG_TRANSMITTER_CONFIG_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) UCHAR ucLaneNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) //Bit0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) //Bit1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) //Bit2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) // Bit3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) // Bit5:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) // Bit7:6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) // Structures used by UNIPHYTransmitterControlTable V1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) // ASIC Families: NI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) // ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) // ucTableContentRevision=4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) typedef struct _ATOM_DP_VS_MODE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) UCHAR ucLaneSel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) UCHAR ucLaneSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }ATOM_DP_VS_MODE_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) // =1 Dig Transmitter 2 ( Uniphy CD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) // =2 Dig Transmitter 3 ( Uniphy EF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }ATOM_DIG_TRANSMITTER_CONFIG_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) UCHAR ucLaneNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) //ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) //Bit0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) //Bit1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) //Bit2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) // Bit3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) // Bit5:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) // Bit7:6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) UCHAR ucReservd1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) UCHAR ucHPDSel:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) UCHAR ucPhyClkSrcId:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) UCHAR ucCoherentMode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) UCHAR ucReserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) UCHAR ucCoherentMode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) UCHAR ucPhyClkSrcId:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) UCHAR ucHPDSel:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) UCHAR ucReservd1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }ATOM_DIG_TRANSMITTER_CONFIG_V5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) UCHAR ucLaneNum; // indicate lane number 1-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) UCHAR ucDigMode; // indicate DIG mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) UCHAR ucDigEncoderSel; // indicate DIG front end encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) UCHAR ucDPLaneSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) UCHAR ucReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) //ucPhyId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define ATOM_PHY_ID_UNIPHYA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define ATOM_PHY_ID_UNIPHYB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define ATOM_PHY_ID_UNIPHYC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define ATOM_PHY_ID_UNIPHYD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define ATOM_PHY_ID_UNIPHYE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define ATOM_PHY_ID_UNIPHYF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define ATOM_PHY_ID_UNIPHYG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) // ucDigEncoderSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) // ucDigMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) // ucDPLaneSet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define DP_LANE_SET__0DB_0_4V 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define DP_LANE_SET__0DB_0_6V 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define DP_LANE_SET__0DB_0_8V 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define DP_LANE_SET__0DB_1_2V 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define DP_LANE_SET__3_5DB_0_4V 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define DP_LANE_SET__3_5DB_0_6V 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define DP_LANE_SET__3_5DB_0_8V 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define DP_LANE_SET__6DB_0_4V 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define DP_LANE_SET__6DB_0_6V 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define DP_LANE_SET__9_5DB_0_4V 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) // Bit1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) // Bit3:2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) // Bit6:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) // Structures used by ExternalEncoderControlTable V1.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) // ASIC Families: Evergreen, Llano, NI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) // ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) // ucTableContentRevision=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) USHORT usConnectorId; // connector id, valid when ucAction = INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) UCHAR ucAction; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) // ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) // ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ULONG ulReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) // Structures used by DAC1OuputControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) // DAC2OuputControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) // LVTMAOutputControlTable (Before DEC30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) // TMDSAOutputControlTable (Before DEC30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) // When the display is LCD, in addition to above:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) // ATOM_LCD_SELFTEST_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) UCHAR aucPadding[3]; // padding to DWORD aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) // Structures used by BlankCRTCTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) typedef struct _BLANK_CRTC_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) USHORT usBlackColorRCr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) USHORT usBlackColorGY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) USHORT usBlackColorBCb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }BLANK_CRTC_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) // Structures used by EnableCRTCTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) // EnableCRTCMemReqTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) // UpdateCRTC_DoubleBufferRegistersTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) typedef struct _ENABLE_CRTC_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }ENABLE_CRTC_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) // Structures used by SetCRTC_OverScanTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) USHORT usOverscanRight; // right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) USHORT usOverscanLeft; // left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) USHORT usOverscanBottom; // bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) USHORT usOverscanTop; // top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }SET_CRTC_OVERSCAN_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) // Structures used by SetCRTC_ReplicationTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) typedef struct _SET_CRTC_REPLICATION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) UCHAR ucH_Replication; // horizontal replication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) UCHAR ucV_Replication; // vertical replication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) UCHAR ucPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }SET_CRTC_REPLICATION_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) // Structures used by SelectCRTC_SourceTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }SELECT_CRTC_SOURCE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) UCHAR ucPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }SELECT_CRTC_SOURCE_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) //ucEncoderID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) //#define ASIC_INT_DAC1_ENCODER_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) //#define ASIC_INT_TV_ENCODER_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) //#define ASIC_INT_DIG1_ENCODER_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) //#define ASIC_INT_DAC2_ENCODER_ID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) //#define ASIC_EXT_TV_ENCODER_ID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) //#define ASIC_INT_DVO_ENCODER_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) //#define ASIC_INT_DIG2_ENCODER_ID 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) //#define ASIC_EXT_DIG_ENCODER_ID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) //ucEncodeMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) //#define ATOM_ENCODER_MODE_DP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) //#define ATOM_ENCODER_MODE_LVDS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) //#define ATOM_ENCODER_MODE_DVI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) //#define ATOM_ENCODER_MODE_HDMI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) //#define ATOM_ENCODER_MODE_SDVO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) //#define ATOM_ENCODER_MODE_TV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) //#define ATOM_ENCODER_MODE_CV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) //#define ATOM_ENCODER_MODE_CRT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) // Structures used by SetPixelClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) // GetPixelClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) //Major revision=1., Minor revision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) typedef struct _PIXEL_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) // 0 means disable PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) USHORT usRefDiv; // Reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) USHORT usFbDiv; // feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) UCHAR ucPostDiv; // post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) UCHAR ucFracFbDiv; // fractional feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) UCHAR ucCRTC; // Which CRTC uses this Ppll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) UCHAR ucPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }PIXEL_CLOCK_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) //Major revision=1., Minor revision=2, add ucMiscIfno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) //ucMiscInfo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define MISC_DEVICE_INDEX_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define MISC_DEVICE_INDEX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) typedef struct _PIXEL_CLOCK_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) // 0 means disable PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) USHORT usRefDiv; // Reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) USHORT usFbDiv; // feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) UCHAR ucPostDiv; // post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) UCHAR ucFracFbDiv; // fractional feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) UCHAR ucCRTC; // Which CRTC uses this Ppll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }PIXEL_CLOCK_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) //Major revision=1., Minor revision=3, structure/definition change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) //ucEncoderMode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) //ATOM_ENCODER_MODE_DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) //ATOM_ENOCDER_MODE_LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) //ATOM_ENOCDER_MODE_DVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) //ATOM_ENOCDER_MODE_HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) //ATOM_ENOCDER_MODE_SDVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) //ATOM_ENCODER_MODE_TV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) //ATOM_ENCODER_MODE_CV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) //ATOM_ENCODER_MODE_CRT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) //ucDVOConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) //#define DVO_ENCODER_CONFIG_24BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) //ucMiscInfo: also changed, see below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define PIXEL_CLOCK_MISC_VGA_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) // V1.4 for RoadRunner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) typedef struct _PIXEL_CLOCK_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) USHORT usRefDiv; // Reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) USHORT usFbDiv; // feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) UCHAR ucPostDiv; // post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) UCHAR ucFracFbDiv; // fractional feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }PIXEL_CLOCK_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) typedef struct _PIXEL_CLOCK_PARAMETERS_V5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) // drive the pixel clock. not used for DCPLL case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) // 0 means disable PPLL/DCPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) USHORT usFbDiv; // feedback divider integer part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) UCHAR ucPostDiv; // post divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) UCHAR ucRefDiv; // Reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) // indicate which graphic encoder will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) UCHAR ucEncoderMode; // Encoder mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) UCHAR ucMiscInfo; // bit[0]= Force program PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) // bit[1]= when VGA timing is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) // bit[4]= RefClock source for PPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) // =0: XTLAIN( default mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) // =1: other external clock source, which is pre-defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) // by VBIOS depend on the feature required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) // bit[7:5]: reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }PIXEL_CLOCK_PARAMETERS_V5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) typedef struct _CRTC_PIXEL_CLOCK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) // drive the pixel clock. not used for DCPLL case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) // drive the pixel clock. not used for DCPLL case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }CRTC_PIXEL_CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) typedef struct _PIXEL_CLOCK_PARAMETERS_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ULONG ulDispEngClkFreq; // dispclk frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) USHORT usFbDiv; // feedback divider integer part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) UCHAR ucPostDiv; // post divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) UCHAR ucRefDiv; // Reference divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) // indicate which graphic encoder will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) UCHAR ucEncoderMode; // Encoder mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) UCHAR ucMiscInfo; // bit[0]= Force program PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) // bit[1]= when VGA timing is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) // bit[4]= RefClock source for PPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) // =0: XTLAIN( default mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) // =1: other external clock source, which is pre-defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) // by VBIOS depend on the feature required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) // bit[7:5]: reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }PIXEL_CLOCK_PARAMETERS_V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) UCHAR ucStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) // Structures used by AdjustDisplayPllTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) USHORT usPixelClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) UCHAR ucTransmitterID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) UCHAR ucEncodeMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) UCHAR ucConfig; //if none DVO, not defined yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }ADJUST_DISPLAY_PLL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) USHORT usPixelClock; // target pixel clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) UCHAR ucExtTransmitterID; // external encoder id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) // usDispPllConfig v1.2 for RoadRunner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) // Structures used by EnableYUVTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) typedef struct _ENABLE_YUV_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }ENABLE_YUV_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) // Structures used by GetMemoryClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) typedef struct _GET_MEMORY_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) } GET_MEMORY_CLOCK_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) // Structures used by GetEngineClockTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) typedef struct _GET_ENGINE_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) } GET_ENGINE_CLOCK_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) // Following Structures and constant may be obsolete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) //Maxium 8 bytes,the data read in will be placed in the parameter space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) USHORT usPrescale; //Ratio between Engine clock and I2C clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) UCHAR ucSlaveAddr; //Read from which slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) UCHAR ucLineNumber; //Read from which HW assisted line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) USHORT usPrescale; //Ratio between Engine clock and I2C clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) USHORT usByteOffset; //Write to which byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) //Upper portion of usByteOffset is Format of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) //1bytePS+offsetPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) //2bytesPS+offsetPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) //blockID+offsetPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) //blockID+offsetID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) //blockID+counterID+offsetID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) UCHAR ucData; //PS data1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) UCHAR ucSlaveAddr; //Write to which slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) UCHAR ucLineNumber; //Write from which HW assisted line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) USHORT usPrescale; //Ratio between Engine clock and I2C clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) UCHAR ucSlaveAddr; //Write to which slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) UCHAR ucLineNumber; //Write from which HW assisted line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }SET_UP_HW_I2C_DATA_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /**************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) // Structures used by PowerConnectorDetectionTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) UCHAR ucPwrBehaviorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) USHORT usPwrBudget; //how much power currently boot to in unit of watt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }POWER_CONNECTOR_DETECTION_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) USHORT usPwrBudget; //how much power currently boot to in unit of watt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /****************************LVDS SS Command Table Definitions**********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) // Structures used by EnableSpreadSpectrumOnPPLLTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) typedef struct _ENABLE_LVDS_SS_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) USHORT usSpreadSpectrumPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }ENABLE_LVDS_SS_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) //ucTableFormatRevision=1,ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) USHORT usSpreadSpectrumPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) UCHAR ucSpreadSpectrumStep; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) UCHAR ucSpreadSpectrumDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) UCHAR ucSpreadSpectrumRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) UCHAR ucPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }ENABLE_LVDS_SS_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) USHORT usSpreadSpectrumPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) UCHAR ucSpreadSpectrumStep; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) UCHAR ucSpreadSpectrumDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) UCHAR ucSpreadSpectrumRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) USHORT usSpreadSpectrumPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) // Bit[1]: 1-Ext. 0-Int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) // Bits[7:4] reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) // Used by DCE5.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) // Bit[1]: 1-Ext. 0-Int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) // Bits[7:4] reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /**************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) PIXEL_CLOCK_PARAMETERS sPCLKInput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }SET_PIXEL_CLOCK_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) // Structures used by ###
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) typedef struct _MEMORY_TRAINING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ULONG ulTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }MEMORY_TRAINING_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /****************************LVDS and other encoder command table definitions **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) // Structures used by LVDSEncoderControlTable (Before DCE30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) // LVTMAEncoderControlTable (Before DCE30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) // TMDSAEncoderControlTable (Before DCE30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) UCHAR ucMisc; // bit0=0: Enable single link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) // =1: Enable dual link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) // Bit1=0: 666RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) // =1: 888RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) UCHAR ucAction; // 0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) // 1: setup and turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }LVDS_ENCODER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) //ucTableFormatRevision=1,ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) UCHAR ucAction; // 0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) // 1: setup and turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) UCHAR ucTruncate; // bit0=0: Disable truncate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) // =1: Enable truncate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) // bit4=0: 666RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) // =1: 888RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) UCHAR ucSpatial; // bit0=0: Disable spatial dithering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) // =1: Enable spatial dithering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) // bit4=0: 666RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) // =1: 888RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) UCHAR ucTemporal; // bit0=0: Disable temporal dithering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) // =1: Enable temporal dithering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) // bit4=0: 666RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) // =1: 888RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) // bit5=0: Gray level 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) // =1: Gray level 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) // =1: 25FRC_SEL pattern F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) // bit6:5=0: 50FRC_SEL pattern A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) // =1: 50FRC_SEL pattern B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) // =2: 50FRC_SEL pattern C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) // =3: 50FRC_SEL pattern D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) // bit7=0: 75FRC_SEL pattern E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) // =1: 75FRC_SEL pattern F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) // Structures used by ###
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) UCHAR ucEnable; // Enable or Disable External TMDS encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) // Structures used by DVOEncoderControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) //ucTableFormatRevision=1,ucTableContentRevision=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) //ucDVOConfig:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define DVO_ENCODER_CONFIG_RATE_SEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define DVO_ENCODER_CONFIG_LOW12BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define DVO_ENCODER_CONFIG_24BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) USHORT usPixelClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) UCHAR ucDVOConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) UCHAR ucReseved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }DVO_ENCODER_CONTROL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) USHORT usPixelClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) UCHAR ucDVOConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) UCHAR ucReseved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) // bit1=0: non-coherent mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) // =1: coherent mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) //Only change is here next time when changing encoder parameter definitions again!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define PANEL_ENCODER_MISC_DUAL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define PANEL_ENCODER_MISC_COHERENT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define PANEL_ENCODER_TRUNCATE_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define PANEL_ENCODER_25FRC_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define PANEL_ENCODER_25FRC_E 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) #define PANEL_ENCODER_25FRC_F 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define PANEL_ENCODER_50FRC_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define PANEL_ENCODER_50FRC_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define PANEL_ENCODER_50FRC_B 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define PANEL_ENCODER_50FRC_C 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define PANEL_ENCODER_50FRC_D 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define PANEL_ENCODER_75FRC_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define PANEL_ENCODER_75FRC_E 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define PANEL_ENCODER_75FRC_F 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) // Structures used by SetVoltageTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define SET_VOLTAGE_INIT_MODE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) typedef struct _SET_VOLTAGE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) UCHAR ucVoltageIndex; // An index to tell which voltage level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }SET_VOLTAGE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) typedef struct _SET_VOLTAGE_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) USHORT usVoltageLevel; // real voltage level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }SET_VOLTAGE_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) // used by both SetVoltageTable v1.3 and v1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) UCHAR ucVoltageMode; // Indicate action: Set voltage level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }SET_VOLTAGE_PARAMETERS_V1_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) //ucVoltageType
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define VOLTAGE_TYPE_VDDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define VOLTAGE_TYPE_MVDDC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define VOLTAGE_TYPE_MVDDQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define VOLTAGE_TYPE_VDDCI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define ATOM_SET_VOLTAGE 0 //Set voltage Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) // define vitual voltage id in usVoltageLevel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) typedef struct _SET_VOLTAGE_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) SET_VOLTAGE_PARAMETERS sASICSetVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }SET_VOLTAGE_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) // New Added from SI for GetVoltageInfoTable, input parameter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ULONG ulVotlageGpioState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) ULONG ulVoltageGPioMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) USHORT usVoltageLevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ULONG ulReseved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) // GetVoltageInfo v1.1 ucVoltageMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define ATOM_GET_VOLTAGE_VID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) // New in GetVoltageInfo v1.2 ucVoltageMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) // New Added from CI Hawaii for EVV feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) USHORT usVoltageLevel; // real voltage level in unit of mv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ULONG ulReseved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) // Structures used by TVEncoderControlTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) typedef struct _TV_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) USHORT usPixelClock; // in 10KHz; for bios convenient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) UCHAR ucAction; // 0: turn off encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) // 1: setup and turn on encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }TV_ENCODER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }TV_ENCODER_CONTROL_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) //==============================Data Table Portion====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) // Structure used in Data.mtb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) USHORT StandardVESA_Timing; // Only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) USHORT PaletteData; // Only used by BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) USHORT SupportedDevicesInfo; // Will be obsolete from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) USHORT VESA_ToInternalModeLUT; // Only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) USHORT CompassionateData; // Will be obsolete from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) USHORT SaveRestoreInfo; // Only used by Bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) USHORT XTMDS_Info; // Will be obsolete from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) USHORT Object_Header; // Shared by various SW components,latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) USHORT MC_InitParameter; // Only used by command table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) USHORT ASIC_VDDC_Info; // Will be obsolete from R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) USHORT TV_VideoMode; // Only used by command table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) USHORT VRAM_Info; // Only used by command table, latest version 1.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) USHORT IntegratedSystemInfo; // Shared by various SW components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) }ATOM_MASTER_LIST_OF_DATA_TABLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) typedef struct _ATOM_MASTER_DATA_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }ATOM_MASTER_DATA_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) // For backward compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) #define LVDS_Info LCD_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) #define DAC_Info PaletteData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) #define TMDS_Info DIGTransmitterInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) // Structure used in MultimediaCapabilityInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ULONG ulSignature; // HW info table signature string "$ATI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) UCHAR ucVideoPortInfo; // Provides the video port capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) UCHAR ucHostPortInfo; // Provides host port configuration information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }ATOM_MULTIMEDIA_CAPABILITY_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) // Structure used in MultimediaConfigInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ULONG ulSignature; // MM info table signature sting "$MMT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }ATOM_MULTIMEDIA_CONFIG_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) // Structures used in FirmwareInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) // usBIOSCapability Definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) // Others: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) #ifndef _H2INC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) //Please don't add or expand this bitfield structure below, this one will retire soon.!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) typedef struct _ATOM_FIRMWARE_CAPABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) USHORT Reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) USHORT SCL2Redefined:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) USHORT PostWithoutModeSet:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) USHORT HyperMemory_Size:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) USHORT HyperMemory_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) USHORT PPMode_Assigned:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) USHORT WMI_SUPPORT:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) USHORT GPUControlsBL:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) USHORT EngineClockSS_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) USHORT MemoryClockSS_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) USHORT ExtendedDesktopSupport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) USHORT DualCRTC_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) USHORT FirmwarePosted:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) USHORT FirmwarePosted:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) USHORT DualCRTC_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) USHORT ExtendedDesktopSupport:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) USHORT MemoryClockSS_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) USHORT EngineClockSS_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) USHORT GPUControlsBL:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) USHORT WMI_SUPPORT:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) USHORT PPMode_Assigned:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) USHORT HyperMemory_Support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) USHORT HyperMemory_Size:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) USHORT PostWithoutModeSet:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) USHORT SCL2Redefined:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) USHORT Reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) }ATOM_FIRMWARE_CAPABILITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) ATOM_FIRMWARE_CAPABILITY sbfAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) USHORT susAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }ATOM_FIRMWARE_CAPABILITY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) USHORT susAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }ATOM_FIRMWARE_CAPABILITY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) typedef struct _ATOM_FIRMWARE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ULONG ulDriverTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ULONG ulDriverTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ULONG ulASICMaxEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ULONG ulASICMaxMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) UCHAR ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) UCHAR ucPadding[3]; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ULONG aulReservedForBIOS[3]; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) USHORT usMinEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) USHORT usMinEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) USHORT usReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) UCHAR ucDesign_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) }ATOM_FIRMWARE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) typedef struct _ATOM_FIRMWARE_INFO_V1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ULONG ulDriverTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ULONG ulDriverTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) ULONG ulASICMaxEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) ULONG ulASICMaxMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) UCHAR ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) UCHAR ucPadding[2]; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) ULONG aulReservedForBIOS[2]; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) USHORT usMinEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) USHORT usMinEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) USHORT usReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) UCHAR ucDesign_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) }ATOM_FIRMWARE_INFO_V1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) typedef struct _ATOM_FIRMWARE_INFO_V1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) ULONG ulDriverTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) ULONG ulDriverTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ULONG ulASICMaxEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ULONG ulASICMaxMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) UCHAR ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) UCHAR ucPadding[2]; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ULONG aulReservedForBIOS; //Don't use them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) ULONG ul3DAccelerationEngineClock;//In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) USHORT usMinEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) USHORT usMinEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) USHORT usReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) UCHAR ucDesign_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }ATOM_FIRMWARE_INFO_V1_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) typedef struct _ATOM_FIRMWARE_INFO_V1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ULONG ulDriverTargetEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ULONG ulDriverTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) ULONG ulASICMaxEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ULONG ulASICMaxMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) UCHAR ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) USHORT usBootUpVDDCVoltage; //In MV unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) ULONG ul3DAccelerationEngineClock;//In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) USHORT usMinEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) USHORT usMinEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) USHORT usReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) UCHAR ucDesign_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) }ATOM_FIRMWARE_INFO_V1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) //the structure below to be used from Cypress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) typedef struct _ATOM_FIRMWARE_INFO_V2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) ULONG ulReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) ULONG ulReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) UCHAR ucReserved1; //Was ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) USHORT usBootUpVDDCVoltage; //In MV unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ULONG ulReserved4; //Was ulAsicMaximumVoltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) USHORT usMinEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) USHORT usMinEngineClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) USHORT usCoreReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) USHORT usMemoryReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) UCHAR ucReserved4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }ATOM_FIRMWARE_INFO_V2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) //the structure below to be used from NI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) //ucTableFormatRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) //ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) typedef struct _ATOM_FIRMWARE_INFO_V2_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) ULONG ulFirmwareRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ULONG ulDefaultEngineClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ULONG ulDefaultMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) ULONG ulSPLL_OutputFreq; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) UCHAR ucReserved3; //Was ucASICMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) USHORT usBootUpVDDCVoltage; //In MV unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ULONG ulReserved4; //Was ulAsicMaximumVoltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) UCHAR ucRemoteDisplayConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) USHORT usMinPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) USHORT usCoreReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) USHORT usMemoryReferenceClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) UCHAR ucMemoryModule_ID; //Indicate what is the board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) UCHAR ucReserved9[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) USHORT usReserved12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) ULONG ulReserved10[3]; // New added comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }ATOM_FIRMWARE_INFO_V2_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) // definition of ucRemoteDisplayConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) #define REMOTE_DISPLAY_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) #define REMOTE_DISPLAY_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) // Structures used in IntegratedSystemInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #define IGP_CAP_FLAG_AC_CARD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) #define IGP_CAP_FLAG_SDVO_CARD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) ULONG ulBootUpEngineClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) ULONG ulBootUpMemoryClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) ULONG ulMaxSystemMemoryClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) ULONG ulMinSystemMemoryClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) UCHAR ucNumberOfCyclesInPeriodHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) USHORT usReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ULONG ulReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) USHORT usFSBClock; //In MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) //Bit[4]==1: P/2 mode, ==0: P/1 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) USHORT usK8MemoryClock; //in MHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) USHORT usK8SyncStartDelay; //in 0.01 us unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) USHORT usK8DataReturnTime; //in 0.01 us unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) UCHAR ucMaxNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) UCHAR ucMinNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) UCHAR ucMaxNBVoltageHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) UCHAR ucMinNBVoltageHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) }ATOM_INTEGRATED_SYSTEM_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) For AMD IGP,for now this can be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) For AMD IGP,for now this can be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) usFSBClock: For Intel IGP,it's FSB Freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) For AMD IGP,it's HT Link Speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) VC:Voltage Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) SW components can access the IGP system infor structure in the same way as before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) ULONG ulBootUpEngineClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) ULONG ulReserved1[2]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) ULONG ulBootUpUMAClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) ULONG ulBootUpSidePortClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) ULONG ulMinSidePortClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) ULONG ulReserved2[6]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) ULONG ulSystemConfig; //see explanation below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) ULONG ulBootUpReqDisplayVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) ULONG ulOtherDisplayMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) ULONG ulDDISlot1Config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) ULONG ulDDISlot2Config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) UCHAR ucUMAChannelNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) UCHAR ucDockingPinBit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) UCHAR ucDockingPinPolarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) ULONG ulDockingPinCFGInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) ULONG ulCPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) USHORT usNumberOfCyclesInPeriod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) USHORT usMaxNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) USHORT usMinNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) USHORT usBootUpNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) ULONG ulHTLinkFreq; //in 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) USHORT usMinHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) USHORT usMaxHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) USHORT usUMASyncStartDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) USHORT usUMADataReturnTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) USHORT usLinkStatusZeroTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) USHORT usDACEfuse; //for storing badgap value (for RS880 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) ULONG ulHighVoltageHTLinkFreq; // in 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) ULONG ulLowVoltageHTLinkFreq; // in 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) USHORT usMaxUpStreamHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) USHORT usMaxDownStreamHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) USHORT usMinUpStreamHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) USHORT usMinDownStreamHTLinkWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) ULONG ulReserved3[96]; //must be 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) }ATOM_INTEGRATED_SYSTEM_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) ulSystemConfig:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) =0: system boots up at driver control state. Power state depends on PowerPlay table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) Bit[3]=1: Only one power state(Performance) will be supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) =0: Multiple power states supported from PowerPlay table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) Bit[4]=1: CLMC is supported and enabled on current system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) =0: Voltage settings is determined by powerplay table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) Bit[8]=1: CDLF is supported and enabled on current system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) =0: CDLF is not supported or enabled on current system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) Bit[9]=1: DLL Shut Down feature is enabled on current system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) =0: DLL Shut Down feature is not enabled or supported on current system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) [15:8] - Lane configuration attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) [23:16]- Connector type, possible value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) CONNECTOR_OBJECT_ID_HDMI_TYPE_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) CONNECTOR_OBJECT_ID_DISPLAYPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) CONNECTOR_OBJECT_ID_eDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) [31:24]- Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) ulDDISlot2Config: Same as Slot1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) For IGP, Hypermemory is the only memory type showed in CCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) ucUMAChannelNumber: how many channels for the UMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ucDockingPinBit: which bit in this register to read the pin status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) ucDockingPinPolarity:Polarity of the pin when docked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) If CDLW enabled, both upstream and downstream width should be the same during bootup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) If CDLW enabled, both upstream and downstream width should be the same during bootup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) usUMASyncStartDelay: Memory access latency, required for watermark calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) usUMADataReturnTime: Memory access latency, required for watermark calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) for Griffin or Greyhound. SBIOS needs to convert to actual time by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) This must be less than or equal to ulHTLinkFreq(bootup frequency).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) This must be less than or equal to ulHighVoltageHTLinkFreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) usMaxDownStreamHTLinkWidth: same as above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) usMinDownStreamHTLinkWidth: same as above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) ULONG ulBootUpEngineClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ULONG ulBootUpUMAClock; //in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) ULONG ulReserved1[8]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) ULONG ulBootUpReqDisplayVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) ULONG ulOtherDisplayMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) ULONG ulReserved2[4]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) ULONG ulSystemConfig; //TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ULONG ulCPUCapInfo; //TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) USHORT usBootUpNBVoltage; //boot up NB voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) ULONG ulReserved3[4]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ULONG ulDDISlot2Config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) ULONG ulDDISlot3Config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ULONG ulDDISlot4Config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) ULONG ulReserved4[4]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) UCHAR ucUMAChannelNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) ULONG ulReserved5[4]; //must be 0x0 for the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) ULONG ulReserved6[61]; //must be 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }ATOM_INTEGRATED_SYSTEM_INFO_V5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) #define ASIC_INT_DAC1_ENCODER_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) #define ASIC_INT_TV_ENCODER_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) #define ASIC_INT_DIG1_ENCODER_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) #define ASIC_INT_DAC2_ENCODER_ID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) #define ASIC_EXT_TV_ENCODER_ID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) #define ASIC_INT_DVO_ENCODER_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) #define ASIC_INT_DIG2_ENCODER_ID 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) #define ASIC_EXT_DIG_ENCODER_ID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) #define ASIC_EXT_DIG2_ENCODER_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #define ASIC_INT_DIG3_ENCODER_ID 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) #define ASIC_INT_DIG4_ENCODER_ID 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) #define ASIC_INT_DIG5_ENCODER_ID 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) #define ASIC_INT_DIG6_ENCODER_ID 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) #define ASIC_INT_DIG7_ENCODER_ID 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) //define Encoder attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) #define ATOM_ANALOG_ENCODER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) #define ATOM_DIGITAL_ENCODER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) #define ATOM_DP_ENCODER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) #define ATOM_ENCODER_ENUM_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) #define ATOM_ENCODER_ENUM_ID1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) #define ATOM_ENCODER_ENUM_ID2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) #define ATOM_ENCODER_ENUM_ID3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) #define ATOM_ENCODER_ENUM_ID4 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) #define ATOM_ENCODER_ENUM_ID5 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) #define ATOM_ENCODER_ENUM_ID6 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #define ATOM_DEVICE_CRT1_INDEX 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) #define ATOM_DEVICE_LCD1_INDEX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #define ATOM_DEVICE_TV1_INDEX 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) #define ATOM_DEVICE_DFP1_INDEX 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #define ATOM_DEVICE_CRT2_INDEX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #define ATOM_DEVICE_LCD2_INDEX 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) #define ATOM_DEVICE_DFP6_INDEX 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) #define ATOM_DEVICE_DFP2_INDEX 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) #define ATOM_DEVICE_CV_INDEX 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) #define ATOM_DEVICE_DFP3_INDEX 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define ATOM_DEVICE_DFP4_INDEX 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) #define ATOM_DEVICE_DFP5_INDEX 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #define ATOM_DEVICE_I2C_ID_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) // usDeviceSupport:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) // Bit 8 = 0 - no CV support= 1- CV is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) /* Structure used in MclkSS_InfoTable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) // ucI2C_ConfigID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) // [7:0] - I2C LINE Associate ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) // = 0 - no I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) // = 0, [6:0]=SW assisted I2C ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) // = 2, HW engine for Multimedia use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) // = 3-7 Reserved for future I2C engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) typedef struct _ATOM_I2C_ID_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) UCHAR bfHW_Capable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) UCHAR bfHW_EngineID:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) UCHAR bfI2C_LineMux:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) UCHAR bfI2C_LineMux:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) UCHAR bfHW_EngineID:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) UCHAR bfHW_Capable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }ATOM_I2C_ID_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) typedef union _ATOM_I2C_ID_CONFIG_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) ATOM_I2C_ID_CONFIG sbfAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) UCHAR ucAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }ATOM_I2C_ID_CONFIG_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) // Structure used in GPIO_I2C_InfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) typedef struct _ATOM_GPIO_I2C_ASSIGMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) USHORT usClkMaskRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) USHORT usClkEnRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) USHORT usClkY_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) USHORT usClkA_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) USHORT usDataMaskRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) USHORT usDataEnRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) USHORT usDataY_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) USHORT usDataA_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) UCHAR ucClkMaskShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) UCHAR ucClkEnShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) UCHAR ucClkY_Shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) UCHAR ucClkA_Shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) UCHAR ucDataMaskShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) UCHAR ucDataEnShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) UCHAR ucDataY_Shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) UCHAR ucDataA_Shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) UCHAR ucReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) UCHAR ucReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }ATOM_GPIO_I2C_ASSIGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) typedef struct _ATOM_GPIO_I2C_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) }ATOM_GPIO_I2C_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) // Common Structure used in other structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) #ifndef _H2INC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) //Please don't add or expand this bitfield structure below, this one will retire soon.!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) typedef struct _ATOM_MODE_MISC_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) USHORT Reserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) USHORT RGB888:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) USHORT DoubleClock:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) USHORT Interlace:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) USHORT CompositeSync:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) USHORT V_ReplicationBy2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) USHORT H_ReplicationBy2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) USHORT VerticalCutOff:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) USHORT HorizontalCutOff:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) USHORT HorizontalCutOff:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) USHORT VerticalCutOff:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) USHORT H_ReplicationBy2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) USHORT V_ReplicationBy2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) USHORT CompositeSync:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) USHORT Interlace:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) USHORT DoubleClock:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) USHORT RGB888:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) USHORT Reserved:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }ATOM_MODE_MISC_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) typedef union _ATOM_MODE_MISC_INFO_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ATOM_MODE_MISC_INFO sbfAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) USHORT usAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) }ATOM_MODE_MISC_INFO_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) typedef union _ATOM_MODE_MISC_INFO_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) USHORT usAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) }ATOM_MODE_MISC_INFO_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) // usModeMiscInfo-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) #define ATOM_H_CUTOFF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) #define ATOM_V_CUTOFF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) #define ATOM_H_REPLICATIONBY2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) #define ATOM_V_REPLICATIONBY2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) #define ATOM_COMPOSITESYNC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) #define ATOM_INTERLACE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) #define ATOM_DOUBLE_CLOCK_MODE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) #define ATOM_RGB888_MODE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) //usRefreshRate-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) #define ATOM_REFRESH_43 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) #define ATOM_REFRESH_47 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) #define ATOM_REFRESH_56 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) #define ATOM_REFRESH_60 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) #define ATOM_REFRESH_65 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) #define ATOM_REFRESH_70 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) #define ATOM_REFRESH_72 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) #define ATOM_REFRESH_75 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) #define ATOM_REFRESH_85 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) // = EDID_HA + EDID_HBL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) // VESA_HDISP = VESA_ACTIVE = EDID_HA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) // = EDID_HA + EDID_HSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) // VESA_BORDER = EDID_BORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) // Structure used in SetCRTC_UsingDTDTimingTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) USHORT usH_Size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) USHORT usH_Blanking_Time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) USHORT usV_Size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) USHORT usV_Blanking_Time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) USHORT usH_SyncOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) USHORT usH_SyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) USHORT usV_SyncOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) USHORT usV_SyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) UCHAR ucH_Border; // From DFP EDID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) UCHAR ucV_Border;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) // Structure used in SetCRTC_TimingTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) typedef struct _SET_CRTC_TIMING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) USHORT usH_Total; // horizontal total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) USHORT usH_Disp; // horizontal display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) USHORT usH_SyncStart; // horozontal Sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) USHORT usH_SyncWidth; // horizontal Sync width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) USHORT usV_Total; // vertical total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) USHORT usV_Disp; // vertical display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) USHORT usV_SyncStart; // vertical Sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) USHORT usV_SyncWidth; // vertical Sync width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) UCHAR ucOverscanRight; // right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) UCHAR ucOverscanLeft; // left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) UCHAR ucOverscanBottom; // bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) UCHAR ucOverscanTop; // top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }SET_CRTC_TIMING_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) // Structure used in StandardVESA_TimingTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) // AnalogTV_InfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) // ComponentVideoInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) typedef struct _ATOM_MODE_TIMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) USHORT usCRTC_H_Total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) USHORT usCRTC_H_Disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) USHORT usCRTC_H_SyncStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) USHORT usCRTC_H_SyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) USHORT usCRTC_V_Total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) USHORT usCRTC_V_Disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) USHORT usCRTC_V_SyncStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) USHORT usCRTC_V_SyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) USHORT usPixelClock; //in 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) USHORT usCRTC_OverscanRight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) USHORT usCRTC_OverscanLeft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) USHORT usCRTC_OverscanBottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) USHORT usCRTC_OverscanTop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) USHORT usReserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) UCHAR ucInternalModeNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) UCHAR ucRefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }ATOM_MODE_TIMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) typedef struct _ATOM_DTD_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) USHORT usPixClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) USHORT usHActive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) USHORT usHBlanking_Time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) USHORT usVActive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) USHORT usVBlanking_Time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) USHORT usHSyncOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) USHORT usHSyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) USHORT usVSyncOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) USHORT usVSyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) USHORT usImageHSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) USHORT usImageVSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) UCHAR ucHBorder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) UCHAR ucVBorder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) UCHAR ucInternalModeNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) UCHAR ucRefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) }ATOM_DTD_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) // Structure used in LVDS_InfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) // * Need a document to describe this table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) //ucTableContentRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) typedef struct _ATOM_LVDS_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) ATOM_DTD_FORMAT sLCDTiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) USHORT usModePatchTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) USHORT usOffDelayInMs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) UCHAR ucPowerSequenceDigOntoDEin10Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) UCHAR ucPowerSequenceDEtoBLOnin10Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) UCHAR ucPanelDefaultRefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) UCHAR ucPanelIdentification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) UCHAR ucSS_Id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }ATOM_LVDS_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) //ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) typedef struct _ATOM_LVDS_INFO_V12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) ATOM_DTD_FORMAT sLCDTiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) USHORT usExtInfoTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) USHORT usOffDelayInMs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) UCHAR ucPowerSequenceDigOntoDEin10Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) UCHAR ucPowerSequenceDEtoBLOnin10Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) UCHAR ucPanelDefaultRefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) UCHAR ucPanelIdentification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) UCHAR ucSS_Id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) USHORT usLCDVenderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) USHORT usLCDProductID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) UCHAR ucLCDPanel_SpecialHandlingCap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) }ATOM_LVDS_INFO_V12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) //Definitions for ucLCDPanel_SpecialHandlingCap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) #define LCDPANEL_CAP_READ_EDID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) #define LCDPANEL_CAP_DRR_SUPPORTED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) #define LCDPANEL_CAP_eDP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) //Color Bit Depth definition in EDID V1.4 @BYTE 14h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) //Bit 6 5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) // 0 0 0 - Color bit depth is undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) // 0 0 1 - 6 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) // 0 1 0 - 8 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) // 0 1 1 - 10 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) // 1 0 0 - 12 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) // 1 0 1 - 14 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) // 1 1 0 - 16 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) // 1 1 1 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) #define PANEL_COLOR_BIT_DEPTH_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) #define PANEL_RANDOM_DITHER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) #define PANEL_RANDOM_DITHER_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) // ASIC Families: NI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) // ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) // ucTableContentRevision=3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) typedef struct _ATOM_LCD_INFO_V13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) ATOM_DTD_FORMAT sLCDTiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) USHORT usExtInfoTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) ULONG ulReserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) UCHAR ucLCD_Misc; // Reorganized in V13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) // Bit0: {=0:single, =1:dual},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) // Bit3:2: {Grey level}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) UCHAR ucPanelDefaultRefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) UCHAR ucPanelIdentification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) UCHAR ucSS_Id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) USHORT usLCDVenderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) USHORT usLCDProductID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) // Bit7-3: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) UCHAR ucOffDelay_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) UCHAR ucReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) UCHAR uceDPToLVDSRxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) UCHAR ucLcdReservd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) ULONG ulReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) }ATOM_LCD_INFO_V13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) //Definitions for ucLCD_Misc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) #define ATOM_PANEL_MISC_V13_DUAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) #define ATOM_PANEL_MISC_V13_FPDI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) //Color Bit Depth definition in EDID V1.4 @BYTE 14h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) //Bit 6 5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) // 0 0 0 - Color bit depth is undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) // 0 0 1 - 6 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) // 0 1 0 - 8 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) // 0 1 1 - 10 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) // 1 0 0 - 12 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) // 1 0 1 - 14 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) // 1 1 0 - 16 Bits per Primary Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) // 1 1 1 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) //Definitions for ucLCDPanel_SpecialHandlingCap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) //uceDPToLVDSRxId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) typedef struct _ATOM_PATCH_RECORD_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) UCHAR ucRecordType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) USHORT usHDisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) USHORT usVDisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) }ATOM_PATCH_RECORD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) typedef struct _ATOM_LCD_RTS_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) UCHAR ucRecordType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) UCHAR ucRTSValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }ATOM_LCD_RTS_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) typedef struct _ATOM_LCD_MODE_CONTROL_CAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) UCHAR ucRecordType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) USHORT usLCDCap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) }ATOM_LCD_MODE_CONTROL_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) #define LCD_MODE_CAP_BL_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) #define LCD_MODE_CAP_CRTC_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) #define LCD_MODE_CAP_PANEL_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) UCHAR ucRecordType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) UCHAR ucFakeEDIDLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) } ATOM_FAKE_EDID_PATCH_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) UCHAR ucRecordType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) USHORT usHSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) USHORT usVSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) #define LCD_RTS_RECORD_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #define LCD_CAP_RECORD_TYPE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) #define ATOM_RECORD_END_TYPE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) /****************************Spread Spectrum Info Table Definitions **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) //ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) USHORT usSpreadSpectrumPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) UCHAR ucSS_Step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) UCHAR ucSS_Delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) UCHAR ucSS_Id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) UCHAR ucRecommendedRef_Div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) UCHAR ucSS_Range; //it was reserved for V11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) #define ATOM_MAX_SS_ENTRY 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) #define ATOM_INTERNAL_SS_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) #define ATOM_EXTERNAL_SS_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) #define EXEC_SS_STEP_SIZE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) #define EXEC_SS_DELAY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) typedef struct _ATOM_SPREAD_SPECTRUM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) }ATOM_SPREAD_SPECTRUM_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) // Structure used in AnalogTV_InfoTable (Top level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) //ucTVBootUpDefaultStd definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) //ATOM_TV_NTSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) //ATOM_TV_NTSCJ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) //ATOM_TV_PAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) //ATOM_TV_PALM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) //ATOM_TV_PALCN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) //ATOM_TV_PALN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) //ATOM_TV_PAL60 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) //ATOM_TV_SECAM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) //ucTVSupportedStd definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) #define NTSC_SUPPORT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) #define NTSCJ_SUPPORT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) #define PAL_SUPPORT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) #define PALM_SUPPORT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) #define PALCN_SUPPORT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) #define PALN_SUPPORT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) #define PAL60_SUPPORT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) #define SECAM_SUPPORT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) #define MAX_SUPPORTED_TV_TIMING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) typedef struct _ATOM_ANALOG_TV_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) UCHAR ucTV_SupportedStandard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) UCHAR ucTV_BootUpDefaultStandard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) UCHAR ucExt_TV_ASIC_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) UCHAR ucExt_TV_ASIC_SlaveAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) }ATOM_ANALOG_TV_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) #define MAX_SUPPORTED_TV_TIMING_V1_2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) typedef struct _ATOM_ANALOG_TV_INFO_V1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) UCHAR ucTV_SupportedStandard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) UCHAR ucTV_BootUpDefaultStandard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) UCHAR ucExt_TV_ASIC_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) UCHAR ucExt_TV_ASIC_SlaveAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }ATOM_ANALOG_TV_INFO_V1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) typedef struct _ATOM_DPCD_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) }ATOM_DPCD_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) #define ATOM_DPCD_MAX_LANE_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) /**************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) // VRAM usage and their defintions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) #ifndef VESA_MEMORY_IN_64K_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) #define ATOM_HWICON_INFOTABLE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define MAX_DTD_MODE_IN_VRAM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) //20 bytes for Encoder Type and DPCD in STD EDID area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) #define ATOM_HWICON1_SURFACE_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) //The size below is in Kb!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) #define ATOM_VRAM_RESERVE_V2_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) /***********************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) // Structure used in VRAM_UsageByFirmwareTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) // at running time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) // note2: From RV770, the memory is more than 32bit addressable, so we will change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) // (in offset to start of memory address) is KB aligned instead of byte aligend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) /***********************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) // Note3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) If (ulStartAddrUsedByFirmware!=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) else //Non VGA case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) if (FB_Size<=2Gb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) /***********************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) ULONG ulStartAddrUsedByFirmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) USHORT usFirmwareUseInKb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) }ATOM_VRAM_USAGE_BY_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) // change verion to 1.5, when allow driver to allocate the vram area for command table access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) ULONG ulStartAddrUsedByFirmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) USHORT usFirmwareUseInKb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) USHORT usFBUsedByDrvInKb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) // Structure used in GPIO_Pin_LUTTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) USHORT usGpioPin_AIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) UCHAR ucGpioPinBitShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) UCHAR ucGPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) }ATOM_GPIO_PIN_ASSIGNMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) //ucGPIO_ID pre-define id for multiple usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) #define PP_AC_DC_SWITCH_GPIO_PINID 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) #define VDDC_VRHOT_GPIO_PINID 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) #define VDDC_PCC_GPIO_PINID 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) typedef struct _ATOM_GPIO_PIN_LUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) }ATOM_GPIO_PIN_LUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) // Structure used in ComponentVideoInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) #define GPIO_PIN_ACTIVE_HIGH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) #define MAX_SUPPORTED_CV_STANDARDS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) // definitions for ATOM_D_INFO.ucSettings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) typedef struct _ATOM_GPIO_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) USHORT usAOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) UCHAR ucSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) }ATOM_GPIO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) //Line 3 out put 5V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) //Line 3 out put 2.2V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) //Line 3 out put 0V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) typedef struct _ATOM_COMPONENT_VIDEO_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) USHORT usMask_PinRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) USHORT usEN_PinRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) USHORT usY_PinRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) USHORT usA_PinRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) UCHAR ucBitShift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) ATOM_DTD_FORMAT sReserved; // must be zeroed out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) UCHAR ucMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) UCHAR uc480i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) UCHAR uc480p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) UCHAR uc720p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) UCHAR uc1080i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) UCHAR ucLetterBoxMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) }ATOM_COMPONENT_VIDEO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) //ucTableFormatRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) //ucTableContentRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) UCHAR ucMiscInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) UCHAR uc480i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) UCHAR uc480p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) UCHAR uc720p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) UCHAR uc1080i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) UCHAR ucLetterBoxMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }ATOM_COMPONENT_VIDEO_INFO_V21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) // Structure used in object_InfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) typedef struct _ATOM_OBJECT_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) USHORT usDeviceSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) USHORT usConnectorObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) USHORT usRouterObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) USHORT usEncoderObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) USHORT usDisplayPathTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) }ATOM_OBJECT_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) typedef struct _ATOM_OBJECT_HEADER_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) USHORT usDeviceSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) USHORT usConnectorObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) USHORT usRouterObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) USHORT usEncoderObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) USHORT usDisplayPathTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) USHORT usMiscObjectTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) }ATOM_OBJECT_HEADER_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) typedef struct _ATOM_DISPLAY_OBJECT_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) USHORT usDeviceTag; //supported device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) USHORT usConnObjectId; //Connector Object ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) USHORT usGPUObjectId; //GPU ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }ATOM_DISPLAY_OBJECT_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) USHORT usDeviceTag; //supported device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) USHORT usConnObjectId; //Connector Object ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) USHORT usGPUObjectId; //GPU ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) UCHAR ucNumOfDispPath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) UCHAR ucVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }ATOM_DISPLAY_OBJECT_PATH_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) typedef struct _ATOM_OBJECT //each object has this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) USHORT usObjectID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) USHORT usSrcDstTableOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) USHORT usRecordOffset; //this pointing to a bunch of records defined below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) }ATOM_OBJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) UCHAR ucNumberOfObjects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) ATOM_OBJECT asObjects[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) }ATOM_OBJECT_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) UCHAR ucNumberOfSrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) USHORT usSrcObjectID[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) UCHAR ucNumberOfDst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) USHORT usDstObjectID[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) //Two definitions below are for OPM on MXM module designs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) #define EXT_HPDPIN_LUTINDEX_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) #define EXT_HPDPIN_LUTINDEX_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) #define EXT_HPDPIN_LUTINDEX_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) #define EXT_HPDPIN_LUTINDEX_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) #define EXT_HPDPIN_LUTINDEX_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) #define EXT_HPDPIN_LUTINDEX_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) #define EXT_HPDPIN_LUTINDEX_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) #define EXT_HPDPIN_LUTINDEX_7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) #define EXT_AUXDDC_LUTINDEX_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) #define EXT_AUXDDC_LUTINDEX_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) #define EXT_AUXDDC_LUTINDEX_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) #define EXT_AUXDDC_LUTINDEX_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) #define EXT_AUXDDC_LUTINDEX_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) #define EXT_AUXDDC_LUTINDEX_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) #define EXT_AUXDDC_LUTINDEX_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) #define EXT_AUXDDC_LUTINDEX_7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) //ucChannelMapping are defined as following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) //for DP connector, eDP, DP to VGA/LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) UCHAR ucDP_Lane3_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) UCHAR ucDP_Lane2_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) UCHAR ucDP_Lane1_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) UCHAR ucDP_Lane0_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) UCHAR ucDP_Lane0_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) UCHAR ucDP_Lane1_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) UCHAR ucDP_Lane2_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) UCHAR ucDP_Lane3_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }ATOM_DP_CONN_CHANNEL_MAPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) //for DVI/HDMI, in dual link case, both links have to have same mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) UCHAR ucDVI_CLK_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) UCHAR ucDVI_DATA0_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) UCHAR ucDVI_DATA1_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) UCHAR ucDVI_DATA2_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) UCHAR ucDVI_DATA2_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) UCHAR ucDVI_DATA1_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) UCHAR ucDVI_DATA0_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) UCHAR ucDVI_CLK_Source:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) }ATOM_DVI_CONN_CHANNEL_MAPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) typedef struct _EXT_DISPLAY_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) USHORT usDeviceTag; //A bit vector to show what devices are supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) USHORT usDeviceACPIEnum; //16bit device ACPI id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) USHORT usExtEncoderObjId; //external encoder object id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) USHORT usCaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) }EXT_DISPLAY_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) #define NUMBER_OF_UCHAR_FOR_GUID 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) //usCaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) UCHAR uc3DStereoPinId; // use for eDP panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) UCHAR ucRemoteDisplayConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) UCHAR uceDPToLVDSRxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) UCHAR Reserved[3]; // for potential expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) //Related definitions, all records are different but they have a commond header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) typedef struct _ATOM_COMMON_RECORD_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) UCHAR ucRecordType; //An emun to indicate the record type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) UCHAR ucRecordSize; //The size of the whole record in byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) }ATOM_COMMON_RECORD_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) #define ATOM_I2C_RECORD_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) #define ATOM_HPD_INT_RECORD_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) #define ATOM_CONNECTOR_CF_RECORD_TYPE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) #define ATOM_ENCODER_CAP_RECORD_TYPE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) //Must be updated when new record type is added,equal to that record definition!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) typedef struct _ATOM_I2C_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) ATOM_I2C_ID_CONFIG sucI2cId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) }ATOM_I2C_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) typedef struct _ATOM_HPD_INT_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) UCHAR ucPlugged_PinState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) }ATOM_HPD_INT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) UCHAR ucProtectionFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) }ATOM_OUTPUT_PROTECTION_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) typedef struct _ATOM_CONNECTOR_DEVICE_TAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) ULONG ulACPIDeviceEnum; //Reserved for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) USHORT usPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) }ATOM_CONNECTOR_DEVICE_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) UCHAR ucNumberOfDevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) UCHAR ucConfigGPIOID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) UCHAR ucFlowinGPIPID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) UCHAR ucExtInGPIPID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) UCHAR ucCTL1GPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) UCHAR ucCTL2GPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) UCHAR ucCTL3GPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) UCHAR ucCTLFPGA_IN_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) }ATOM_ENCODER_FPGA_CONTROL_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) typedef struct _ATOM_JTAG_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) UCHAR ucTMSGPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) UCHAR ucTMSGPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) UCHAR ucTCKGPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) UCHAR ucTCKGPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) UCHAR ucTDOGPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) UCHAR ucTDOGPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) UCHAR ucTDIGPIO_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) UCHAR ucTDIGPIOState; //Set to 1 when it's active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }ATOM_JTAG_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) }ATOM_GPIO_PIN_CONTROL_PAIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) UCHAR ucFlags; // Future expnadibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) }ATOM_OBJECT_GPIO_CNTL_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) //Definitions for GPIO pin state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) #define GPIO_PIN_TYPE_INPUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) #define GPIO_PIN_TYPE_OUTPUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) #define GPIO_PIN_TYPE_HW_CONTROL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) //For GPIO_PIN_TYPE_OUTPUT the following is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) #define GPIO_PIN_OUTPUT_STATE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) #define GPIO_PIN_OUTPUT_STATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) #define GPIO_PIN_STATE_ACTIVE_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) // Indexes to GPIO array in GLSync record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) // GLSync record is for Frame Lock/Gen Lock feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) #define ATOM_GPIO_INDEX_GLSYNC_MAX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) typedef struct _ATOM_ENCODER_DVO_CF_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) ULONG ulStrengthControl; // DVOA strength control for CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) }ATOM_ENCODER_DVO_CF_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) typedef struct _ATOM_ENCODER_CAP_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) USHORT usEncoderCap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) }ATOM_ENCODER_CAP_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) typedef struct _ATOM_CONNECTOR_CF_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) USHORT usMaxPixClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) UCHAR ucFlowCntlGpioId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) UCHAR ucSwapCntlGpioId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) UCHAR ucConnectedDvoBundle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) UCHAR ucPadding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) }ATOM_CONNECTOR_CF_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) ATOM_DTD_FORMAT asTiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) UCHAR ucMuxControlPin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) UCHAR ucMuxState[2]; //for alligment purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) UCHAR ucMuxType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) UCHAR ucMuxControlPin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) UCHAR ucMuxState[2]; //for alligment purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) // define ucMuxType
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) typedef struct _ATOM_OBJECT_LINK_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) USHORT usObjectID; //could be connector, encorder or other object in object.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) }ATOM_OBJECT_LINK_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) typedef struct _ATOM_CONNECTOR_LAYOUT_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) USHORT usConnectorObjectId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) UCHAR ucConnectorType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) UCHAR ucPosition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) }ATOM_CONNECTOR_LAYOUT_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) #define CONNECTOR_TYPE_DVI_D 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) #define CONNECTOR_TYPE_DVI_I 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) #define CONNECTOR_TYPE_VGA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) #define CONNECTOR_TYPE_HDMI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) #define CONNECTOR_TYPE_DISPLAY_PORT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) typedef struct _ATOM_BRACKET_LAYOUT_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) ATOM_COMMON_RECORD_HEADER sheader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) UCHAR ucLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) UCHAR ucWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) UCHAR ucConnNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) }ATOM_BRACKET_LAYOUT_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) // ASIC voltage data table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) typedef struct _ATOM_VOLTAGE_INFO_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) USHORT usVDDCBaseLevel; //In number of 50mv unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) USHORT usReserved; //For possible extension table offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) UCHAR ucNumOfVoltageEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) UCHAR ucBytesPerVoltageEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) UCHAR ucDefaultVoltageEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) UCHAR ucVoltageControlI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) UCHAR ucVoltageControlAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) UCHAR ucVoltageControlOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) }ATOM_VOLTAGE_INFO_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) typedef struct _ATOM_VOLTAGE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) ATOM_VOLTAGE_INFO_HEADER viHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) }ATOM_VOLTAGE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) typedef struct _ATOM_VOLTAGE_FORMULA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) USHORT usVoltageBaseLevel; // In number of 1mv unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) }ATOM_VOLTAGE_FORMULA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) typedef struct _VOLTAGE_LUT_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) USHORT usVoltageValue; // The corresponding Voltage Value, in mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) }VOLTAGE_LUT_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) typedef struct _ATOM_VOLTAGE_FORMULA_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) }ATOM_VOLTAGE_FORMULA_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) typedef struct _ATOM_VOLTAGE_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) UCHAR ucVoltageControlI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) UCHAR ucVoltageControlAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) UCHAR ucVoltageControlOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) USHORT usGpioPin_AIndex; //GPIO_PAD register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) }ATOM_VOLTAGE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) // Define ucVoltageControlId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) #define VOLTAGE_CONTROLLED_BY_HW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) #define VOLTAGE_CONTROLLED_BY_GPIO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) #define VOLTAGE_CONTROL_ID_DS4402 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) #define VOLTAGE_CONTROL_ID_UP6266 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) #define VOLTAGE_CONTROL_ID_SCORPIO 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) #define VOLTAGE_CONTROL_ID_VT1556M 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) #define VOLTAGE_CONTROL_ID_CHL822x 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) #define VOLTAGE_CONTROL_ID_VT1586M 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) #define VOLTAGE_CONTROL_ID_UP1637 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) #define VOLTAGE_CONTROL_ID_CHL8214 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) #define VOLTAGE_CONTROL_ID_UP1801 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) #define VOLTAGE_CONTROL_ID_ST6788A 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) #define VOLTAGE_CONTROL_ID_AD527x 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) #define VOLTAGE_CONTROL_ID_NCP81022 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) #define VOLTAGE_CONTROL_ID_LTC2635 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) typedef struct _ATOM_VOLTAGE_OBJECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) UCHAR ucSize; //Size of Object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) ATOM_VOLTAGE_CONTROL asControl; //describ how to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) }ATOM_VOLTAGE_OBJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) typedef struct _ATOM_VOLTAGE_OBJECT_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) UCHAR ucSize; //Size of Object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) ATOM_VOLTAGE_CONTROL asControl; //describ how to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) }ATOM_VOLTAGE_OBJECT_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) typedef struct _ATOM_VOLTAGE_OBJECT_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) }ATOM_VOLTAGE_OBJECT_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) }ATOM_VOLTAGE_OBJECT_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) typedef struct _ATOM_LEAKID_VOLTAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) UCHAR ucLeakageId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) USHORT usVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) }ATOM_LEAKID_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) USHORT usSize; //Size of Object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) }ATOM_VOLTAGE_OBJECT_HEADER_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) #define VOLTAGE_OBJ_EVV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) typedef struct _VOLTAGE_LUT_ENTRY_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) USHORT usVoltageValue; // The corresponding Voltage Value, in mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) }VOLTAGE_LUT_ENTRY_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) USHORT usVoltageId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) USHORT usLeakageId; // The corresponding Voltage Value, in mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) }LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) UCHAR ucVoltageControlI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) UCHAR ucVoltageControlAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) UCHAR ucVoltageControlOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) }ATOM_I2C_VOLTAGE_OBJECT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) #define VOLTAGE_DATA_ONE_BYTE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) #define VOLTAGE_DATA_TWO_BYTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) UCHAR ucPhaseDelay; // phase delay in unit of micro second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) ULONG ulGpioMaskVal; // GPIO Mask value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) }ATOM_GPIO_VOLTAGE_OBJECT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) UCHAR ucLeakageCntlId; // default is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) ULONG ulMaxVoltageLevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) // 14:7 PSI0_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) // 6 PSI0_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) // 5 PSI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) // 4:2 load line slope trim.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) // 1:0 offset trim,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) USHORT usLoadLine_PSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) }ATOM_SVID2_VOLTAGE_OBJECT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) typedef union _ATOM_VOLTAGE_OBJECT_V3{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) }ATOM_VOLTAGE_OBJECT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) }ATOM_VOLTAGE_OBJECT_INFO_V3_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) UCHAR ucProfileId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) USHORT usEfuseSpareStartAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) }ATOM_ASIC_PROFILE_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) //ucProfileId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) typedef struct _ATOM_ASIC_PROFILING_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) ATOM_COMMON_TABLE_HEADER asHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) }ATOM_ASIC_PROFILING_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) ATOM_COMMON_TABLE_HEADER asHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) UCHAR ucElbVDDC_Num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) UCHAR ucElbVDDCI_Num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) }ATOM_ASIC_PROFILING_INFO_V2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) ATOM_COMMON_TABLE_HEADER asHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) ULONG ulEvvDerateTdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) ULONG ulEvvDerateTdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) ULONG ulBoardCoreTemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) ULONG ulMaxVddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) ULONG ulMinVddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) ULONG ulLoadLineSlop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) ULONG ulLeakageTemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) ULONG ulLeakageVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) ULONG ulCACmEncodeRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) ULONG ulCACmEncodeAverage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) ULONG ulCACbEncodeRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) ULONG ulCACbEncodeAverage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) ULONG ulKt_bEncodeRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) ULONG ulKt_bEncodeAverage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) ULONG ulKv_mEncodeRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) ULONG ulKv_mEncodeAverage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) ULONG ulKv_bEncodeRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) ULONG ulKv_bEncodeAverage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) ULONG ulLkgEncodeLn_MaxDivMin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) ULONG ulLkgEncodeMin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) ULONG ulEfuseLogisticAlpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) USHORT usPowerDpm0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) USHORT usCurrentDpm0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) USHORT usPowerDpm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) USHORT usCurrentDpm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) USHORT usPowerDpm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) USHORT usCurrentDpm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) USHORT usPowerDpm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) USHORT usCurrentDpm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) USHORT usPowerDpm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) USHORT usCurrentDpm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) USHORT usPowerDpm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) USHORT usCurrentDpm5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) USHORT usPowerDpm6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) USHORT usCurrentDpm6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) USHORT usPowerDpm7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) USHORT usCurrentDpm7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) }ATOM_ASIC_PROFILING_INFO_V3_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) typedef struct _ATOM_POWER_SOURCE_OBJECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) UCHAR ucPwrSrcId; // Power source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) UCHAR ucPwrSensorType; // GPIO, I2C or none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) UCHAR ucPwrSensActiveState; // high active or low active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) UCHAR ucReserve[3]; // reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) USHORT usSensPwr; // in unit of watt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) }ATOM_POWER_SOURCE_OBJECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) typedef struct _ATOM_POWER_SOURCE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) ATOM_COMMON_TABLE_HEADER asHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) UCHAR asPwrbehave[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) }ATOM_POWER_SOURCE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) //Define ucPwrSrcId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) #define POWERSOURCE_PCIE_ID1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) //define ucPwrSensorId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) #define POWER_SENSOR_ALWAYS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) #define POWER_SENSOR_GPIO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) #define POWER_SENSOR_I2C 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) typedef struct _ATOM_CLK_VOLT_CAPABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) }ATOM_CLK_VOLT_CAPABILITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) typedef struct _ATOM_AVAILABLE_SCLK_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) }ATOM_AVAILABLE_SCLK_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) // this IntegrateSystemInfoTable is used for Liano/Ontario APU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) ULONG ulBootUpEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) ULONG ulDentistVCOFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) ULONG ulBootUpUMAClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) ULONG ulBootUpReqDisplayVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) ULONG ulOtherDisplayMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) ULONG ulGPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) ULONG ulSB_MMIO_Base_Addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) USHORT usRequestedPWMFreqInHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) UCHAR ucHtcTmpLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) UCHAR ucHtcHystLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) ULONG ulMinEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) ULONG ulSystemConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) ULONG ulCPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) USHORT usNBP0Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) USHORT usNBP1Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) USHORT usBootUpNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) USHORT usExtDispConnInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) USHORT usPanelRefreshRateRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) UCHAR ucMemoryType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) UCHAR ucUMAChannelNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) ULONG ulCSR_M3_ARB_CNTL_UVD[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) ULONG ulGMCRestoreResetTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) ULONG ulMinimumNClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) ULONG ulIdleNClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) ULONG ulDDR_DLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) ULONG ulDDR_PLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) USHORT usPCIEClkSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) USHORT usPCIEClkSSType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) USHORT usLvdsSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) USHORT usLvdsSSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) USHORT usHDMISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) USHORT usHDMISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) USHORT usDVISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) USHORT usDVISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) ULONG SclkDpmBoostMargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) ULONG SclkDpmThrottleMargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) USHORT SclkDpmTdpLimitPG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) USHORT SclkDpmTdpLimitBoost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) ULONG ulBoostEngineCLock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) UCHAR ulBoostVid_2bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) UCHAR EnableBoost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) USHORT GnbTdpLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) USHORT usMaxLVDSPclkFreqInSingleLink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) UCHAR ucLvdsMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) UCHAR ucLVDSReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) ULONG ulReserved3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) }ATOM_INTEGRATED_SYSTEM_INFO_V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) // ulGPUCapInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) //ucLVDSMisc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) #define SYS_INFO_LVDSMISC__888_BPC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) // new since Trinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) // not used any more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) /**********************************************************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) sDISPCLK_Voltage: Report Display clock voltage requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) ATOM_DEVICE_CRT1_SUPPORT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) ATOM_DEVICE_CRT2_SUPPORT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) ATOM_DEVICE_DFP1_SUPPORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) ATOM_DEVICE_DFP6_SUPPORT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) ATOM_DEVICE_DFP2_SUPPORT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) ATOM_DEVICE_DFP3_SUPPORT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) ATOM_DEVICE_DFP4_SUPPORT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) ATOM_DEVICE_DFP5_SUPPORT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) ATOM_DEVICE_LCD1_SUPPORT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) ulOtherDisplayMisc: Other display related flags, not defined yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) =1: TMDS/HDMI Coherent Mode use signel PLL mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) bit[3]=0: Enable HW AUX mode detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) =1: Disable HW AUX mode dettion logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) Changing BL using VBIOS function is functional in both driver and non-driver present environment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) that BL control from GPU is expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) it's per platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) Threshold on value to enter HTC_active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) =1: PCIE Power Gating Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) Bit[1]=0: DDR-DLL shut-down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) 1: DDR-DLL shut-down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) Bit[2]=0: DDR-PLL Power down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) 1: DDR-PLL Power down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) ulCPUCapInfo: TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) usNBP0Voltage: VID for voltage on NB P0 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) usNBP1Voltage: VID for voltage on NB P1 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) to indicate a range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) ucUMAChannelNumber: System memory channel numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) **********************************************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) // this Table is used for Liano/Ontario APU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) ULONG ulPowerplayTable[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) }ATOM_FUSION_SYSTEM_INFO_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) typedef struct _ATOM_TDP_CONFIG_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) ULONG uReserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) ULONG uCTDP_Value:14; // Override value in tens of milli watts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) ULONG uCTDP_Value:14; // Override value in tens of milli watts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) ULONG uReserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) }ATOM_TDP_CONFIG_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) typedef union _ATOM_TDP_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) ATOM_TDP_CONFIG_BITS TDP_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) ULONG TDP_config_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) }ATOM_TDP_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) /**********************************************************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) ATOM_FUSION_SYSTEM_INFO_V1 Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) **********************************************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) // this IntegrateSystemInfoTable is used for Trinity APU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) ULONG ulBootUpEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) ULONG ulDentistVCOFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) ULONG ulBootUpUMAClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) ULONG ulBootUpReqDisplayVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) ULONG ulOtherDisplayMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) ULONG ulGPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) ULONG ulSB_MMIO_Base_Addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) USHORT usRequestedPWMFreqInHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) UCHAR ucHtcTmpLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) UCHAR ucHtcHystLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) ULONG ulMinEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) ULONG ulSystemConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) ULONG ulCPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) USHORT usNBP0Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) USHORT usNBP1Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) USHORT usBootUpNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) USHORT usExtDispConnInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) USHORT usPanelRefreshRateRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) UCHAR ucMemoryType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) UCHAR ucUMAChannelNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) UCHAR strVBIOSMsg[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) ATOM_TDP_CONFIG asTdpConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) ULONG ulReserved[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) ULONG ulGMCRestoreResetTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) ULONG ulMinimumNClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) ULONG ulIdleNClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) ULONG ulDDR_DLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) ULONG ulDDR_PLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) USHORT usPCIEClkSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) USHORT usPCIEClkSSType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) USHORT usLvdsSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) USHORT usLvdsSSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) USHORT usHDMISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) USHORT usHDMISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) USHORT usDVISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) USHORT usDVISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) ULONG SclkDpmBoostMargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) ULONG SclkDpmThrottleMargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) USHORT SclkDpmTdpLimitPG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) USHORT SclkDpmTdpLimitBoost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) ULONG ulBoostEngineCLock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) UCHAR ulBoostVid_2bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) UCHAR EnableBoost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) USHORT GnbTdpLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) USHORT usMaxLVDSPclkFreqInSingleLink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) UCHAR ucLvdsMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) UCHAR ucTravisLVDSVolAdjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) UCHAR ucLVDSOffToOnDelay_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) ULONG ulLCDBitDepthControlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) ULONG ulNbpStateMemclkFreq[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) USHORT usNBP2Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) USHORT usNBP3Voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) ULONG ulNbpStateNClkFreq[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) UCHAR ucNBDPMEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) UCHAR ucDPMState0VclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) UCHAR ucDPMState0DclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) UCHAR ucDPMState1VclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) UCHAR ucDPMState1DclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) UCHAR ucDPMState2VclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) UCHAR ucDPMState2DclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) UCHAR ucDPMState3VclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) UCHAR ucDPMState3DclkFid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) }ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) // ulOtherDisplayMisc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) // ulGPUCapInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) /**********************************************************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) sDISPCLK_Voltage: Report Display clock voltage requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) ATOM_DEVICE_CRT1_SUPPORT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) ATOM_DEVICE_DFP1_SUPPORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) ATOM_DEVICE_DFP6_SUPPORT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) ATOM_DEVICE_DFP2_SUPPORT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) ATOM_DEVICE_DFP3_SUPPORT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) ATOM_DEVICE_DFP4_SUPPORT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) ATOM_DEVICE_DFP5_SUPPORT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) ATOM_DEVICE_LCD1_SUPPORT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) bit[3]=0: VBIOS fast boot is disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) =1: TMDS/HDMI Coherent Mode use signel PLL mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) =1: DP mode use single PLL mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) bit[3]=0: Enable AUX HW mode detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) =1: Disable AUX HW mode detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) Changing BL using VBIOS function is functional in both driver and non-driver present environment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) that BL control from GPU is expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) it's per platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) Threshold on value to enter HTC_active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) =1: PCIE Power Gating Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) Bit[1]=0: DDR-DLL shut-down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) 1: DDR-DLL shut-down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) Bit[2]=0: DDR-PLL Power down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) 1: DDR-PLL Power down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) ulCPUCapInfo: TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) usNBP0Voltage: VID for voltage on NB P0 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) usNBP1Voltage: VID for voltage on NB P1 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) usNBP2Voltage: VID for voltage on NB P2 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) usNBP3Voltage: VID for voltage on NB P3 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) to indicate a range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) ucUMAChannelNumber: System memory channel numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) value to program Travis register LVDS_CTRL_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) =0 means to use VBIOS default delay which is 125 ( 500ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) =0 means to use VBIOS default delay which is 0 ( 0ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) =0 means to use VBIOS default delay which is 0 ( 0ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) **********************************************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) ULONG ulBootUpEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) ULONG ulDentistVCOFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) ULONG ulBootUpUMAClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) ULONG ulBootUpReqDisplayVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) ULONG ulVBIOSMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) ULONG ulGPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) ULONG ulDISP_CLK2Freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) USHORT usRequestedPWMFreqInHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) UCHAR ucHtcTmpLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) UCHAR ucHtcHystLmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) ULONG ulReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) ULONG ulSystemConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) ULONG ulCPUCapInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) ULONG ulReserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) USHORT usGPUReservedSysMemSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) USHORT usExtDispConnInfoOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) USHORT usPanelRefreshRateRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) UCHAR ucMemoryType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) UCHAR ucUMAChannelNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) UCHAR strVBIOSMsg[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) ATOM_TDP_CONFIG asTdpConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) ULONG ulReserved[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) ULONG ulGMCRestoreResetTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) ULONG ulReserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) ULONG ulIdleNClk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) ULONG ulDDR_DLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) ULONG ulDDR_PLL_PowerUpTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) USHORT usPCIEClkSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) USHORT usPCIEClkSSType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) USHORT usLvdsSSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) USHORT usLvdsSSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) USHORT usHDMISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) USHORT usHDMISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) USHORT usDVISSPercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) USHORT usDVISSpreadRateIn10Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) ULONG ulGPUReservedSysMemBaseAddrLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) ULONG ulGPUReservedSysMemBaseAddrHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) ULONG ulReserved5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) USHORT usMaxLVDSPclkFreqInSingleLink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) UCHAR ucLvdsMisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) UCHAR ucTravisLVDSVolAdjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) UCHAR ucLVDSOffToOnDelay_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) UCHAR ucMinAllowedBL_Level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) ULONG ulLCDBitDepthControlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) ULONG ulNbpStateMemclkFreq[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) ULONG ulReserved6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) ULONG ulNbpStateNClkFreq[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) USHORT usNBPStateVoltage[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) USHORT usBootUpNBVoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) USHORT usReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) }ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) /**********************************************************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) ATOM_DEVICE_CRT1_SUPPORT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) ATOM_DEVICE_DFP1_SUPPORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) ATOM_DEVICE_DFP6_SUPPORT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) ATOM_DEVICE_DFP2_SUPPORT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) ATOM_DEVICE_DFP3_SUPPORT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) ATOM_DEVICE_DFP4_SUPPORT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) ATOM_DEVICE_DFP5_SUPPORT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) ATOM_DEVICE_LCD1_SUPPORT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) bit[3]=0: VBIOS fast boot is disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) ulGPUCapInfo: bit[0~2]= Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) bit[3]=0: Enable AUX HW mode detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) =1: Disable AUX HW mode detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) bit[4]=0: Disable DFS bypass feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) =1: Enable DFS bypass feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) Changing BL using VBIOS function is functional in both driver and non-driver present environment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) that BL control from GPU is expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) it's per platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) and enabling VariBri under the driver environment from PP table is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) =1: PCIE Power Gating Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) Bit[1]=0: DDR-DLL shut-down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) 1: DDR-DLL shut-down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) Bit[2]=0: DDR-PLL Power down feature disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) 1: DDR-PLL Power down feature enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) Bit[3]=0: GNB DPM is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) =1: GNB DPM is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) ulCPUCapInfo: TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) to indicate a range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) ucUMAChannelNumber: System memory channel numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) strVBIOSMsg[40]: VBIOS boot up customized message string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) value to program Travis register LVDS_CTRL_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) ucLVDSPwrOnSeqDIGONtoDE_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) ucLVDSPwrOnDEtoVARY_BL_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) ucLVDSPwrOffVARY_BLtoDE_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) ucLVDSPwrOffDEtoDIGON_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) ucLVDSOffToOnDelay_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) =0 means to use VBIOS default delay which is 125 ( 500ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) =0 means to use VBIOS default delay which is 0 ( 0ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) =0 means to use VBIOS default delay which is 0 ( 0ms ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) sExtDispConnInfo: Display connector information table provided to VBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) **********************************************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) // this Table is used for Kaveri/Kabini APU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) }ATOM_FUSION_SYSTEM_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) /**************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) //Memory SS Info Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) //Define Memory Clock SS chip ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) #define ICS91719 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) #define ICS91720 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) typedef struct _ATOM_I2C_DATA_RECORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) }ATOM_I2C_DATA_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) UCHAR ucSSChipID; //SS chip being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) UCHAR ucNumOfI2CDataRecords; //number of data block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) ATOM_I2C_DATA_RECORD asI2CData[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) }ATOM_I2C_DEVICE_SETUP_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) typedef struct _ATOM_ASIC_MVDD_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) }ATOM_ASIC_MVDD_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) /**************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) typedef struct _ATOM_ASIC_SS_ASSIGNMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) UCHAR ucClockIndication; //Indicate which clock source needs SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) }ATOM_ASIC_SS_ASSIGNMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) //SS is not required or enabled if a match is not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) #define ASIC_INTERNAL_MEMORY_SS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) #define ASIC_INTERNAL_ENGINE_SS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) #define ASIC_INTERNAL_UVD_SS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) #define ASIC_INTERNAL_SS_ON_TMDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) #define ASIC_INTERNAL_SS_ON_HDMI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) #define ASIC_INTERNAL_SS_ON_LVDS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) #define ASIC_INTERNAL_SS_ON_DP 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) #define ASIC_INTERNAL_SS_ON_DCPLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) #define ASIC_INTERNAL_VCE_SS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) #define ASIC_INTERNAL_GPUPLL_SS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) UCHAR ucClockIndication; //Indicate which clock source needs SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) }ATOM_ASIC_SS_ASSIGNMENT_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) //ucSpreadSpectrumMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) //#define ATOM_INTERNAL_SS_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) //#define ATOM_EXTERNAL_SS_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) }ATOM_ASIC_INTERNAL_SS_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) }ATOM_ASIC_INTERNAL_SS_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) UCHAR ucClockIndication; //Indicate which clock source needs SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) }ATOM_ASIC_SS_ASSIGNMENT_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) }ATOM_ASIC_INTERNAL_SS_INFO_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) //==============================Scratch Pad Definition Portion===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) #define ATOM_DEVICE_CONNECT_INFO_DEF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) #define ATOM_ROM_LOCATION_DEF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) #define ATOM_TV_STANDARD_DEF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) #define ATOM_ACTIVE_INFO_DEF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) #define ATOM_LCD_INFO_DEF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) #define ATOM_DOS_REQ_INFO_DEF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) #define ATOM_ACC_CHANGE_INFO_DEF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) #define ATOM_DOS_MODE_INFO_DEF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) #define ATOM_I2C_CHANNEL_STATUS_DEF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) #define ATOM_I2C_CHANNEL_STATUS1_DEF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) #define ATOM_INTERNAL_TIMER_DEF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) // BIOS_0_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) #define ATOM_S0_CRT1_MONO 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) #define ATOM_S0_CRT1_COLOR 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) #define ATOM_S0_TV1_SVIDEO_A 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) #define ATOM_S0_CV_A 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) #define ATOM_S0_CV_DIN_A 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) #define ATOM_S0_CRT2_MONO 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) #define ATOM_S0_CRT2_COLOR 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) #define ATOM_S0_TV1_COMPOSITE 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) #define ATOM_S0_TV1_SVIDEO 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) #define ATOM_S0_TV1_SCART 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) #define ATOM_S0_CV 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) #define ATOM_S0_CV_DIN 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) #define ATOM_S0_DFP1 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) #define ATOM_S0_DFP2 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) #define ATOM_S0_LCD1 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) #define ATOM_S0_LCD2 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) #define ATOM_S0_DFP6 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) #define ATOM_S0_DFP3 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) #define ATOM_S0_DFP4 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) #define ATOM_S0_DFP5 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) #define ATOM_S0_THERMAL_STATE_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) //Byte aligned definition for BIOS usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) #define ATOM_S0_CRT1_MONOb0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) #define ATOM_S0_CRT1_COLORb0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) #define ATOM_S0_TV1_COMPOSITEb0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) #define ATOM_S0_TV1_SVIDEOb0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) #define ATOM_S0_CVb0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) #define ATOM_S0_CV_DINb0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) #define ATOM_S0_CRT2_MONOb1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) #define ATOM_S0_CRT2_COLORb1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) #define ATOM_S0_TV1_COMPOSITEb1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) #define ATOM_S0_TV1_SVIDEOb1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) #define ATOM_S0_TV1_SCARTb1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) #define ATOM_S0_CVb1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) #define ATOM_S0_CV_DINb1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) #define ATOM_S0_DFP1b2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) #define ATOM_S0_DFP2b2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) #define ATOM_S0_LCD1b2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) #define ATOM_S0_LCD2b2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) #define ATOM_S0_DFP6b2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) #define ATOM_S0_DFP3b2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) #define ATOM_S0_DFP4b2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) #define ATOM_S0_DFP5b2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) #define ATOM_S0_THERMAL_STATE_SHIFTb3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) #define ATOM_S0_LCD1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) // BIOS_1_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) // BIOS_2_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) //Byte aligned definition for BIOS usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) // BIOS_3_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) #define ATOM_S3_CRT1_ACTIVE 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) #define ATOM_S3_LCD1_ACTIVE 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) #define ATOM_S3_TV1_ACTIVE 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) #define ATOM_S3_DFP1_ACTIVE 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) #define ATOM_S3_CRT2_ACTIVE 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) #define ATOM_S3_LCD2_ACTIVE 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) #define ATOM_S3_DFP6_ACTIVE 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) #define ATOM_S3_DFP2_ACTIVE 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) #define ATOM_S3_CV_ACTIVE 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) #define ATOM_S3_DFP3_ACTIVE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) #define ATOM_S3_DFP4_ACTIVE 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) #define ATOM_S3_DFP5_ACTIVE 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) //Below two definitions are not supported in pplib, but in the old powerplay in DAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) //Byte aligned definition for BIOS usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) #define ATOM_S3_CRT1_ACTIVEb0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) #define ATOM_S3_LCD1_ACTIVEb0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) #define ATOM_S3_TV1_ACTIVEb0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) #define ATOM_S3_DFP1_ACTIVEb0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) #define ATOM_S3_CRT2_ACTIVEb0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) #define ATOM_S3_LCD2_ACTIVEb0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) #define ATOM_S3_DFP6_ACTIVEb0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) #define ATOM_S3_DFP2_ACTIVEb0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) #define ATOM_S3_CV_ACTIVEb1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) #define ATOM_S3_DFP3_ACTIVEb1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) #define ATOM_S3_DFP4_ACTIVEb1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) #define ATOM_S3_DFP5_ACTIVEb1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) // BIOS_4_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) #define ATOM_S4_LCD1_REFRESH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) //Byte aligned definition for BIOS usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) #define ATOM_S5_DOS_REQ_CRT1b0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) #define ATOM_S5_DOS_REQ_LCD1b0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) #define ATOM_S5_DOS_REQ_TV1b0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) #define ATOM_S5_DOS_REQ_DFP1b0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) #define ATOM_S5_DOS_REQ_CRT2b0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) #define ATOM_S5_DOS_REQ_LCD2b0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) #define ATOM_S5_DOS_REQ_DFP6b0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) #define ATOM_S5_DOS_REQ_DFP2b0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) #define ATOM_S5_DOS_REQ_CVb1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) #define ATOM_S5_DOS_REQ_DFP3b1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) #define ATOM_S5_DOS_REQ_DFP4b1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) #define ATOM_S5_DOS_REQ_DFP5b1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) #define ATOM_S5_DOS_REQ_CRT1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) #define ATOM_S5_DOS_REQ_LCD1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) #define ATOM_S5_DOS_REQ_TV1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) #define ATOM_S5_DOS_REQ_DFP1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) #define ATOM_S5_DOS_REQ_CRT2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) #define ATOM_S5_DOS_REQ_LCD2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) #define ATOM_S5_DOS_REQ_DFP6 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) #define ATOM_S5_DOS_REQ_DFP2 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) #define ATOM_S5_DOS_REQ_CV 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) #define ATOM_S5_DOS_REQ_DFP3 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) #define ATOM_S5_DOS_REQ_DFP4 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) #define ATOM_S5_DOS_REQ_DFP5 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) (ATOM_S5_DOS_FORCE_CVb3<<8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) // BIOS_6_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) #define ATOM_S6_DEVICE_CHANGE 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) #define ATOM_S6_SCALER_CHANGE 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) #define ATOM_S6_LID_CHANGE 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) #define ATOM_S6_DOCKING_CHANGE 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) #define ATOM_S6_ACC_MODE 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) #define ATOM_S6_LID_STATE 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) #define ATOM_S6_DOCK_STATE 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) #define ATOM_S6_CRITICAL_STATE 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) #define ATOM_S6_ACC_REQ_CRT1 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) #define ATOM_S6_ACC_REQ_LCD1 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) #define ATOM_S6_ACC_REQ_TV1 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) #define ATOM_S6_ACC_REQ_DFP1 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) #define ATOM_S6_ACC_REQ_CRT2 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) #define ATOM_S6_ACC_REQ_LCD2 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) #define ATOM_S6_ACC_REQ_DFP6 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) #define ATOM_S6_ACC_REQ_DFP2 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) #define ATOM_S6_ACC_REQ_CV 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) #define ATOM_S6_ACC_REQ_DFP3 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) #define ATOM_S6_ACC_REQ_DFP4 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) #define ATOM_S6_ACC_REQ_DFP5 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) //Byte aligned definition for BIOS usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) #define ATOM_S6_DEVICE_CHANGEb0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) #define ATOM_S6_SCALER_CHANGEb0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) #define ATOM_S6_LID_CHANGEb0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) #define ATOM_S6_DOCKING_CHANGEb0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) #define ATOM_S6_ACC_MODEb0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) #define ATOM_S6_LID_STATEb0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) #define ATOM_S6_DOCK_STATEb0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) #define ATOM_S6_CRITICAL_STATEb1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) #define ATOM_S6_ACC_REQ_CRT1b2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) #define ATOM_S6_ACC_REQ_LCD1b2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) #define ATOM_S6_ACC_REQ_TV1b2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) #define ATOM_S6_ACC_REQ_DFP1b2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) #define ATOM_S6_ACC_REQ_CRT2b2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) #define ATOM_S6_ACC_REQ_LCD2b2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) #define ATOM_S6_ACC_REQ_DFP6b2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) #define ATOM_S6_ACC_REQ_DFP2b2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) #define ATOM_S6_ACC_REQ_CVb3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) #define ATOM_S6_ACC_REQ_DFP3b3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) #define ATOM_S6_ACC_REQ_DFP4b3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) #define ATOM_S6_ACC_REQ_DFP5b3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) #define ATOM_S6_DEVICE_CHANGE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) #define ATOM_S6_SCALER_CHANGE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) #define ATOM_S6_LID_CHANGE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) #define ATOM_S6_DOCKING_CHANGE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) #define ATOM_S6_ACC_MODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) #define ATOM_S6_LID_STATE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) #define ATOM_S6_DOCK_STATE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) #define ATOM_S6_CRITICAL_STATE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) #define ATOM_S6_REQ_SCALER_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) #define ATOM_S7_DOS_MODE_TYPEb0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) #define ATOM_S7_DOS_MODE_VGAb0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) #define ATOM_S7_DOS_MODE_VESAb0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) #define ATOM_S7_DOS_MODE_EXTb0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) // BIOS_8_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) // BIOS_9_SCRATCH Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) #define ATOM_FLAG_SET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) #define ATOM_FLAG_CLEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) //Portion II: Definitinos only used in Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) // Macros used by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) #ifdef __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) #else // not __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) #endif // __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) //Portion III: Definitinos only used in VBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) #define ATOM_DAC_SRC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) #define ATOM_SRC_DAC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) #define ATOM_SRC_DAC2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) typedef struct _MEMORY_PLLINIT_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) ULONG ulTargetMemoryClock; //In 10Khz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) UCHAR ucAction; //not define yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) UCHAR ucFbDiv; //FB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) UCHAR ucPostDiv; //Post div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) }MEMORY_PLLINIT_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) #define GPIO_PIN_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) #define GPIO_PIN_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) typedef struct _GPIO_PIN_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) UCHAR ucGPIO_ID; //return value, read from GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) }GPIO_PIN_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) typedef struct _ENABLE_SCALER_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) UCHAR ucTVStandard; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) UCHAR ucPadding[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) }ENABLE_SCALER_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) //ucEnable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) #define SCALER_ENABLE_2TAP_ALPHA_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) #define SCALER_ENABLE_MULTITAP_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) ENABLE_CRTC_PARAMETERS sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) USHORT usHight; // Image Hight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) USHORT usWidth; // Image Width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) UCHAR ucSurface; // Surface 1 or 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) UCHAR ucPadding[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) }ENABLE_GRAPH_SURFACE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) USHORT usHight; // Image Hight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) USHORT usWidth; // Image Width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) UCHAR ucSurface; // Surface 1 or 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) USHORT usHight; // Image Hight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) USHORT usWidth; // Image Width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) UCHAR ucSurface; // Surface 1 or 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) USHORT usHight; // Image Hight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) USHORT usWidth; // Image Width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) USHORT usGraphPitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) UCHAR ucColorDepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) UCHAR ucPixelFormat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) UCHAR ucSurface; // Surface 1 or 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) UCHAR ucModeType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) // ucEnable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) typedef struct _MEMORY_CLEAN_UP_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) USHORT usMemorySize; //8Kb blocks aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) }MEMORY_CLEAN_UP_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) USHORT usY_Size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) USHORT usSurface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) USHORT usY_Size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) USHORT usDispXStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) USHORT usDispYStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) UCHAR ucLutId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) USHORT usLutStartIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) USHORT usLutLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) USHORT usLutOffsetInVram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) }PALETTE_DATA_CONTROL_PARAMETERS_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) // ucAction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) #define PALETTE_DATA_AUTO_FILL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) #define PALETTE_DATA_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) #define PALETTE_DATA_WRITE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) UCHAR ucInterruptId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) UCHAR ucServiceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) UCHAR ucStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) }INTERRUPT_SERVICE_PARAMETER_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) // ucInterruptId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) #define HDP1_INTERRUPT_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) #define HDP2_INTERRUPT_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) #define HDP3_INTERRUPT_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) #define HDP4_INTERRUPT_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) #define HDP5_INTERRUPT_ID 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) #define HDP6_INTERRUPT_ID 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) #define SW_INTERRUPT_ID 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) // ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) #define INTERRUPT_SERVICE_GEN_SW_INT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) #define INTERRUPT_SERVICE_GET_STATUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) // ucStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) #define INTERRUPT_STATUS__INT_TRIGGER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) #define INTERRUPT_STATUS__HPD_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) typedef struct _INDIRECT_IO_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) UCHAR IOAccessSequence[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) } INDIRECT_IO_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) #define INDIRECT_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) #define INDIRECT_WRITE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) #define INDIRECT_IO_MM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) #define INDIRECT_IO_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) #define INDIRECT_IO_MC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) #define INDIRECT_IO_PCIE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) #define INDIRECT_IO_PCIEP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) #define INDIRECT_IO_NBMISC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) #define INDIRECT_IO_SMU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) typedef struct _ATOM_OEM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) }ATOM_OEM_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) typedef struct _ATOM_TV_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) UCHAR ucVMode_Num; //Video mode number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) UCHAR ucTV_Mode_Num; //Internal TV mode number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) }ATOM_TV_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) typedef struct _ATOM_BIOS_INT_TVSTD_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) }ATOM_BIOS_INT_TVSTD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) typedef struct _ATOM_TV_MODE_SCALER_PTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) UCHAR ucTV_Mode_Num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) }ATOM_TV_MODE_SCALER_PTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) typedef struct _ATOM_STANDARD_VESA_TIMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) }ATOM_STANDARD_VESA_TIMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) typedef struct _ATOM_STD_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) USHORT usSTD_HDisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) USHORT usSTD_VDisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) USHORT usSTD_RefreshRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) }ATOM_STD_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) typedef struct _ATOM_VESA_TO_EXTENDED_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) USHORT usVESA_ModeNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) USHORT usExtendedModeNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) }ATOM_VESA_TO_EXTENDED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) }ATOM_VESA_TO_INTENAL_MODE_LUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) /*************** ATOM Memory Related Data Structure ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) UCHAR ucMemoryType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) UCHAR ucMemoryVendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) UCHAR ucAdjMCId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) UCHAR ucDynClkId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) ULONG ulDllResetClkRange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) }ATOM_MEMORY_VENDOR_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) ULONG ucMemBlkId:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) ULONG ulMemClockRange:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) ULONG ulMemClockRange:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) ULONG ucMemBlkId:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) }ATOM_MEMORY_SETTING_ID_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) ULONG ulAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) ULONG aulMemData[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) }ATOM_MEMORY_SETTING_DATA_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) USHORT usRegIndex; // MC register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) }ATOM_INIT_REG_INDEX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) typedef struct _ATOM_INIT_REG_BLOCK{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) USHORT usRegIndexTblSize; //size of asRegIndexBuf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) }ATOM_INIT_REG_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) #define END_OF_REG_INDEX_BLOCK 0x0ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) #define END_OF_REG_DATA_BLOCK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) #define CLOCK_RANGE_HIGHEST 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) #define VALUE_DWORD SIZEOF ULONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) #define VALUE_SAME_AS_ABOVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) #define VALUE_MASK_DWORD 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) #define ACCESS_PLACEHOLDER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) typedef struct _ATOM_MC_INIT_PARAM_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) USHORT usAdjustARB_SEQDataOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) USHORT usMCInitMemTypeTblOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) USHORT usMCInitCommonTblOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) USHORT usMCInitPowerDownTblOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) ULONG ulARB_SEQDataBuf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) ATOM_INIT_REG_BLOCK asMCInitMemType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) ATOM_INIT_REG_BLOCK asMCInitCommon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) }ATOM_MC_INIT_PARAM_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) #define _4Mx16 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) #define _4Mx32 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) #define _8Mx16 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) #define _8Mx32 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) #define _16Mx16 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) #define _16Mx32 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) #define _32Mx16 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) #define _32Mx32 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) #define _64Mx8 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) #define _64Mx16 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) #define _64Mx32 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) #define _128Mx8 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) #define _128Mx16 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) #define _128Mx32 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) #define _256Mx8 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) #define _256Mx16 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) #define _512Mx8 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) #define SAMSUNG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) #define INFINEON 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) #define ELPIDA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) #define ETRON 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) #define NANYA 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) #define HYNIX 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) #define MOSEL 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) #define WINBOND 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) #define ESMT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) #define MICRON 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) #define QIMONDA INFINEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) #define PROMOS MOSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) #define KRETON INFINEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) #define ELIXIR NANYA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) #define MEZZA ELPIDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) #define UCODE_ROM_START_ADDRESS 0x1b800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) //uCode block header for reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) typedef struct _MCuCodeHeader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) ULONG ulSignature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) UCHAR ucRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) UCHAR ucChecksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) UCHAR ucReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) UCHAR ucReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) USHORT usParametersLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) USHORT usUCodeLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) USHORT usReserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) USHORT usReserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) } MCuCodeHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) //////////////////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) typedef struct _ATOM_VRAM_MODULE_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) USHORT usEMRSValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) USHORT usMRSValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) UCHAR ucRow; // Number of Row,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) UCHAR ucColumn; // Number of Column,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) UCHAR ucBank; // Nunber of Bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) UCHAR ucRank; // Number of Rank, in power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) UCHAR ucChannelNum; // Number of channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) }ATOM_VRAM_MODULE_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) typedef struct _ATOM_VRAM_MODULE_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) ULONG ulFlags; // To enable/disable functionalities based on memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) ULONG ulEngineClock; // Override of default engine clock for particular memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) ULONG ulMemoryClock; // Override of default memory clock for particular memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) USHORT usEMRSValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) USHORT usMRSValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) UCHAR ucRow; // Number of Row,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) UCHAR ucColumn; // Number of Column,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) UCHAR ucBank; // Nunber of Bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) UCHAR ucRank; // Number of Rank, in power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) UCHAR ucChannelNum; // Number of channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) UCHAR ucRefreshRateFactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) }ATOM_VRAM_MODULE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) typedef struct _ATOM_MEMORY_TIMING_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) USHORT usMRS; // mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) USHORT usDDR3_MR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) USHORT usEMRS; // extended mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) USHORT usDDR3_MR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) UCHAR ucCL; // CAS latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) UCHAR ucWL; // WRITE Latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) UCHAR uctRAS; // tRAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) UCHAR uctRC; // tRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) UCHAR uctRFC; // tRFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) UCHAR uctRCDR; // tRCDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) UCHAR uctRCDW; // tRCDW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) UCHAR uctRP; // tRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) UCHAR uctRRD; // tRRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) UCHAR uctWR; // tWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) UCHAR uctWTR; // tWTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) UCHAR uctPDIX; // tPDIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) UCHAR uctFAW; // tFAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) UCHAR uctAOND; // tAOND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) USHORT usDDR3_MR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) }ATOM_MEMORY_TIMING_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) USHORT usMRS; // mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) USHORT usEMRS; // extended mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) UCHAR ucCL; // CAS latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) UCHAR ucWL; // WRITE Latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) UCHAR uctRAS; // tRAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) UCHAR uctRC; // tRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) UCHAR uctRFC; // tRFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) UCHAR uctRCDR; // tRCDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) UCHAR uctRCDW; // tRCDW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) UCHAR uctRP; // tRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) UCHAR uctRRD; // tRRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) UCHAR uctWR; // tWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) UCHAR uctWTR; // tWTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) UCHAR uctPDIX; // tPDIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) UCHAR uctFAW; // tFAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) UCHAR uctAOND; // tAOND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) ////////////////////////////////////GDDR parameters///////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) UCHAR uctCCDL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) UCHAR uctCRCRL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) UCHAR uctCRCWL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) UCHAR uctCKE; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) UCHAR uctCKRSE; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) UCHAR uctCKRSX; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) UCHAR uctFAW32; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) UCHAR ucMR5lo; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) UCHAR ucMR5hi; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) UCHAR ucTerminator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) }ATOM_MEMORY_TIMING_FORMAT_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) USHORT usMRS; // mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) USHORT usEMRS; // extended mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) UCHAR ucCL; // CAS latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) UCHAR ucWL; // WRITE Latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) UCHAR uctRAS; // tRAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) UCHAR uctRC; // tRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) UCHAR uctRFC; // tRFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) UCHAR uctRCDR; // tRCDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) UCHAR uctRCDW; // tRCDW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) UCHAR uctRP; // tRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) UCHAR uctRRD; // tRRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) UCHAR uctWR; // tWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) UCHAR uctWTR; // tWTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) UCHAR uctPDIX; // tPDIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) UCHAR uctFAW; // tFAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) UCHAR uctAOND; // tAOND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) ////////////////////////////////////GDDR parameters///////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) UCHAR uctCCDL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) UCHAR uctCRCRL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) UCHAR uctCRCWL; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) UCHAR uctCKE; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) UCHAR uctCKRSE; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) UCHAR uctCKRSX; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) UCHAR uctFAW32; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) UCHAR ucMR4lo; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) UCHAR ucMR4hi; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) UCHAR ucMR5lo; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) UCHAR ucMR5hi; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) UCHAR ucTerminator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) }ATOM_MEMORY_TIMING_FORMAT_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) typedef struct _ATOM_MEMORY_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) USHORT usDDR3_Reserved; // Not used for DDR3 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) USHORT usDDR3_MR3; // Used for DDR3 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) UCHAR ucRow; // Number of Row,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) UCHAR ucColumn; // Number of Column,in power of 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) UCHAR ucBank; // Nunber of Bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) UCHAR ucRank; // Number of Rank, in power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) }ATOM_MEMORY_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) typedef struct _ATOM_VRAM_MODULE_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) USHORT usSize; // size of ATOM_VRAM_MODULE_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) UCHAR ucChannelNum; // board dependent parameter:Number of channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) UCHAR ucFlag; // To enable/disable functionalities based on memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) }ATOM_VRAM_MODULE_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) //ATOM_VRAM_MODULE_V3.ucNPL_RT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) #define NPL_RT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) #define BATTERY_ODT_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) typedef struct _ATOM_VRAM_MODULE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) UCHAR ucChannelNum; // Number of channels present in this module config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) UCHAR ucFlag; // To enable/disable functionalities based on memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) UCHAR ucVREFI; // board dependent parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) USHORT usDDR3_Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) union{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) USHORT usDDR3_MR3; // Used for DDR3 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) UCHAR ucReserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) }ATOM_VRAM_MODULE_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) #define VRAM_MODULE_V4_MISC_BL_MASK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) #define VRAM_MODULE_V4_MISC_BL8 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) typedef struct _ATOM_VRAM_MODULE_V5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) UCHAR ucChannelNum; // Number of channels present in this module config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) UCHAR ucFlag; // To enable/disable functionalities based on memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) UCHAR ucVREFI; // board dependent parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) }ATOM_VRAM_MODULE_V5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) typedef struct _ATOM_VRAM_MODULE_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) UCHAR ucChannelNum; // Number of channels present in this module config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) UCHAR ucFlag; // To enable/disable functionalities based on memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) UCHAR ucVREFI; // board dependent parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) }ATOM_VRAM_MODULE_V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) typedef struct _ATOM_VRAM_MODULE_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) // Design Specific Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) USHORT usEnableChannels; // bit vector which indicate which channels are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) UCHAR ucExtMemoryID; // Current memory module ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) UCHAR ucChannelNum; // Number of mem. channels supported in this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) UCHAR ucVREFI; // Not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) USHORT usSEQSettingOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) // Memory Module specific values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) USHORT usEMRS2Value; // EMRS2/MR2 Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) USHORT usEMRS3Value; // EMRS3/MR3 Value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) char strMemPNString[20]; // part number end with '0'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) }ATOM_VRAM_MODULE_V7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) typedef struct _ATOM_VRAM_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) UCHAR ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) }ATOM_VRAM_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) typedef struct _ATOM_VRAM_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) USHORT usRerseved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) UCHAR ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) // ATOM_INIT_REG_BLOCK aMemAdjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) }ATOM_VRAM_INFO_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) typedef struct _ATOM_VRAM_INFO_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) USHORT usRerseved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) UCHAR ucReservde[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) UCHAR ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) // ATOM_INIT_REG_BLOCK aMemAdjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) }ATOM_VRAM_INFO_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) USHORT usReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) }ATOM_VRAM_INFO_HEADER_V2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) }ATOM_VRAM_GPIO_DETECTION_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) typedef struct _ATOM_MEMORY_TRAINING_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) UCHAR ucTrainingLoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) ATOM_INIT_REG_BLOCK asMemTrainingSetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) }ATOM_MEMORY_TRAINING_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) typedef struct SW_I2C_CNTL_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) UCHAR ucControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) UCHAR ucData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) UCHAR ucSatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) UCHAR ucTemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) } SW_I2C_CNTL_DATA_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) typedef struct _SW_I2C_IO_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) USHORT GPIO_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) UCHAR ucAct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) UCHAR ucData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) } SW_I2C_IO_DATA_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) /****************************SW I2C CNTL DEFINITIONS**********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) #define SW_I2C_IO_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) #define SW_I2C_IO_GET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) #define SW_I2C_IO_DRIVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) #define SW_I2C_IO_SET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) #define SW_I2C_IO_START 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) #define SW_I2C_IO_CLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) #define SW_I2C_IO_DATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) #define SW_I2C_IO_ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) #define SW_I2C_IO_ONE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) #define SW_I2C_CNTL_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) #define SW_I2C_CNTL_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) #define SW_I2C_CNTL_START 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) #define SW_I2C_CNTL_STOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) #define SW_I2C_CNTL_OPEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) #define SW_I2C_CNTL_CLOSE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) #define SW_I2C_CNTL_WRITE1BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) //==============================VESA definition Portion===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) #define VESA_OEM_PRODUCT_REV "01.00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) #define VESA_MODE_WIN_ATTRIBUTE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) #define VESA_WIN_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) typedef struct _PTR_32_BIT_STRUCTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) USHORT Offset16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) USHORT Segment16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) } PTR_32_BIT_STRUCTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) typedef union _PTR_32_BIT_UNION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) PTR_32_BIT_STRUCTURE SegmentOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) ULONG Ptr32_Bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) } PTR_32_BIT_UNION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) UCHAR VbeSignature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) USHORT VbeVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) PTR_32_BIT_UNION OemStringPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) UCHAR Capabilities[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) PTR_32_BIT_UNION VideoModePtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) USHORT TotalMemory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) } VBE_1_2_INFO_BLOCK_UPDATABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) USHORT OemSoftRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) PTR_32_BIT_UNION OemVendorNamePtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) PTR_32_BIT_UNION OemProductNamePtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) PTR_32_BIT_UNION OemProductRevPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) } VBE_2_0_INFO_BLOCK_UPDATABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) typedef union _VBE_VERSION_UNION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) } VBE_VERSION_UNION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) typedef struct _VBE_INFO_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) VBE_VERSION_UNION UpdatableVBE_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) UCHAR Reserved[222];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) UCHAR OemData[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) } VBE_INFO_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) typedef struct _VBE_FP_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) USHORT HSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) USHORT VSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) USHORT FPType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) UCHAR RedBPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) UCHAR GreenBPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) UCHAR BlueBPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) UCHAR ReservedBPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) ULONG RsvdOffScrnMemSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) ULONG RsvdOffScrnMEmPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) UCHAR Reserved[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) } VBE_FP_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) typedef struct _VESA_MODE_INFO_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) // Mandatory information for all VBE revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) USHORT ModeAttributes; // dw ? ; mode attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) UCHAR WinAAttributes; // db ? ; window A attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) UCHAR WinBAttributes; // db ? ; window B attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) USHORT WinGranularity; // dw ? ; window granularity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) USHORT WinSize; // dw ? ; window size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) USHORT WinASegment; // dw ? ; window A start segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) USHORT WinBSegment; // dw ? ; window B start segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) USHORT BytesPerScanLine;// dw ? ; bytes per scan line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) //; Mandatory information for VBE 1.2 and above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) UCHAR XCharSize; // db ? ; character cell width in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) UCHAR YCharSize; // db ? ; character cell height in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) UCHAR NumberOfPlanes; // db ? ; number of memory planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) UCHAR BitsPerPixel; // db ? ; bits per pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) UCHAR NumberOfBanks; // db ? ; number of banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) UCHAR MemoryModel; // db ? ; memory model type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) UCHAR BankSize; // db ? ; bank size in KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) UCHAR NumberOfImagePages;// db ? ; number of images
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) //; Direct Color fields(required for direct/6 and YUV/7 memory models)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) //; Mandatory information for VBE 2.0 and above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) ULONG Reserved_1; // dd 0 ; reserved - always set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) USHORT Reserved_2; // dw 0 ; reserved - always set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) //; Mandatory information for VBE 3.0 and above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) UCHAR Reserved; // db 190 dup (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) } VESA_MODE_INFO_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) // BIOS function CALLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) #define ATOM_BIOS_FUNCTION_COP_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) #define ATOM_BIOS_FUNCTION_STV_STD 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) // structure used for VBIOS only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) //DispOutInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) typedef struct _ASIC_TRANSMITTER_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) USHORT usTransmitterObjId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) USHORT usSupportDevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) UCHAR ucTransmitterCmdTblId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) UCHAR ucEncoderID; //available 1st encoder ( default )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) UCHAR uc2ndEncoderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) }ASIC_TRANSMITTER_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) typedef struct _ASIC_ENCODER_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) UCHAR ucEncoderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) UCHAR ucEncoderConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) USHORT usEncoderCmdTblId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) }ASIC_ENCODER_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) typedef struct _ATOM_DISP_OUT_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) USHORT ptrTransmitterInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) USHORT ptrEncoderInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) ASIC_ENCODER_INFO asEncoderInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) }ATOM_DISP_OUT_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) typedef struct _ATOM_DISP_OUT_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) USHORT ptrTransmitterInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) USHORT ptrEncoderInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) ASIC_ENCODER_INFO asEncoderInfo[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) }ATOM_DISP_OUT_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) typedef struct _ATOM_DISP_CLOCK_ID {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) UCHAR ucPpllId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) UCHAR ucPpllAttribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) }ATOM_DISP_CLOCK_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) // ucPpllAttribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) #define CLOCK_SOURCE_SHAREABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) #define CLOCK_SOURCE_DP_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) #define CLOCK_SOURCE_NONE_DP_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) //DispOutInfoTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) typedef struct _ASIC_TRANSMITTER_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) USHORT usTransmitterObjId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) UCHAR ucTransmitterCmdTblId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) UCHAR ucConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) UCHAR ucEncoderID; // available 1st encoder ( default )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) UCHAR uc2ndEncoderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) }ASIC_TRANSMITTER_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) typedef struct _ATOM_DISP_OUT_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) USHORT ptrTransmitterInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) USHORT ptrEncoderInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) UCHAR ucDCERevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) UCHAR ucMaxDispEngineNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) UCHAR ucMaxActiveDispEngineNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) UCHAR ucMaxPPLLNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) UCHAR ucDispCaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) }ATOM_DISP_OUT_INFO_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) //ucDispCaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) typedef enum CORE_REF_CLK_SOURCE{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) CLOCK_SRC_XTALIN=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) CLOCK_SRC_XO_IN=1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) CLOCK_SRC_XO_IN2=2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) }CORE_REF_CLK_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) // DispDevicePriorityInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) USHORT asDevicePriority[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) //ProcessAuxChannelTransactionTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) USHORT lpAuxRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) USHORT lpDataOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) UCHAR ucChannelID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) UCHAR ucReplyStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) UCHAR ucDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) UCHAR ucDataOutLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) UCHAR ucReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) //ProcessAuxChannelTransactionTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) USHORT lpAuxRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) USHORT lpDataOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) UCHAR ucChannelID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) UCHAR ucReplyStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) UCHAR ucDelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) UCHAR ucDataOutLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) //GetSinkType
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) typedef struct _DP_ENCODER_SERVICE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) USHORT ucLinkClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) UCHAR ucConfig; // for DP training command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) UCHAR ucI2cId; // use for GET_SINK_TYPE command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) UCHAR ucStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) UCHAR ucLaneNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) }DP_ENCODER_SERVICE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) // ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) /* obselete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) #define ATOM_DP_ACTION_TRAINING_START 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) #define ATOM_DP_ACTION_BLANKING 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) // ucConfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) #define ATOM_DP_CONFIG_LINK_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) #define ATOM_DP_CONFIG_LINK_B 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) /* /obselete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) UCHAR ucAuxId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) UCHAR ucAction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) UCHAR ucSinkType; // Iput and Output parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) UCHAR ucReserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) }DP_ENCODER_SERVICE_PARAMETERS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) // ucAction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) // DP_TRAINING_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) UCHAR ucI2CSpeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) UCHAR ucRegIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) UCHAR ucStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) USHORT lpI2CDataOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) UCHAR ucFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) UCHAR ucTransBytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) UCHAR ucSlaveAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) UCHAR ucLineNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) //ucFlag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) #define HW_I2C_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) #define HW_I2C_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) #define I2C_2BYTE_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) // Structures used by HW_Misc_OperationTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) UCHAR ucCmd; // Input: To tell which action to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) UCHAR ucReturnCode; // Output: Return value base on action was taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) ULONG ulReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) // Actions code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) #define ATOM_GET_SDI_SUPPORT 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) // Return code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) #define ATOM_UNKNOWN_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) #define ATOM_FEATURE_NOT_SUPPORTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) #define ATOM_FEATURE_SUPPORTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) }ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) UCHAR ucReserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) #define HWBLKINST_INSTANCE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) #define HWBLKINST_HWBLK_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) #define HWBLKINST_HWBLK_SHIFT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) //ucHWBlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) #define SELECT_DISP_ENGINE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) #define SELECT_DISP_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) #define SELECT_DCIO_UNIPHY_LINK0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) #define SELECT_DCIO_UNIPHY_LINK1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) #define SELECT_DCIO_IMPCAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) #define SELECT_DCIO_DIG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) #define SELECT_CRTC_PIXEL_RATE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) #define SELECT_VGA_BLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) // DIGTransmitterInfoTable structure used to program UNIPHY settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) }DIG_TRANSMITTER_INFO_HEADER_V3_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) }DIG_TRANSMITTER_INFO_HEADER_V3_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) typedef struct _CLOCK_CONDITION_REGESTER_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) USHORT usRegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) UCHAR ucStartBit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) UCHAR ucEndBit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) }CLOCK_CONDITION_REGESTER_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) USHORT usMaxClockFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) UCHAR ucEncodeMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) UCHAR ucPhySel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) ULONG ulAnalogSetting[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) }CLOCK_CONDITION_SETTING_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) typedef struct _CLOCK_CONDITION_SETTING_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) USHORT usEntrySize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) }CLOCK_CONDITION_SETTING_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) typedef struct _PHY_CONDITION_REG_VAL{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) ULONG ulCondition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) ULONG ulRegVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) }PHY_CONDITION_REG_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) typedef struct _PHY_CONDITION_REG_VAL_V2{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) ULONG ulCondition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) UCHAR ucCondition2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) ULONG ulRegVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) }PHY_CONDITION_REG_VAL_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) typedef struct _PHY_CONDITION_REG_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) USHORT usRegIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) PHY_CONDITION_REG_VAL asRegVal[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) }PHY_CONDITION_REG_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) typedef struct _PHY_CONDITION_REG_INFO_V2{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) USHORT usRegIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) PHY_CONDITION_REG_VAL_V2 asRegVal[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) }PHY_CONDITION_REG_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) typedef struct _PHY_ANALOG_SETTING_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) UCHAR ucEncodeMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) UCHAR ucPhySel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) PHY_CONDITION_REG_INFO asAnalogSetting[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) }PHY_ANALOG_SETTING_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) typedef struct _PHY_ANALOG_SETTING_INFO_V2{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) UCHAR ucEncodeMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) UCHAR ucPhySel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) USHORT usSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) }PHY_ANALOG_SETTING_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) typedef struct _GFX_HAVESTING_PARAMETERS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) UCHAR ucReserved; //reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) } GFX_HAVESTING_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) //ucGfxBlkId
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) #define GFX_HARVESTING_CU_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) #define GFX_HARVESTING_RB_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) #define GFX_HARVESTING_PRIM_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) //Portion VI: Definitinos for vbios MC scratch registers that driver used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) #define ATOM_MEM_TYPE_DDR_STRING "DDR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) #define ATOM_MEM_TYPE_DDR2_STRING "DDR2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) #define ATOM_MEM_TYPE_HBM_STRING "HBM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) #define ATOM_MEM_TYPE_DDR3_STRING "DDR3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) //Portion VI: Definitinos being oboselete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) //==========================================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) //Remove the definitions below when driver is ready!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) typedef struct _ATOM_DAC_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) USHORT usMaxFrequency; // in 10kHz unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) USHORT usReserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) }ATOM_DAC_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) typedef struct _COMPASSIONATE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) //============================== DAC1 portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) UCHAR ucDAC1_BG_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) UCHAR ucDAC1_DAC_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) USHORT usDAC1_FORCE_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) //============================== DAC2 portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) UCHAR ucDAC2_CRT2_BG_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) UCHAR ucDAC2_CRT2_DAC_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) USHORT usDAC2_CRT2_FORCE_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) USHORT usDAC2_CRT2_MUX_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) UCHAR ucDAC2_NTSC_BG_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) UCHAR ucDAC2_NTSC_DAC_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) USHORT usDAC2_TV1_FORCE_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) USHORT usDAC2_TV1_MUX_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) UCHAR ucDAC2_CV_BG_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) UCHAR ucDAC2_CV_DAC_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) USHORT usDAC2_CV_FORCE_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) USHORT usDAC2_CV_MUX_RegisterIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) UCHAR ucDAC2_PAL_BG_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) UCHAR ucDAC2_PAL_DAC_Adjustment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) USHORT usDAC2_TV2_FORCE_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) }COMPASSIONATE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) /****************************Supported Device Info Table Definitions**********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) // ucConnectInfo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) // [7:4] - connector type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) // = 1 - VGA connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) // = 2 - DVI-I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) // = 3 - DVI-D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) // = 4 - DVI-A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) // = 5 - SVIDEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) // = 6 - COMPOSITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) // = 7 - LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) // = 8 - DIGITAL LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) // = 9 - SCART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) // = 0xA - HDMI_type A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) // = 0xB - HDMI_type B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) // = 0xE - Special case1 (DVI+DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) // Others=TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) // [3:0] - DAC Associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) // = 0 - no DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) // = 1 - DACA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) // = 2 - DACB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) // = 3 - External DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) // Others=TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) typedef struct _ATOM_CONNECTOR_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) #if ATOM_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) UCHAR bfConnectorType:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) UCHAR bfAssociatedDAC:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) UCHAR bfAssociatedDAC:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) UCHAR bfConnectorType:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) }ATOM_CONNECTOR_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) typedef union _ATOM_CONNECTOR_INFO_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) ATOM_CONNECTOR_INFO sbfAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) UCHAR ucAccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) }ATOM_CONNECTOR_INFO_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) typedef struct _ATOM_CONNECTOR_INFO_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) }ATOM_CONNECTOR_INFO_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) typedef struct _ATOM_SUPPORTED_DEVICES_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) USHORT usDeviceSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) }ATOM_SUPPORTED_DEVICES_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) #define NO_INT_SRC_MAPPED 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) UCHAR ucIntSrcBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) }ATOM_CONNECTOR_INC_SRC_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) USHORT usDeviceSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) }ATOM_SUPPORTED_DEVICES_INFO_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) USHORT usDeviceSupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) }ATOM_SUPPORTED_DEVICES_INFO_2d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) typedef struct _ATOM_MISC_CONTROL_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) USHORT usFrequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) UCHAR ucPLL_DutyCycle; // PLL duty cycle control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) }ATOM_MISC_CONTROL_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) #define ATOM_MAX_MISC_INFO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) typedef struct _ATOM_TMDS_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) USHORT usMaxFrequency; // in 10Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) }ATOM_TMDS_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) UCHAR ucTVStandard; //Same as TV standards defined above,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) UCHAR ucPadding[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) }ATOM_ENCODER_ANALOG_ATTRIBUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) UCHAR ucAttribute; //Same as other digital encoder attributes defined above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) UCHAR ucPadding[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) typedef union _ATOM_ENCODER_ATTRIBUTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) }ATOM_ENCODER_ATTRIBUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) USHORT usPixelClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) USHORT usEncoderID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) ATOM_ENCODER_ATTRIBUTE usDevAttr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) }DVO_ENCODER_CONTROL_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) }DVO_ENCODER_CONTROL_PS_ALLOCATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) #define ATOM_XTMDS_ASIC_SI164_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) #define ATOM_XTMDS_ASIC_SI178_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) #define ATOM_XTMDS_ASIC_TFP513_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) #define ATOM_XTMDS_MVPU_FPGA 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) typedef struct _ATOM_XTMDS_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) USHORT usSingleLinkMaxFrequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) UCHAR ucXtransimitterID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) // due to design. This ID is used to alert driver that the sequence is not "standard"!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) }ATOM_XTMDS_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) UCHAR ucPadding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) /****************************Legacy Power Play Table Definitions **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) //Definitions for ulPowerPlayMiscInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638) #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) //ucTableFormatRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) //ucTableContentRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) typedef struct _ATOM_POWERMODE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) ULONG ulMiscInfo; //The power level should be arranged in ascending order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) ULONG ulReserved1; // must set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) ULONG ulReserved2; // must set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) USHORT usEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) USHORT usMemoryClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) UCHAR ucVoltageDropIndex; // index to GPIO table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) UCHAR ucMinTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) UCHAR ucMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) UCHAR ucNumPciELanes; // number of PCIE lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) }ATOM_POWERMODE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) //ucTableFormatRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) //ucTableContentRevision=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) typedef struct _ATOM_POWERMODE_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) ULONG ulMiscInfo; //The power level should be arranged in ascending order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) ULONG ulMiscInfo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) ULONG ulEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) ULONG ulMemoryClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) UCHAR ucVoltageDropIndex; // index to GPIO table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) UCHAR ucMinTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) UCHAR ucMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) UCHAR ucNumPciELanes; // number of PCIE lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) }ATOM_POWERMODE_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) //ucTableFormatRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) //ucTableContentRevision=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) typedef struct _ATOM_POWERMODE_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) ULONG ulMiscInfo; //The power level should be arranged in ascending order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) ULONG ulMiscInfo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) ULONG ulEngineClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) ULONG ulMemoryClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) UCHAR ucMinTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) UCHAR ucMaxTemperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) UCHAR ucNumPciELanes; // number of PCIE lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) }ATOM_POWERMODE_INFO_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) typedef struct _ATOM_POWERPLAY_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) UCHAR ucOverdriveThermalController;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) UCHAR ucOverdriveI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) UCHAR ucOverdriveIntBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) UCHAR ucOverdriveControllerAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) UCHAR ucSizeOfPowerModeEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) UCHAR ucNumOfPowerModeEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) }ATOM_POWERPLAY_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) typedef struct _ATOM_POWERPLAY_INFO_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) UCHAR ucOverdriveThermalController;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) UCHAR ucOverdriveI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) UCHAR ucOverdriveIntBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) UCHAR ucOverdriveControllerAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) UCHAR ucSizeOfPowerModeEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) UCHAR ucNumOfPowerModeEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) }ATOM_POWERPLAY_INFO_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) typedef struct _ATOM_POWERPLAY_INFO_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) ATOM_COMMON_TABLE_HEADER sHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) UCHAR ucOverdriveThermalController;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) UCHAR ucOverdriveI2cLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) UCHAR ucOverdriveIntBitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) UCHAR ucOverdriveControllerAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) UCHAR ucSizeOfPowerModeEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) UCHAR ucNumOfPowerModeEntries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) }ATOM_POWERPLAY_INFO_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) // Following definitions are for compatibility issue in different SW components.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) #define ATOM_MASTER_DATA_TABLE_REVISION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) #define Object_Info Object_Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) #define AdjustARB_SEQ MC_InitParameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) #define VRAM_GPIO_DetectionInfo VoltageObjectInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) #define ASIC_VDDCI_Info ASIC_ProfilingInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) #define ASIC_MVDDQ_Info MemoryTrainingInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) #define SS_Info PPLL_SS_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) #define ASIC_MVDDC_Info ASIC_InternalSS_Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) #define DispDevicePriorityInfo SaveRestoreInfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) #define DispOutInfo TV_VideoMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) //New device naming, remove them when both DAL/VBIOS is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) #define ATOM_DEVICE_DFP2I_INDEX 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) #define ATOM_S0_DFP1I ATOM_S0_DFP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) #define ATOM_S0_DFP1X ATOM_S0_DFP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) #define ATOM_S0_DFP2I 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) #define ATOM_S0_DFP2Ib2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) #define ATOM_S3_DFP2I_ACTIVEb1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) #define ATOM_S3_DFP2I_ACTIVE 0x00000200L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) #define ATOM_S5_DOS_REQ_DFP2I 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836) #define TMDS1XEncoderControl DVOEncoderControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) #define DFP1XOutputControl DVOOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) #define ExternalDFPOutputControl DFP1XOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) #define EnableExternalTMDS_Encoder TMDS1XEncoderControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) #define DFP1IOutputControl TMDSAOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) #define DFP2IOutputControl LVTMAOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845) #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) #define ucDac1Standard ucDacStandard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) #define ucDac2Standard ucDacStandard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854) #define TMDS1EncoderControl TMDSAEncoderControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) #define TMDS2EncoderControl LVTMAEncoderControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) #define DFP1OutputControl TMDSAOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) #define DFP2OutputControl LVTMAOutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859) #define CRT1OutputControl DAC1OutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) #define CRT2OutputControl DAC2OutputControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) //These two lines will be removed for sure in a few days, will follow up with Michael V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863) #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) #define ATOM_S6_ACC_REQ_TV2 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) #define ATOM_DEVICE_TV2_INDEX 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) #define ATOM_S0_TV2 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) #define ATOM_S2_TV1_DPMS_STATE 0x00040000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) #define ATOM_S2_TV2_DPMS_STATE 0x00400000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) #define ATOM_S2_CV_DPMS_STATE 0x01000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891) #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) #define ATOM_S2_CRT1_DPMS_STATEb2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) #define ATOM_S2_LCD1_DPMS_STATEb2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) #define ATOM_S2_TV1_DPMS_STATEb2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) #define ATOM_S2_DFP1_DPMS_STATEb2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) #define ATOM_S2_CRT2_DPMS_STATEb2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) #define ATOM_S2_LCD2_DPMS_STATEb2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) #define ATOM_S2_TV2_DPMS_STATEb2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) #define ATOM_S2_DFP2_DPMS_STATEb2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901) #define ATOM_S2_CV_DPMS_STATEb3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) #define ATOM_S2_DFP3_DPMS_STATEb3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) #define ATOM_S2_DFP4_DPMS_STATEb3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) #define ATOM_S2_DFP5_DPMS_STATEb3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) /*********************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) #pragma pack() // BIOS data must use byte alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) // AMD ACPI Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) ULONG Signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) ULONG TableLength; //Length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) UCHAR Revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) UCHAR Checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) UCHAR OemId[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) UCHAR OemTableId[8]; //UINT64 OemTableId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) ULONG OemRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) ULONG CreatorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) ULONG CreatorRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) } AMD_ACPI_DESCRIPTION_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) UINT32 Signature; //0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) UINT32 Length; //0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) UINT8 Revision; //0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) UINT8 Checksum; //0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) UINT8 OemId[6]; //0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) UINT64 OemTableId; //0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) UINT32 OemRevision; //0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) UINT32 CreatorId; //0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) UINT32 CreatorRevision; //0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942) }EFI_ACPI_DESCRIPTION_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945) AMD_ACPI_DESCRIPTION_HEADER SHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) UCHAR TableUUID[16]; //0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) ULONG Reserved[4]; //0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) }UEFI_ACPI_VFCT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) ULONG PCIBus; //0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) ULONG PCIDevice; //0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) ULONG PCIFunction; //0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) USHORT VendorID; //0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) USHORT DeviceID; //0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) USHORT SSVID; //0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) USHORT SSID; //0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) ULONG Revision; //0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) ULONG ImageLength; //0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) }VFCT_IMAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) VFCT_IMAGE_HEADER VbiosHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) UCHAR VbiosContent[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) }GOP_VBIOS_CONTENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) VFCT_IMAGE_HEADER Lib1Header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) UCHAR Lib1Content[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) }GOP_LIB1_CONTENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) #endif /* _ATOMBIOS_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) #include "pptable.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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