^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2008 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Author: Stanislaw Skowronek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef ATOM_NAMES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ATOM_NAMES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "atom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef ATOM_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ATOM_OP_NAMES_CNT 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "DEBUG", "CTB_DS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATOM_TABLE_NAMES_CNT 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "MemoryDeviceInit", "EnableYUV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ATOM_IO_NAMES_CNT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "MM", "PLL", "MC", "PCIE", "PCIE PORT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ATOM_OP_NAMES_CNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ATOM_TABLE_NAMES_CNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ATOM_IO_NAMES_CNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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