Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Xinpeng xpp055c272 5.5" MIPI-DSI panel driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2019 Theobroma Systems Design und Consulting GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Rockteck jh057n00900 5.5" MIPI-DSI panel driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) Purism SPC 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <video/display_timing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/media-bus-format.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Manufacturer specific Commands send via DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define XPP055C272_CMD_ALL_PIXEL_OFF	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define XPP055C272_CMD_ALL_PIXEL_ON	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define XPP055C272_CMD_SETDISP		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define XPP055C272_CMD_SETRGBIF		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XPP055C272_CMD_SETCYC		0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XPP055C272_CMD_SETBGP		0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define XPP055C272_CMD_SETVCOM		0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XPP055C272_CMD_SETOTP		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XPP055C272_CMD_SETPOWER_EXT	0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XPP055C272_CMD_SETEXTC		0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XPP055C272_CMD_SETMIPI		0xbA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define XPP055C272_CMD_SETVDC		0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define XPP055C272_CMD_SETPCR		0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define XPP055C272_CMD_SETSCR		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define XPP055C272_CMD_SETPOWER		0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define XPP055C272_CMD_SETECO		0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define XPP055C272_CMD_SETPANEL		0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define XPP055C272_CMD_SETGAMMA		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define XPP055C272_CMD_SETEQ		0xe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define XPP055C272_CMD_SETGIP1		0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define XPP055C272_CMD_SETGIP2		0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct xpp055c272 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct regulator *vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct regulator *iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return container_of(panel, struct xpp055c272, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		static const u8 b[] = { cmd, seq };			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		int ret;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		if (ret < 0)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			return ret;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int xpp055c272_init_sequence(struct xpp055c272 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * Init sequence was supplied by the panel vendor without much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETMIPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			      0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			      0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			      0x00, 0x00, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETRGBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			      0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			      0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			      0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			      0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			      0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			      0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			      0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			      0x67, 0x77, 0x33, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			      0xff, 0x01, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			      0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			      0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			      0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			      0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			      0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			      0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			      0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			      0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			      0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			      0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			      0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			      0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			      0xa0, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGAMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			      0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			      0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			      0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			      0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			      0x11, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	dev_dbg(dev, "Panel init sequence done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int xpp055c272_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		dev_err(ctx->dev, "failed to set display off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	regulator_disable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	regulator_disable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int xpp055c272_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dev_dbg(ctx->dev, "Resetting the panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = regulator_enable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dev_err(ctx->dev, "Failed to enable vci supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ret = regulator_enable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		goto disable_vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* T6: 10us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* T8: 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = xpp055c272_init_sequence(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* T9: 120ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(ctx->dev, "Failed to set display on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) disable_iovcc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	regulator_disable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) disable_vci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	regulator_disable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct drm_display_mode default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.hdisplay	= 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.hsync_start	= 720 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.hsync_end	= 720 + 40 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.htotal		= 720 + 40 + 10 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.vdisplay	= 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.vsync_start	= 1280 + 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.vsync_end	= 1280 + 22 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.vtotal		= 1280 + 22 + 4 + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.clock		= 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.width_mm	= 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.height_mm	= 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int xpp055c272_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mode = drm_mode_duplicate(connector->dev, &default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			default_mode.hdisplay, default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			drm_mode_vrefresh(&default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct drm_panel_funcs xpp055c272_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.unprepare	= xpp055c272_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.prepare	= xpp055c272_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.get_modes	= xpp055c272_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int xpp055c272_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct xpp055c272 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(dev, "cannot get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ctx->vci = devm_regulator_get(dev, "vci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (IS_ERR(ctx->vci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = PTR_ERR(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			dev_err(dev, "Failed to request vci regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ctx->iovcc = devm_regulator_get(dev, "iovcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (IS_ERR(ctx->iovcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		ret = PTR_ERR(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			dev_err(dev, "Failed to request iovcc regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			  MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	drm_panel_init(&ctx->panel, &dsi->dev, &xpp055c272_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		       DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		dev_err(dev, "mipi_dsi_attach failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void xpp055c272_shutdown(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ret = drm_panel_unprepare(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = drm_panel_disable(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int xpp055c272_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	xpp055c272_shutdown(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret = mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct of_device_id xpp055c272_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ .compatible = "xinpeng,xpp055c272" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DEVICE_TABLE(of, xpp055c272_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct mipi_dsi_driver xpp055c272_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.name = "panel-xinpeng-xpp055c272",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.of_match_table = xpp055c272_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.probe	= xpp055c272_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.remove = xpp055c272_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.shutdown = xpp055c272_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) module_mipi_dsi_driver(xpp055c272_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_DESCRIPTION("DRM driver for Xinpeng xpp055c272 MIPI DSI panel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_LICENSE("GPL v2");