Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct visionox_rm69299 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct regulator_bulk_data supplies[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return container_of(panel, struct visionox_rm69299, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	 * Reset sequence of visionox panel requires the panel to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 * out of reset for 10ms, followed by being held in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 * for 10ms and then out again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int visionox_rm69299_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ctx->dsi->mode_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		dev_err(ctx->panel.dev, "set_display_off cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* 120ms delay required here as per DCS spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		dev_err(ctx->panel.dev, "enter_sleep cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ret = visionox_rm69299_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int visionox_rm69299_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ret = visionox_rm69299_power_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xfe, 0x00 }, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		dev_err(ctx->panel.dev, "cmd set tx 0 failed, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xc2, 0x08 }, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_err(ctx->panel.dev, "cmd set tx 1 failed, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x35, 0x00 }, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dev_err(ctx->panel.dev, "cmd set tx 2 failed, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x51, 0xff }, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		dev_err(ctx->panel.dev, "cmd set tx 3 failed, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		dev_err(ctx->panel.dev, "exit_sleep_mode cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Per DSI spec wait 120ms after sending exit sleep DCS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		dev_err(ctx->panel.dev, "set_display_on cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* Per DSI spec wait 120ms after sending set_display_on DCS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct drm_display_mode visionox_rm69299_1080x2248_60hz = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.name = "1080x2248",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.clock = 158695,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.hdisplay = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.hsync_start = 1080 + 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.hsync_end = 1080 + 26 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.htotal = 1080 + 26 + 2 + 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.vdisplay = 2248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.vsync_start = 2248 + 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.vsync_end = 2248 + 56 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.vtotal = 2248 + 56 + 4 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int visionox_rm69299_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				      struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	mode = drm_mode_create(connector->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		dev_err(ctx->panel.dev, "failed to create a new display mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	connector->display_info.width_mm = 74;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	connector->display_info.height_mm = 131;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	drm_mode_copy(mode, &visionox_rm69299_1080x2248_60hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct drm_panel_funcs visionox_rm69299_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.unprepare = visionox_rm69299_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.prepare = visionox_rm69299_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.get_modes = visionox_rm69299_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int visionox_rm69299_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct visionox_rm69299 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ctx->panel.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ctx->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ctx->supplies[0].supply = "vdda";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ctx->supplies[1].supply = "vdd3p3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				      ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 					 "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(dev, "cannot get reset gpio %ld\n", PTR_ERR(ctx->reset_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	drm_panel_init(&ctx->panel, dev, &visionox_rm69299_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		       DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ctx->panel.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ctx->panel.funcs = &visionox_rm69299_drm_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			  MIPI_DSI_CLOCK_NON_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_err(dev, "dsi attach failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = regulator_set_load(ctx->supplies[0].consumer, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(dev, "regulator set load failed for vdda supply ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		goto err_set_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		dev_err(dev, "regulator set load failed for vdd3p3 supply ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto err_set_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err_set_load:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int visionox_rm69299_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct visionox_rm69299 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	mipi_dsi_detach(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	mipi_dsi_device_unregister(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id visionox_rm69299_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	{ .compatible = "visionox,rm69299-1080p-display", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_DEVICE_TABLE(of, visionox_rm69299_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct mipi_dsi_driver visionox_rm69299_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.name = "panel-visionox-rm69299",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.of_match_table = visionox_rm69299_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.probe = visionox_rm69299_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.remove = visionox_rm69299_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_mipi_dsi_driver(visionox_rm69299_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DESCRIPTION("Visionox RM69299 DSI Panel Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_LICENSE("GPL v2");