^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const char * const regulator_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "vdispp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "vdispn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static unsigned long const regulator_enable_loads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 62000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static unsigned long const regulator_disable_loads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct cmd_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 commands[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct nt35597_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const char *panel_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct cmd_set *panel_on_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 num_on_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const struct drm_display_mode *dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct truly_nt35597 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct gpio_desc *mode_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct backlight_device *backlight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mipi_dsi_device *dsi[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct nt35597_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct truly_nt35597 *panel_to_ctx(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return container_of(panel, struct truly_nt35597, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct cmd_set qcom_2k_panel_magic_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* CMD2_P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { { 0xff, 0x20 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { { 0xfb, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { { 0x00, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { { 0x01, 0x55 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { { 0x02, 0x45 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { { 0x05, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { { 0x06, 0x19 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { { 0x07, 0x1e }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { { 0x0b, 0x73 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { { 0x0c, 0x73 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { { 0x0e, 0xb0 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { { 0x0f, 0xae }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { { 0x11, 0xb8 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { { 0x13, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { { 0x58, 0x80 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { { 0x59, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { { 0x5a, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { { 0x5b, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { { 0x5c, 0x80 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { { 0x5d, 0x81 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { { 0x5e, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { { 0x5f, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { { 0x72, 0x11 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { { 0x68, 0x03 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* CMD2_P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { { 0xFF, 0x24 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { { 0xFB, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { { 0x00, 0x1C }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { { 0x01, 0x0B }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { { 0x02, 0x0C }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { { 0x03, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { { 0x04, 0x0F }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { { 0x05, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { { 0x06, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { { 0x07, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { { 0x08, 0x89 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { { 0x09, 0x8A }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { { 0x0A, 0x13 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { { 0x0B, 0x13 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { { 0x0C, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { { 0x0D, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { { 0x0E, 0x17 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { { 0x0F, 0x17 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { { 0x10, 0x1C }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { { 0x11, 0x0B }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { { 0x12, 0x0C }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { { 0x13, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { { 0x14, 0x0F }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { { 0x15, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { { 0x16, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { { 0x17, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { { 0x18, 0x89 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { { 0x19, 0x8A }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { { 0x1A, 0x13 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { { 0x1B, 0x13 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { { 0x1C, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { { 0x1D, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { { 0x1E, 0x17 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { { 0x1F, 0x17 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* STV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { { 0x20, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { { 0x21, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { { 0x22, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { { 0x23, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { { 0x24, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { { 0x25, 0x6D }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { { 0x26, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { { 0x27, 0x40 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Vend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { { 0xE0, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { { 0xDC, 0x21 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { { 0xDD, 0x22 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { { 0xDE, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { { 0xDF, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { { 0xE3, 0x6D }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { { 0xE1, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { { 0xE2, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { { 0x29, 0xD8 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { { 0x2A, 0x2A }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { { 0x4B, 0x03 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { { 0x4C, 0x11 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { { 0x4D, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { { 0x4E, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { { 0x4F, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { { 0x50, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { { 0x51, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { { 0x52, 0x80 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { { 0x53, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { { 0x56, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { { 0x54, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { { 0x58, 0x07 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { { 0x55, 0x25 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Reset XDONB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { { 0x5B, 0x43 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { { 0x5C, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { { 0x5F, 0x73 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { { 0x60, 0x73 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { { 0x63, 0x22 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { { 0x64, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { { 0x67, 0x08 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { { 0x68, 0x04 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Resolution:1440x2560 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { { 0x72, 0x02 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { { 0x7A, 0x80 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { { 0x7B, 0x91 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { { 0x7C, 0xD8 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { { 0x7D, 0x60 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { { 0x7F, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { { 0x75, 0x15 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* ABOFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { { 0xB3, 0xC0 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { { 0xB4, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { { 0xB5, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Source EQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { { 0x78, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { { 0x79, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { { 0x80, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { { 0x83, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* FP BP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { { 0x93, 0x0A }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { { 0x94, 0x0A }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Inversion Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { { 0x8A, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { { 0x9B, 0xFF }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* IMGSWAP =1 @PortSwap=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { { 0x9D, 0xB0 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { { 0x9F, 0x63 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { { 0x98, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* FRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { { 0xEC, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* CMD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { { 0xFF, 0x10 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* VBP+VSA=,VFP = 10H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { { 0x3B, 0x03, 0x0A, 0x0A }, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* FTE on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { { 0x35, 0x00 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* EN_BK =1(auto black) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { { 0xE5, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* CMD mode(10) VDO mode(03) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { { 0xBB, 0x03 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Non Reload MTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { { 0xFB, 0x01 }, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int truly_dcs_write(struct drm_panel *panel, u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = mipi_dsi_dcs_write(ctx->dsi[i], command, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(ctx->dev, "cmd 0x%x failed for dsi = %d\n", command, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int truly_dcs_write_buf(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 size, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = mipi_dsi_dcs_write_buffer(ctx->dsi[i], buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(ctx->dev, "failed to tx cmd [%d], err: %d\n", i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int truly_35597_power_on(struct truly_nt35597 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = regulator_set_load(ctx->supplies[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regulator_enable_loads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Reset sequence of truly panel requires the panel to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * out of reset for 10ms, followed by being held in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * for 10ms and then out again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int truly_nt35597_power_off(struct truly_nt35597 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = regulator_set_load(ctx->supplies[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regulator_disable_loads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(ctx->dev, "regulator_set_load failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(ctx->dev, "regulator_bulk_disable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int truly_nt35597_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!ctx->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ctx->backlight) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = backlight_disable(ctx->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(ctx->dev, "backlight disable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctx->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int truly_nt35597_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ctx->dsi[0]->mode_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ctx->dsi[1]->mode_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = truly_dcs_write(panel, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(ctx->dev, "set_display_off cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* 120ms delay required here as per DCS spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = truly_dcs_write(panel, MIPI_DCS_ENTER_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(ctx->dev, "enter_sleep cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = truly_nt35597_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(ctx->dev, "power_off failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int truly_nt35597_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const struct cmd_set *panel_on_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const struct nt35597_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 num_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = truly_35597_power_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ctx->dsi[0]->mode_flags |= MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ctx->dsi[1]->mode_flags |= MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) config = ctx->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) panel_on_cmds = config->panel_on_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) num_cmds = config->num_on_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (i = 0; i < num_cmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = truly_dcs_write_buf(panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) panel_on_cmds[i].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) panel_on_cmds[i].commands);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(ctx->dev, "cmd set tx failed i = %d ret = %d\n", i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = truly_dcs_write(panel, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(ctx->dev, "exit_sleep_mode cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Per DSI spec wait 120ms after sending exit sleep DCS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = truly_dcs_write(panel, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_err(ctx->dev, "set_display_on cmd failed ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Per DSI spec wait 120ms after sending set_display_on DCS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (truly_nt35597_power_off(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(ctx->dev, "power_off failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int truly_nt35597_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ctx->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ctx->backlight) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = backlight_enable(ctx->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(ctx->dev, "backlight enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ctx->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int truly_nt35597_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct truly_nt35597 *ctx = panel_to_ctx(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct nt35597_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) config = ctx->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mode = drm_mode_create(connector->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(ctx->dev, "failed to create a new display mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) connector->display_info.width_mm = config->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) connector->display_info.height_mm = config->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) drm_mode_copy(mode, config->dm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct drm_panel_funcs truly_nt35597_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .disable = truly_nt35597_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .unprepare = truly_nt35597_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .prepare = truly_nt35597_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .enable = truly_nt35597_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .get_modes = truly_nt35597_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int truly_nt35597_panel_add(struct truly_nt35597 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ctx->supplies[i].supply = regulator_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(dev, "cannot get reset gpio %ld\n", PTR_ERR(ctx->reset_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ctx->mode_gpio = devm_gpiod_get(dev, "mode", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (IS_ERR(ctx->mode_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "cannot get mode gpio %ld\n", PTR_ERR(ctx->mode_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return PTR_ERR(ctx->mode_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* dual port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) gpiod_set_value(ctx->mode_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) drm_panel_init(&ctx->panel, dev, &truly_nt35597_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct drm_display_mode qcom_sdm845_mtp_2k_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "1440x2560",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .clock = 268316,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .hdisplay = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .hsync_start = 1440 + 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hsync_end = 1440 + 200 + 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .htotal = 1440 + 200 + 32 + 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .vdisplay = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .vsync_start = 2560 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .vsync_end = 2560 + 8 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .vtotal = 2560 + 8 + 1 + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct nt35597_config nt35597_dir = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .width_mm = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .height_mm = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .panel_name = "qcom_sdm845_mtp_2k_panel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .dm = &qcom_sdm845_mtp_2k_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .panel_on_cmds = qcom_2k_panel_magic_cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .num_on_cmds = ARRAY_SIZE(qcom_2k_panel_magic_cmds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int truly_nt35597_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct truly_nt35597 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct mipi_dsi_device *dsi1_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct device_node *dsi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct mipi_dsi_host *dsi1_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct mipi_dsi_device *dsi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct mipi_dsi_device_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .type = "trulynt35597",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .node = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * This device represents itself as one with two input ports which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * fed by the output ports of the two DSI controllers . The DSI0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * the master controller and has most of the panel related info in its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * child node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ctx->config = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!ctx->config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev, "missing device configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dsi1 = of_graph_get_remote_node(dsi->dev.of_node, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!dsi1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(dev, "failed to get remote node for dsi1_device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dsi1_host = of_find_mipi_dsi_host_by_node(dsi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) of_node_put(dsi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!dsi1_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(dev, "failed to find dsi host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* register the second DSI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dsi1_device = mipi_dsi_device_register_full(dsi1_host, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (IS_ERR(dsi1_device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(dev, "failed to create dsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return PTR_ERR(dsi1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ctx->dsi[0] = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ctx->dsi[1] = dsi1_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = truly_nt35597_panel_add(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(dev, "failed to add panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) goto err_panel_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dsi_dev = ctx->dsi[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dsi_dev->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dsi_dev->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dsi_dev->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MIPI_DSI_CLOCK_NON_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = mipi_dsi_attach(dsi_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dev, "dsi attach failed i = %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) err_panel_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mipi_dsi_device_unregister(dsi1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int truly_nt35597_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct truly_nt35597 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ctx->dsi[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mipi_dsi_detach(ctx->dsi[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ctx->dsi[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mipi_dsi_detach(ctx->dsi[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mipi_dsi_device_unregister(ctx->dsi[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const struct of_device_id truly_nt35597_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .compatible = "truly,nt35597-2K-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .data = &nt35597_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MODULE_DEVICE_TABLE(of, truly_nt35597_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct mipi_dsi_driver truly_nt35597_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "panel-truly-nt35597",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .of_match_table = truly_nt35597_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .probe = truly_nt35597_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .remove = truly_nt35597_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) module_mipi_dsi_driver(truly_nt35597_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_DESCRIPTION("Truly NT35597 DSI Panel Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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