^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Panel driver for the TPO TPG110 400CH LTPS TFT LCD Single Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Digital Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This chip drives a TFT LCD, so it does not know what kind of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * display is actually connected to it, so the width and height of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * display needs to be supplied from the machine configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TPG110_TEST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TPG110_CHIPID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TPG110_CTRL1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TPG110_RES_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TPG110_RES_800X480 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TPG110_RES_640X480 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TPG110_RES_480X272 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TPG110_RES_480X640 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TPG110_RES_480X272_D 0x01 /* Dual scan: outputs 800x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TPG110_RES_400X240_D 0x00 /* Dual scan: outputs 800x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TPG110_CTRL2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TPG110_CTRL2_PM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TPG110_CTRL2_RES_PM_CTRL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * struct tpg110_panel_mode - lookup struct for the supported modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tpg110_panel_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @name: the name of this panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @magic: the magic value from the detection register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @mode: the DRM display mode for this panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @bus_flags: the DRM bus flags for this panel e.g. inverted clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * struct tpg110 - state container for the TPG110 panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tpg110 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @dev: the container device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @spi: the corresponding SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @panel: the DRM panel instance for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @panel_type: the panel mode as detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const struct tpg110_panel_mode *panel_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @width: the width of this panel in mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @height: the height of this panel in mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @grestb: reset GPIO line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct gpio_desc *grestb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * TPG110 modes, these are the simple modes, the dualscan modes that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * take 400x240 or 480x272 in and display as 800x480 are not listed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct tpg110_panel_mode tpg110_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "800x480 RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .magic = TPG110_RES_800X480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .clock = 33200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .hdisplay = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .hsync_start = 800 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .hsync_end = 800 + 40 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .htotal = 800 + 40 + 1 + 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .vdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .vsync_start = 480 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .vsync_end = 480 + 10 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .vtotal = 480 + 10 + 1 + 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "640x480 RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .magic = TPG110_RES_640X480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .clock = 25200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .hdisplay = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .hsync_start = 640 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hsync_end = 640 + 24 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .htotal = 640 + 24 + 1 + 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .vdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .vsync_start = 480 + 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .vsync_end = 480 + 18 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .vtotal = 480 + 18 + 1 + 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "480x272 RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .magic = TPG110_RES_480X272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .clock = 9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .hdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .hsync_start = 480 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .hsync_end = 480 + 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .htotal = 480 + 2 + 1 + 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .vdisplay = 272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .vsync_start = 272 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .vsync_end = 272 + 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .vtotal = 272 + 2 + 1 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "480x640 RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .magic = TPG110_RES_480X640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .clock = 20500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .hsync_start = 480 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hsync_end = 480 + 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .htotal = 480 + 2 + 1 + 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .vdisplay = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .vsync_start = 640 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .vsync_end = 640 + 4 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .vtotal = 640 + 4 + 1 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "400x240 RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .magic = TPG110_RES_400X240_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .clock = 8300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .hdisplay = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .hsync_start = 400 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .hsync_end = 400 + 20 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .htotal = 400 + 20 + 1 + 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .vdisplay = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .vsync_start = 240 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .vsync_end = 240 + 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .vtotal = 240 + 2 + 1 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline struct tpg110 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) to_tpg110(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return container_of(panel, struct tpg110, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static u8 tpg110_readwrite_reg(struct tpg110 *tpg, bool write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 address, u8 outval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Clear address bit 0, 1 when writing, just to be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * The actual bit indicating a write here is bit 1, bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 0 is just surplus to pad it up to 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) buf[0] = address << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) buf[0] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) buf[1] = outval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) t[0].bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) t[0].tx_buf = &buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) t[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) t[1].tx_buf = &buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) t[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) t[1].bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Set address bit 0 to 1 to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) buf[0] = address << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) buf[0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * The last bit/clock is Hi-Z turnaround cycle, so we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * to send only 7 bits here. The 8th bit is the high impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * turn-around cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) t[0].bits_per_word = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) t[0].tx_buf = &buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) t[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) t[1].rx_buf = &buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) t[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) t[1].bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = spi_sync(tpg->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(tpg->dev, "SPI message error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static u8 tpg110_read_reg(struct tpg110 *tpg, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return tpg110_readwrite_reg(tpg, false, address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void tpg110_write_reg(struct tpg110 *tpg, u8 address, u8 outval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tpg110_readwrite_reg(tpg, true, address, outval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int tpg110_startup(struct tpg110 *tpg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* De-assert the reset signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) gpiod_set_value_cansleep(tpg->grestb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(tpg->dev, "de-asserted GRESTB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Test display communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tpg110_write_reg(tpg, TPG110_TEST, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val = tpg110_read_reg(tpg, TPG110_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (val != 0x55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(tpg->dev, "failed communication test\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val = tpg110_read_reg(tpg, TPG110_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_info(tpg->dev, "TPG110 chip ID: %d version: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val >> 4, val & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Show display resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val = tpg110_read_reg(tpg, TPG110_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val &= TPG110_RES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case TPG110_RES_400X240_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_info(tpg->dev, "IN 400x240 RGB -> OUT 800x480 RGB (dual scan)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case TPG110_RES_480X272_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_info(tpg->dev, "IN 480x272 RGB -> OUT 800x480 RGB (dual scan)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case TPG110_RES_480X640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_info(tpg->dev, "480x640 RGB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case TPG110_RES_480X272:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_info(tpg->dev, "480x272 RGB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case TPG110_RES_640X480:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_info(tpg->dev, "640x480 RGB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case TPG110_RES_800X480:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_info(tpg->dev, "800x480 RGB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(tpg->dev, "ILLEGAL RESOLUTION 0x%02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* From the producer side, this is the same resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (val == TPG110_RES_480X272_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val = TPG110_RES_480X272;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; i < ARRAY_SIZE(tpg110_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const struct tpg110_panel_mode *pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pm = &tpg110_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (pm->magic == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tpg->panel_mode = pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (i == ARRAY_SIZE(tpg110_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(tpg->dev, "unsupported mode (%02x) detected\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = tpg110_read_reg(tpg, TPG110_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_info(tpg->dev, "resolution and standby is controlled by %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (val & TPG110_CTRL2_RES_PM_CTRL) ? "software" : "hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Take control over resolution and standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val |= TPG110_CTRL2_RES_PM_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tpg110_write_reg(tpg, TPG110_CTRL2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int tpg110_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct tpg110 *tpg = to_tpg110(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Put chip into standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val &= ~TPG110_CTRL2_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int tpg110_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct tpg110 *tpg = to_tpg110(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Take chip out of standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val |= TPG110_CTRL2_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * tpg110_get_modes() - return the appropriate mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @panel: the panel to get the mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * This currently does not present a forest of modes, instead it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * presents the mode that is configured for the system under use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * and which is detected by reading the registers of the display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int tpg110_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct tpg110 *tpg = to_tpg110(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) connector->display_info.width_mm = tpg->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) connector->display_info.height_mm = tpg->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) connector->display_info.bus_flags = tpg->panel_mode->bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mode = drm_mode_duplicate(connector->dev, &tpg->panel_mode->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mode->width_mm = tpg->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mode->height_mm = tpg->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct drm_panel_funcs tpg110_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .disable = tpg110_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .enable = tpg110_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .get_modes = tpg110_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int tpg110_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct tpg110 *tpg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tpg = devm_kzalloc(dev, sizeof(*tpg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!tpg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tpg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* We get the physical display dimensions from the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = of_property_read_u32(np, "width-mm", &tpg->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(dev, "no panel width specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = of_property_read_u32(np, "height-mm", &tpg->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(dev, "no panel height specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* This asserts the GRESTB signal, putting the display into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tpg->grestb = devm_gpiod_get(dev, "grestb", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (IS_ERR(tpg->grestb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(dev, "no GRESTB GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spi->mode |= SPI_3WIRE_HIZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(dev, "spi setup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tpg->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = tpg110_startup(tpg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) drm_panel_init(&tpg->panel, dev, &tpg110_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = drm_panel_of_backlight(&tpg->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spi_set_drvdata(spi, tpg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) drm_panel_add(&tpg->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int tpg110_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct tpg110 *tpg = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) drm_panel_remove(&tpg->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct of_device_id tpg110_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { .compatible = "tpo,tpg110", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DEVICE_TABLE(of, tpg110_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct spi_driver tpg110_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .probe = tpg110_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .remove = tpg110_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "tpo-tpg110-panel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .of_match_table = tpg110_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) module_spi_driver(tpg110_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_DESCRIPTION("TPO TPG110 panel driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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