Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Toppoly TD028TTEC1 Panel Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on the omapdrm-specific panel-tpo-td028ttec1 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Neo 1973 code (jbt6k74.c):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2006-2007 OpenMoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Author: Harald Welte <laforge@openmoko.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Ported and adapted from Neo 1973 U-Boot by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * H. Nikolaus Schaller <hns@goldelico.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define JBT_COMMAND			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define JBT_DATA			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define JBT_REG_SLEEP_IN		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define JBT_REG_SLEEP_OUT		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define JBT_REG_DISPLAY_OFF		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define JBT_REG_DISPLAY_ON		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define JBT_REG_RGB_FORMAT		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define JBT_REG_QUAD_RATE		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define JBT_REG_POWER_ON_OFF		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define JBT_REG_BOOSTER_OP		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define JBT_REG_BOOSTER_MODE		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define JBT_REG_BOOSTER_FREQ		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define JBT_REG_OPAMP_SYSCLK		0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define JBT_REG_VSC_VOLTAGE		0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define JBT_REG_VCOM_VOLTAGE		0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define JBT_REG_EXT_DISPL		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define JBT_REG_OUTPUT_CONTROL		0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define JBT_REG_DCCLK_DCEV		0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define JBT_REG_DISPLAY_MODE1		0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define JBT_REG_DISPLAY_MODE2		0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define JBT_REG_DISPLAY_MODE		0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define JBT_REG_ASW_SLEW		0xbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define JBT_REG_DUMMY_DISPLAY		0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define JBT_REG_DRIVE_SYSTEM		0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define JBT_REG_SLEEP_OUT_FR_A		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define JBT_REG_SLEEP_OUT_FR_B		0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define JBT_REG_SLEEP_OUT_FR_C		0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define JBT_REG_SLEEP_IN_LCCNT_D	0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define JBT_REG_SLEEP_IN_LCCNT_E	0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define JBT_REG_SLEEP_IN_LCCNT_F	0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define JBT_REG_SLEEP_IN_LCCNT_G	0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define JBT_REG_GAMMA1_FINE_1		0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define JBT_REG_GAMMA1_FINE_2		0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define JBT_REG_GAMMA1_INCLINATION	0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define JBT_REG_GAMMA1_BLUE_OFFSET	0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define JBT_REG_BLANK_CONTROL		0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define JBT_REG_BLANK_TH_TV		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define JBT_REG_CKV_ON_OFF		0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define JBT_REG_CKV_1_2			0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define JBT_REG_OEV_TIMING		0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define JBT_REG_ASW_TIMING_1		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define JBT_REG_ASW_TIMING_2		0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define JBT_REG_HCLOCK_VGA		0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define JBT_REG_HCLOCK_QVGA		0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct td028ttec1_panel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * noinline_for_stack so we don't get multiple copies of tx_buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * on the stack in case of gcc-plugin-structleak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int noinline_for_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct spi_device *spi = lcd->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u16 tx_buf = JBT_COMMAND | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (err && *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			*err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int noinline_for_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) jbt_reg_write_1(struct td028ttec1_panel *lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		u8 reg, u8 data, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct spi_device *spi = lcd->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u16 tx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (err && *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	tx_buf[0] = JBT_COMMAND | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tx_buf[1] = JBT_DATA | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			*err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int noinline_for_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) jbt_reg_write_2(struct td028ttec1_panel *lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		u8 reg, u16 data, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct spi_device *spi = lcd->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u16 tx_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (err && *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	tx_buf[0] = JBT_COMMAND | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	tx_buf[1] = JBT_DATA | (data >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tx_buf[2] = JBT_DATA | (data & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			*err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int td028ttec1_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Three times command zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		jbt_ret_write_0(lcd, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* deep standby out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Quad mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* AVDD on, XVDD on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Sleep mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* at this point we have like 50% grey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* initialize register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * to avoid red / blue flicker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int td028ttec1_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	ret = jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int td028ttec1_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int td028ttec1_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct drm_display_mode td028ttec1_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.clock = 22153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.hdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.hsync_start = 480 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.hsync_end = 480 + 24 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.htotal = 480 + 24 + 8 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.vdisplay = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.vsync_start = 640 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.vsync_end = 640 + 4 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.vtotal = 640 + 4 + 2 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.width_mm = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.height_mm = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int td028ttec1_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	connector->display_info.width_mm = td028ttec1_mode.width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	connector->display_info.height_mm = td028ttec1_mode.height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * FIXME: According to the datasheet sync signals are sampled on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * rising edge of the clock, but the code running on the OpenMoko Neo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 * FreeRunner and Neo 1973 indicates sampling on the falling edge. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 * should be tested on a real device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 					  | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 					  | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct drm_panel_funcs td028ttec1_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.prepare = td028ttec1_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.enable = td028ttec1_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.disable = td028ttec1_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.unprepare = td028ttec1_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.get_modes = td028ttec1_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int td028ttec1_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct td028ttec1_panel *lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	spi_set_drvdata(spi, lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	lcd->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	spi->mode = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	spi->bits_per_word = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	drm_panel_init(&lcd->panel, &lcd->spi->dev, &td028ttec1_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		       DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ret = drm_panel_of_backlight(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	drm_panel_add(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int td028ttec1_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	drm_panel_remove(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	drm_panel_disable(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	drm_panel_unprepare(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct of_device_id td028ttec1_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	{ .compatible = "tpo,td028ttec1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/* DT backward compatibility. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{ .compatible = "toppoly,td028ttec1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct spi_device_id td028ttec1_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{ "td028ttec1", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct spi_driver td028ttec1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.probe		= td028ttec1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.remove		= td028ttec1_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.id_table	= td028ttec1_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.name   = "panel-tpo-td028ttec1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.of_match_table = td028ttec1_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) module_spi_driver(td028ttec1_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_LICENSE("GPL");