Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ST7789V_COLMOD_RGB_FMT_18BITS		(6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ST7789V_COLMOD_CTRL_FMT_18BITS		(6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ST7789V_RAMCTRL_CMD		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ST7789V_RAMCTRL_RM_RGB			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ST7789V_RAMCTRL_DM_RGB			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ST7789V_RAMCTRL_MAGIC			(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ST7789V_RAMCTRL_EPF(n)			(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ST7789V_RGBCTRL_CMD		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ST7789V_RGBCTRL_WO			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ST7789V_RGBCTRL_RCM(n)			(((n) & 3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ST7789V_RGBCTRL_VSYNC_HIGH		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ST7789V_RGBCTRL_HSYNC_HIGH		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ST7789V_RGBCTRL_PCLK_HIGH		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ST7789V_RGBCTRL_VBP(n)			((n) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ST7789V_RGBCTRL_HBP(n)			((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ST7789V_PORCTRL_CMD		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ST7789V_PORCTRL_IDLE_BP(n)		(((n) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ST7789V_PORCTRL_IDLE_FP(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ST7789V_PORCTRL_PARTIAL_BP(n)		(((n) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ST7789V_PORCTRL_PARTIAL_FP(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ST7789V_GCTRL_CMD		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ST7789V_GCTRL_VGHS(n)			(((n) & 7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ST7789V_GCTRL_VGLS(n)			((n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ST7789V_VCOMS_CMD		0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ST7789V_LCMCTRL_CMD		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ST7789V_LCMCTRL_XBGR			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ST7789V_LCMCTRL_XMX			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ST7789V_LCMCTRL_XMH			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ST7789V_VDVVRHEN_CMD		0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ST7789V_VDVVRHEN_CMDEN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ST7789V_VRHS_CMD		0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ST7789V_VDVS_CMD		0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ST7789V_FRCTRL2_CMD		0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ST7789V_PWCTRL1_CMD		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ST7789V_PWCTRL1_MAGIC			0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ST7789V_PWCTRL1_AVDD(n)			(((n) & 3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ST7789V_PWCTRL1_AVCL(n)			(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ST7789V_PWCTRL1_VDS(n)			((n) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ST7789V_PVGAMCTRL_CMD		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ST7789V_PVGAMCTRL_JP0(n)		(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ST7789V_PVGAMCTRL_JP1(n)		(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ST7789V_PVGAMCTRL_VP0(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ST7789V_PVGAMCTRL_VP1(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ST7789V_PVGAMCTRL_VP2(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ST7789V_PVGAMCTRL_VP4(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ST7789V_PVGAMCTRL_VP6(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ST7789V_PVGAMCTRL_VP13(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ST7789V_PVGAMCTRL_VP20(n)		((n) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ST7789V_PVGAMCTRL_VP27(n)		((n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ST7789V_PVGAMCTRL_VP36(n)		(((n) & 7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define ST7789V_PVGAMCTRL_VP43(n)		((n) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ST7789V_PVGAMCTRL_VP50(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ST7789V_PVGAMCTRL_VP57(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define ST7789V_PVGAMCTRL_VP59(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ST7789V_PVGAMCTRL_VP61(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ST7789V_PVGAMCTRL_VP62(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ST7789V_PVGAMCTRL_VP63(n)		(((n) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define ST7789V_NVGAMCTRL_CMD		0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ST7789V_NVGAMCTRL_JN0(n)		(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ST7789V_NVGAMCTRL_JN1(n)		(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ST7789V_NVGAMCTRL_VN0(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ST7789V_NVGAMCTRL_VN1(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ST7789V_NVGAMCTRL_VN2(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ST7789V_NVGAMCTRL_VN4(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ST7789V_NVGAMCTRL_VN6(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ST7789V_NVGAMCTRL_VN13(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ST7789V_NVGAMCTRL_VN20(n)		((n) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ST7789V_NVGAMCTRL_VN27(n)		((n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ST7789V_NVGAMCTRL_VN36(n)		(((n) & 7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ST7789V_NVGAMCTRL_VN43(n)		((n) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ST7789V_NVGAMCTRL_VN50(n)		((n) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ST7789V_NVGAMCTRL_VN57(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ST7789V_NVGAMCTRL_VN59(n)		((n) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ST7789V_NVGAMCTRL_VN61(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ST7789V_NVGAMCTRL_VN62(n)		((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ST7789V_NVGAMCTRL_VN63(n)		(((n) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ST7789V_TEST(val, func)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	do {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		if ((val = (func)))		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			return val;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct st7789v {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct regulator *power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum st7789v_prefix {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ST7789V_COMMAND = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ST7789V_DATA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline struct st7789v *panel_to_st7789v(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return container_of(panel, struct st7789v, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int st7789v_spi_write(struct st7789v *ctx, enum st7789v_prefix prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			     u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct spi_transfer xfer = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u16 txbuf = ((prefix & 1) << 8) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	xfer.tx_buf = &txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	xfer.bits_per_word = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	xfer.len = sizeof(txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spi_message_add_tail(&xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return spi_sync(ctx->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int st7789v_write_command(struct st7789v *ctx, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return st7789v_spi_write(ctx, ST7789V_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int st7789v_write_data(struct st7789v *ctx, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return st7789v_spi_write(ctx, ST7789V_DATA, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct drm_display_mode default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.clock = 7000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.hdisplay = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.hsync_start = 240 + 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.hsync_end = 240 + 38 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.htotal = 240 + 38 + 10 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.vdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.vsync_start = 320 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.vsync_end = 320 + 8 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.vtotal = 320 + 8 + 4 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int st7789v_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			     struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mode = drm_mode_duplicate(connector->dev, &default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_err(panel->dev, "failed to add mode %ux%ux@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			default_mode.hdisplay, default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			drm_mode_vrefresh(&default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	connector->display_info.width_mm = 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	connector->display_info.height_mm = 103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int st7789v_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct st7789v *ctx = panel_to_st7789v(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ret = regulator_enable(ctx->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	gpiod_set_value(ctx->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	gpiod_set_value(ctx->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_EXIT_SLEEP_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* We need to wait 120ms after a sleep out command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ST7789V_TEST(ret, st7789v_write_command(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 						MIPI_DCS_SET_ADDRESS_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ST7789V_TEST(ret, st7789v_write_command(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 						MIPI_DCS_SET_PIXEL_FORMAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ST7789V_TEST(ret, st7789v_write_data(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					     (MIPI_DCS_PIXEL_FMT_18BIT << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					     (MIPI_DCS_PIXEL_FMT_18BIT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PORCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0xc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0xc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PORCTRL_IDLE_BP(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					     ST7789V_PORCTRL_IDLE_FP(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ST7789V_TEST(ret, st7789v_write_data(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					     ST7789V_PORCTRL_PARTIAL_BP(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					     ST7789V_PORCTRL_PARTIAL_FP(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_GCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_GCTRL_VGLS(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					     ST7789V_GCTRL_VGHS(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VCOMS_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0x2b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_LCMCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_LCMCTRL_XMH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					     ST7789V_LCMCTRL_XMX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 					     ST7789V_LCMCTRL_XBGR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VDVVRHEN_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_VDVVRHEN_CMDEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VRHS_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VDVS_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_FRCTRL2_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ST7789V_TEST(ret, st7789v_write_data(ctx, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PWCTRL1_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PWCTRL1_MAGIC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PWCTRL1_AVDD(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					     ST7789V_PWCTRL1_AVCL(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 					     ST7789V_PWCTRL1_VDS(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PVGAMCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP63(0xd)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP1(0xca)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP2(0xe)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP4(8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP6(9)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP13(7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP20(0x2d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP27(0xb) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					     ST7789V_PVGAMCTRL_VP36(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP43(0x3d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_JP1(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 					     ST7789V_PVGAMCTRL_VP50(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP57(0xa)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP59(0xa)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP61(0x1b)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP62(0x28)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_NVGAMCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN63(0xd)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN1(0xca)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN2(0xf)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN4(8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN6(8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN13(7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN20(0x2e)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN27(0xc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 					     ST7789V_NVGAMCTRL_VN36(5)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN43(0x40)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_JN1(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					     ST7789V_NVGAMCTRL_VN50(4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN57(9)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN59(0xb)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN61(0x1b)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN62(0x28)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_ENTER_INVERT_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RAMCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RAMCTRL_DM_RGB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					     ST7789V_RAMCTRL_RM_RGB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RAMCTRL_EPF(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 					     ST7789V_RAMCTRL_MAGIC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RGBCTRL_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_WO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					     ST7789V_RGBCTRL_RCM(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					     ST7789V_RGBCTRL_VSYNC_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 					     ST7789V_RGBCTRL_HSYNC_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 					     ST7789V_RGBCTRL_PCLK_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_VBP(8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_HBP(20)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int st7789v_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct st7789v *ctx = panel_to_st7789v(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return st7789v_write_command(ctx, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int st7789v_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct st7789v *ctx = panel_to_st7789v(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_SET_DISPLAY_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int st7789v_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct st7789v *ctx = panel_to_st7789v(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_ENTER_SLEEP_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	regulator_disable(ctx->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct drm_panel_funcs st7789v_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.disable	= st7789v_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.enable		= st7789v_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.get_modes	= st7789v_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.prepare	= st7789v_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.unprepare	= st7789v_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int st7789v_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	struct st7789v *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ctx = devm_kzalloc(&spi->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	spi_set_drvdata(spi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ctx->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	drm_panel_init(&ctx->panel, &spi->dev, &st7789v_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		       DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ctx->power = devm_regulator_get(&spi->dev, "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (IS_ERR(ctx->power))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return PTR_ERR(ctx->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ctx->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (IS_ERR(ctx->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		dev_err(&spi->dev, "Couldn't get our reset line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return PTR_ERR(ctx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int st7789v_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	struct st7789v *ctx = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct of_device_id st7789v_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ .compatible = "sitronix,st7789v" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_DEVICE_TABLE(of, st7789v_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct spi_driver st7789v_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.probe = st7789v_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.remove = st7789v_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		.name = "st7789v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.of_match_table = st7789v_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) module_spi_driver(st7789v_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_DESCRIPTION("Sitronix st7789v LCD Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_LICENSE("GPL v2");