^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for panels based on Sitronix ST7703 controller, souch as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * - Rocktech jh057n00900 5.5" MIPI-DSI panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) Purism SPC 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/media-bus-format.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <video/display_timing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_NAME "panel-sitronix-st7703"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Manufacturer specific Commands send via DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ST7703_CMD_ALL_PIXEL_OFF 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ST7703_CMD_ALL_PIXEL_ON 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ST7703_CMD_SETDISP 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ST7703_CMD_SETRGBIF 0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ST7703_CMD_SETCYC 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ST7703_CMD_SETBGP 0xB5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ST7703_CMD_SETVCOM 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ST7703_CMD_SETOTP 0xB7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ST7703_CMD_SETPOWER_EXT 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ST7703_CMD_SETEXTC 0xB9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ST7703_CMD_SETMIPI 0xBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ST7703_CMD_SETVDC 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ST7703_CMD_UNKNOWN_BF 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ST7703_CMD_SETSCR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ST7703_CMD_SETPOWER 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ST7703_CMD_SETPANEL 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ST7703_CMD_UNKNOWN_C6 0xC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ST7703_CMD_SETGAMMA 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ST7703_CMD_SETEQ 0xE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ST7703_CMD_SETGIP1 0xE9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ST7703_CMD_SETGIP2 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct st7703 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct regulator *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct regulator *iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct st7703_panel_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct st7703_panel_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum mipi_dsi_pixel_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int (*init_sequence)(struct st7703 *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct st7703 *panel_to_st7703(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return container_of(panel, struct st7703, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define dsi_generic_write_seq(dsi, seq...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int jh057n_init_sequence(struct st7703 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Init sequence was supplied by the panel vendor. Most of the commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * resemble the ST7703 but the number of parameters often don't match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * so it's likely a clone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0xF1, 0x12, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0xA5, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x11, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct drm_display_mode jh057n00900_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .hdisplay = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .hsync_start = 720 + 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hsync_end = 720 + 90 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .htotal = 720 + 90 + 20 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .vdisplay = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .vsync_start = 1440 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .vsync_end = 1440 + 20 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .vtotal = 1440 + 20 + 4 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .clock = 75276,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .width_mm = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .height_mm = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct st7703_panel_desc jh057n00900_panel_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mode = &jh057n00900_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .mode_flags = MIPI_DSI_MODE_VIDEO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .init_sequence = jh057n_init_sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = mipi_dsi_dcs_write(dsi, cmd, d, ARRAY_SIZE(d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int xbd599_init_sequence(struct st7703 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Init sequence was supplied by the panel vendor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Magic sequence to unlock user commands below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x05, /* IHSRX = x6 (Low High Speed driving ability) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0xF9, /* TX_CLK_SEL = fDSICLK/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* The rest is undocumented in ST7703 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x4F, 0x11, 0x00, 0x00, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x22, /* DT = 15ms XDK_ECP = x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x20, /* PFM_DC_DIV = /1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* RGB I/F porch timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x10, /* VBP_RGB_GEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x10, /* VFP_RGB_GEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x05, /* DE_BP_RGB_GEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x05, /* DE_FP_RGB_GEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* The rest is undocumented in ST7703 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x03, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Source driving settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x73, /* N_POPON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x73, /* N_NOPON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0x50, /* I_POPON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x50, /* I_NOPON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x00, /* SCR[31,24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0xC0, /* SCR[23,16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0x08, /* SCR[15,8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x70, /* SCR[7,0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x00 /* Undocumented */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * REV_PANEL = 1 (normally black panel), BGR_PANEL = 1 (BGR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Zig-Zag Type C column inversion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Set display resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0xF0, /* NL = 240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * RESO_SEL = 720RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0xF0 /* WHITE_GND_EN = 1 (GND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * WHITE_FRAME_SEL = 7 frames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * ISC = 0 frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x00, /* PNOEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x00, /* NNOEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x0B, /* PEQGND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x0B, /* NEQGND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x10, /* PEQVCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x10, /* NEQVCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x00, /* PEQVCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x00, /* NEQVCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x00, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x00, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0xFF, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x00, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * VEDIO_NO_CHECK_EN = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * ESD_WHITE_GND_EN = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * ESD_DET_TIME_SEL = 0 frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Undocumented command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_C6, 0x01, 0x00, 0xFF, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x32, /* VRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x32, /* VRN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x77, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0xF1, /* APS = 1 (small),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * VGL_DET_EN = 1, VGH_DET_EN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * VGL_TURBO = 1, VGH_TURBO = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Reference voltage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x07, /* VREF_SEL = 4.2V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x07 /* NVREF_SEL = 4.2V */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x2C, /* VCOMDC_F = -0.67V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x2C /* VCOMDC_B = -0.67V */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Undocumented command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* This command is to set forward GIP timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* This command is to set backward GIP timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0xA5, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Adjust the gamma characteristics of the panel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x12, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct drm_display_mode xbd599_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .hdisplay = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .hsync_start = 720 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hsync_end = 720 + 40 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .htotal = 720 + 40 + 40 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .vdisplay = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .vsync_start = 1440 + 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .vsync_end = 1440 + 18 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .vtotal = 1440 + 18 + 10 + 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .clock = 69000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .width_mm = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .height_mm = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct st7703_panel_desc xbd599_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .mode = &xbd599_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .init_sequence = xbd599_init_sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int st7703_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct st7703 *ctx = panel_to_st7703(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = ctx->desc->init_sequence(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Panel is operational 120 msec after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_dbg(ctx->dev, "Panel init sequence done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int st7703_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct st7703 *ctx = panel_to_st7703(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int st7703_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct st7703 *ctx = panel_to_st7703(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regulator_disable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regulator_disable(ctx->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int st7703_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct st7703 *ctx = panel_to_st7703(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_dbg(ctx->dev, "Resetting the panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = regulator_enable(ctx->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = regulator_enable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto disable_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) usleep_range(20, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) disable_vcc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regulator_disable(ctx->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int st7703_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct st7703 *ctx = panel_to_st7703(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mode = drm_mode_duplicate(connector->dev, ctx->desc->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) drm_mode_vrefresh(ctx->desc->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct drm_panel_funcs st7703_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .disable = st7703_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .unprepare = st7703_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .prepare = st7703_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .enable = st7703_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .get_modes = st7703_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int allpixelson_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct st7703 *ctx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(ctx->dev, "Setting all pixels on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msleep(val * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Reset the panel to get video back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) drm_panel_disable(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) drm_panel_unprepare(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) drm_panel_prepare(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) drm_panel_enable(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DEFINE_SIMPLE_ATTRIBUTE(allpixelson_fops, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) allpixelson_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void st7703_debugfs_init(struct st7703 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ctx->debugfs = debugfs_create_dir(DRV_NAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) debugfs_create_file("allpixelson", 0600, ctx->debugfs, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &allpixelson_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void st7703_debugfs_remove(struct st7703 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) debugfs_remove_recursive(ctx->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ctx->debugfs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int st7703_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct st7703 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_err(dev, "cannot get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ctx->desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dsi->mode_flags = ctx->desc->mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dsi->format = ctx->desc->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dsi->lanes = ctx->desc->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ctx->vcc = devm_regulator_get(dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (IS_ERR(ctx->vcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = PTR_ERR(ctx->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(dev, "Failed to request vcc regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ctx->iovcc = devm_regulator_get(dev, "iovcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (IS_ERR(ctx->iovcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = PTR_ERR(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(dev, "Failed to request iovcc regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) drm_panel_init(&ctx->panel, dev, &st7703_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "mipi_dsi_attach failed (%d). Is host ready?\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_info(dev, "%ux%u@%u %ubpp dsi %udl - ready\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) drm_mode_vrefresh(ctx->desc->mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) st7703_debugfs_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void st7703_shutdown(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct st7703 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = drm_panel_unprepare(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = drm_panel_disable(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int st7703_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct st7703 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) st7703_shutdown(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) st7703_debugfs_remove(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct of_device_id st7703_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { .compatible = "xingbangda,xbd599", .data = &xbd599_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_DEVICE_TABLE(of, st7703_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct mipi_dsi_driver st7703_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .probe = st7703_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .remove = st7703_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .shutdown = st7703_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .of_match_table = st7703_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) module_mipi_dsi_driver(st7703_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_AUTHOR("Guido Günther <agx@sigxcpu.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_DESCRIPTION("DRM driver for Sitronix ST7703 based MIPI DSI panels");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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