^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2019, Michael Srba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct s6e88a0_ams452ef01 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct regulator_bulk_data supplies[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) s6e88a0_ams452ef01 *to_s6e88a0_ams452ef01(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return container_of(panel, struct s6e88a0_ams452ef01, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define dsi_dcs_write_seq(dsi, seq...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ret < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mipi_dsi_device *dsi = ctx->dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dsi->mode_flags |= MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) // set default brightness/gama
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dsi_dcs_write_seq(dsi, 0xca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x80, 0x80, 0x80, // V203 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x80, 0x80, 0x80, // V151 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x80, 0x80, 0x80, // V87 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x80, 0x80, 0x80, // V51 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x80, 0x80, 0x80, // V35 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x80, 0x80, 0x80, // V23 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x80, 0x80, 0x80, // V11 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x6b, 0x68, 0x71, // V3 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x00, 0x00, 0x00); // V1 R,G,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) // set default Amoled Off Ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(dev, "Failed to set display on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mipi_dsi_device *dsi = ctx->dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(dev, "Failed to set display off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct device *dev = &ctx->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(dev, "Failed to enable regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) s6e88a0_ams452ef01_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = s6e88a0_ams452ef01_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_err(dev, "Failed to initialize panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) regulator_bulk_disable(ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int s6e88a0_ams452ef01_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct device *dev = &ctx->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = s6e88a0_ams452ef01_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct drm_display_mode s6e88a0_ams452ef01_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .clock = (540 + 88 + 4 + 20) * (960 + 14 + 2 + 8) * 60 / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .hdisplay = 540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .hsync_start = 540 + 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hsync_end = 540 + 88 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .htotal = 540 + 88 + 4 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .vdisplay = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .vsync_start = 960 + 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .vsync_end = 960 + 14 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .vtotal = 960 + 14 + 2 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .width_mm = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .height_mm = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int s6e88a0_ams452ef01_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mode = drm_mode_duplicate(connector->dev, &s6e88a0_ams452ef01_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct drm_panel_funcs s6e88a0_ams452ef01_panel_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .unprepare = s6e88a0_ams452ef01_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .prepare = s6e88a0_ams452ef01_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .get_modes = s6e88a0_ams452ef01_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int s6e88a0_ams452ef01_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct s6e88a0_ams452ef01 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctx->supplies[0].supply = "vdd3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ctx->supplies[1].supply = "vci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(dev, "Failed to get regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dev, "Failed to get reset-gpios: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctx->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dsi->lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) drm_panel_init(&ctx->panel, dev, &s6e88a0_ams452ef01_panel_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int s6e88a0_ams452ef01_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct s6e88a0_ams452ef01 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id s6e88a0_ams452ef01_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "samsung,s6e88a0-ams452ef01" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_DEVICE_TABLE(of, s6e88a0_ams452ef01_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct mipi_dsi_driver s6e88a0_ams452ef01_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .probe = s6e88a0_ams452ef01_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .remove = s6e88a0_ams452ef01_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .name = "panel-s6e88a0-ams452ef01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .of_match_table = s6e88a0_ams452ef01_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_mipi_dsi_driver(s6e88a0_ams452ef01_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_DESCRIPTION("MIPI-DSI based Panel Driver for AMS452EF01 AMOLED LCD with a S6E88A0 controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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