Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MIPI-DSI based S6E63J0X03 AMOLED lcd 1.63 inch panel driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014-2017 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Inki Dae <inki.dae@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Hoegeun Kwon <hoegeun.kwon@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MCS_LEVEL2_KEY		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MCS_MTP_KEY		0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MCS_MTP_SET3		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX_BRIGHTNESS		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DEFAULT_BRIGHTNESS	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define NUM_GAMMA_STEPS		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GAMMA_CMD_CNT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define FIRST_COLUMN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct s6e63j0x03 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct backlight_device *bl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct regulator_bulk_data supplies[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const struct drm_display_mode default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.clock = 4649,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.hdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.hsync_start = 320 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.hsync_end = 320 + 1 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.htotal = 320 + 1 + 1 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.vdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.vsync_start = 320 + 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.vsync_end = 320 + 150 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.vtotal = 320 + 150 + 1 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static const unsigned char gamma_tbl[NUM_GAMMA_STEPS][GAMMA_CMD_CNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{	/* Gamma 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		0x00, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x52, 0x6b, 0x6f, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		0x28, 0x2d, 0x28, 0x26, 0x27, 0x33, 0x34, 0x32, 0x36, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		0x35, 0x00, 0xab, 0x00, 0xae, 0x00, 0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{	/* gamma 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		0x00, 0x00, 0x00, 0x70, 0x7f, 0x7f, 0x4e, 0x64, 0x69, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		0x27, 0x2a, 0x28, 0x29, 0x27, 0x31, 0x32, 0x31, 0x35, 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		0x35, 0x00, 0xc4, 0x00, 0xca, 0x00, 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{	/* gamma 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		0x00, 0x00, 0x00, 0x65, 0x7b, 0x7d, 0x5f, 0x67, 0x68, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		0x28, 0x29, 0x28, 0x2a, 0x27, 0x31, 0x2f, 0x30, 0x34, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		0x34, 0x00, 0xd9, 0x00, 0xe4, 0x00, 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{	/* gamma 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		0x00, 0x00, 0x00, 0x4d, 0x6f, 0x71, 0x67, 0x6a, 0x6c, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		0x28, 0x28, 0x28, 0x29, 0x27, 0x30, 0x2e, 0x30, 0x32, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		0x31, 0x00, 0xea, 0x00, 0xf6, 0x01, 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{	/* gamma 120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		0x00, 0x00, 0x00, 0x3d, 0x66, 0x68, 0x69, 0x69, 0x69, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		0x28, 0x27, 0x28, 0x28, 0x27, 0x30, 0x2e, 0x2f, 0x31, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		0x30, 0x00, 0xf9, 0x01, 0x05, 0x01, 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{	/* gamma 150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		0x00, 0x00, 0x00, 0x31, 0x51, 0x53, 0x66, 0x66, 0x67, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		0x29, 0x27, 0x28, 0x27, 0x27, 0x2e, 0x2d, 0x2e, 0x31, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		0x30, 0x01, 0x04, 0x01, 0x11, 0x01, 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{	/* gamma 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		0x00, 0x00, 0x00, 0x2f, 0x4f, 0x51, 0x67, 0x65, 0x65, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		0x2a, 0x28, 0x27, 0x25, 0x26, 0x2d, 0x2c, 0x2c, 0x30, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		0x30, 0x01, 0x14, 0x01, 0x23, 0x01, 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{	/* gamma 240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		0x00, 0x00, 0x00, 0x2c, 0x4d, 0x50, 0x65, 0x63, 0x64, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		0x2c, 0x29, 0x26, 0x24, 0x25, 0x2c, 0x2b, 0x2b, 0x30, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		0x30, 0x01, 0x1e, 0x01, 0x2f, 0x01, 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{	/* gamma 300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		MCS_MTP_SET3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		0x00, 0x00, 0x00, 0x38, 0x61, 0x64, 0x65, 0x63, 0x64, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		0x2a, 0x27, 0x26, 0x23, 0x25, 0x2b, 0x2b, 0x2a, 0x30, 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		0x30, 0x01, 0x2d, 0x01, 0x3f, 0x01, 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline struct s6e63j0x03 *panel_to_s6e63j0x03(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return container_of(panel, struct s6e63j0x03, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline ssize_t s6e63j0x03_dcs_write_seq(struct s6e63j0x03 *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					const void *seq, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return mipi_dsi_dcs_write_buffer(dsi, seq, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define s6e63j0x03_dcs_write_seq_static(ctx, seq...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		static const u8 d[] = { seq };				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		s6e63j0x03_dcs_write_seq(ctx, d, ARRAY_SIZE(d));	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline int s6e63j0x03_enable_lv2_command(struct s6e63j0x03 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return s6e63j0x03_dcs_write_seq_static(ctx, MCS_LEVEL2_KEY, 0x5a, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline int s6e63j0x03_apply_mtp_key(struct s6e63j0x03 *ctx, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return s6e63j0x03_dcs_write_seq_static(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				MCS_MTP_KEY, 0x5a, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return s6e63j0x03_dcs_write_seq_static(ctx, MCS_MTP_KEY, 0xa5, 0xa5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int s6e63j0x03_power_on(struct s6e63j0x03 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int s6e63j0x03_power_off(struct s6e63j0x03 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned int s6e63j0x03_get_brightness_index(unsigned int brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	index = brightness / (MAX_BRIGHTNESS / NUM_GAMMA_STEPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (index >= NUM_GAMMA_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		index = NUM_GAMMA_STEPS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int s6e63j0x03_update_gamma(struct s6e63j0x03 *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					unsigned int brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct backlight_device *bl_dev = ctx->bl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	unsigned int index = s6e63j0x03_get_brightness_index(brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = s6e63j0x03_apply_mtp_key(ctx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ret = s6e63j0x03_dcs_write_seq(ctx, gamma_tbl[index], GAMMA_CMD_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = s6e63j0x03_apply_mtp_key(ctx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bl_dev->props.brightness = brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int s6e63j0x03_set_brightness(struct backlight_device *bl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct s6e63j0x03 *ctx = bl_get_data(bl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned int brightness = bl_dev->props.brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return s6e63j0x03_update_gamma(ctx, brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct backlight_ops s6e63j0x03_bl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.update_status = s6e63j0x03_set_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int s6e63j0x03_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ctx->bl_dev->props.power = FB_BLANK_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int s6e63j0x03_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = s6e63j0x03_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int s6e63j0x03_panel_init(struct s6e63j0x03 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = s6e63j0x03_enable_lv2_command(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = s6e63j0x03_apply_mtp_key(ctx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* set porch adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf2, 0x1c, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* set frame freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb5, 0x00, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* set caset, paset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = mipi_dsi_dcs_set_column_address(dsi, FIRST_COLUMN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		default_mode.hdisplay - 1 + FIRST_COLUMN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* set ltps timming 0, 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf8, 0x08, 0x08, 0x08, 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		0x00, 0x2a, 0x02, 0x26, 0x00, 0x00, 0x02, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf7, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* set param pos te_edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* set te rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xe2, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* set param pos default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = s6e63j0x03_apply_mtp_key(ctx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int s6e63j0x03_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = s6e63j0x03_power_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ret = s6e63j0x03_panel_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ctx->bl_dev->props.power = FB_BLANK_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	s6e63j0x03_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int s6e63j0x03_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = s6e63j0x03_apply_mtp_key(ctx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* set elvss_cond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb1, 0x00, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* set pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ret = s6e63j0x03_dcs_write_seq_static(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		MIPI_DCS_SET_ADDRESS_MODE, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/* set default white brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* set white ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ret = s6e63j0x03_dcs_write_seq_static(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* set acl off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ret = s6e63j0x03_dcs_write_seq_static(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		MIPI_DCS_WRITE_POWER_SAVE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	ret = s6e63j0x03_apply_mtp_key(ctx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ctx->bl_dev->props.power = FB_BLANK_UNBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int s6e63j0x03_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 				struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	mode = drm_mode_duplicate(connector->dev, &default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			default_mode.hdisplay, default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			drm_mode_vrefresh(&default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	connector->display_info.width_mm = 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	connector->display_info.height_mm = 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct drm_panel_funcs s6e63j0x03_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.disable = s6e63j0x03_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	.unprepare = s6e63j0x03_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	.prepare = s6e63j0x03_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.enable = s6e63j0x03_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.get_modes = s6e63j0x03_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int s6e63j0x03_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	struct s6e63j0x03 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ctx = devm_kzalloc(dev, sizeof(struct s6e63j0x03), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	dsi->lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	dsi->mode_flags = MIPI_DSI_MODE_EOT_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ctx->supplies[0].supply = "vdd3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	ctx->supplies[1].supply = "vci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 				      ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		dev_err(dev, "failed to get regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		dev_err(dev, "cannot get reset-gpio: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				PTR_ERR(ctx->reset_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	drm_panel_init(&ctx->panel, dev, &s6e63j0x03_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		       DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	ctx->bl_dev = backlight_device_register("s6e63j0x03", dev, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 						&s6e63j0x03_bl_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (IS_ERR(ctx->bl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		dev_err(dev, "failed to register backlight device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		return PTR_ERR(ctx->bl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	ctx->bl_dev->props.max_brightness = MAX_BRIGHTNESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	ctx->bl_dev->props.brightness = DEFAULT_BRIGHTNESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		goto remove_panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) remove_panel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	backlight_device_unregister(ctx->bl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int s6e63j0x03_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	struct s6e63j0x03 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	backlight_device_unregister(ctx->bl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct of_device_id s6e63j0x03_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	{ .compatible = "samsung,s6e63j0x03" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DEVICE_TABLE(of, s6e63j0x03_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct mipi_dsi_driver s6e63j0x03_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	.probe = s6e63j0x03_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	.remove = s6e63j0x03_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		.name = "panel_samsung_s6e63j0x03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		.of_match_table = s6e63j0x03_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) module_mipi_dsi_driver(s6e63j0x03_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_AUTHOR("Hoegeun Kwon <hoegeun.kwon@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_DESCRIPTION("MIPI-DSI based s6e63j0x03 AMOLED LCD Panel Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_LICENSE("GPL v2");