Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ld9040 AMOLED LCD drm_panel driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Derived from drivers/video/backlight/ld9040.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <video/of_videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Manufacturer Command Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MCS_MANPWR		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MCS_ELVSS_ON		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MCS_USER_SETTING	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCS_DISPCTL		0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCS_POWER_CTRL		0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MCS_GTCON		0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MCS_PANEL_CONDITION	0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCS_GAMMA_SET1		0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MCS_GAMMA_CTRL		0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* array of gamma tables for gamma value 2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static u8 const ld9040_gammas[25][22] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ 0xf9, 0x00, 0x13, 0xb2, 0xba, 0xd2, 0x00, 0x30, 0x00, 0xaf, 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	  0xb8, 0xcd, 0x00, 0x3d, 0x00, 0xa8, 0xb8, 0xb7, 0xcd, 0x00, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ 0xf9, 0x00, 0x13, 0xb9, 0xb9, 0xd0, 0x00, 0x3c, 0x00, 0xaf, 0xbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	  0xb6, 0xcb, 0x00, 0x4b, 0x00, 0xa8, 0xb9, 0xb5, 0xcc, 0x00, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ 0xf9, 0x00, 0x13, 0xba, 0xb9, 0xcd, 0x00, 0x41, 0x00, 0xb0, 0xbe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	  0xb5, 0xc9, 0x00, 0x51, 0x00, 0xa9, 0xb9, 0xb5, 0xca, 0x00, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ 0xf9, 0x00, 0x13, 0xb9, 0xb8, 0xcd, 0x00, 0x46, 0x00, 0xb1, 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	  0xb5, 0xc8, 0x00, 0x56, 0x00, 0xaa, 0xb8, 0xb4, 0xc9, 0x00, 0x5d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ 0xf9, 0x00, 0x13, 0xba, 0xb8, 0xcb, 0x00, 0x4b, 0x00, 0xb3, 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	  0xb4, 0xc7, 0x00, 0x5c, 0x00, 0xac, 0xb8, 0xb4, 0xc8, 0x00, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ 0xf9, 0x00, 0x13, 0xbb, 0xb7, 0xca, 0x00, 0x4f, 0x00, 0xb4, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	  0xb3, 0xc7, 0x00, 0x60, 0x00, 0xad, 0xb8, 0xb4, 0xc7, 0x00, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ 0xf9, 0x00, 0x47, 0xba, 0xb6, 0xca, 0x00, 0x53, 0x00, 0xb5, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	  0xb3, 0xc6, 0x00, 0x65, 0x00, 0xae, 0xb8, 0xb3, 0xc7, 0x00, 0x6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ 0xf9, 0x00, 0x71, 0xbb, 0xb5, 0xc8, 0x00, 0x57, 0x00, 0xb5, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  0xb0, 0xc5, 0x00, 0x6a, 0x00, 0xae, 0xb9, 0xb1, 0xc6, 0x00, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ 0xf9, 0x00, 0x7b, 0xbb, 0xb4, 0xc8, 0x00, 0x5b, 0x00, 0xb5, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	  0xb1, 0xc4, 0x00, 0x6e, 0x00, 0xae, 0xb9, 0xb0, 0xc5, 0x00, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 0xf9, 0x00, 0x82, 0xba, 0xb4, 0xc7, 0x00, 0x5f, 0x00, 0xb5, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	  0xb0, 0xc3, 0x00, 0x72, 0x00, 0xae, 0xb8, 0xb0, 0xc3, 0x00, 0x7a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ 0xf9, 0x00, 0x89, 0xba, 0xb3, 0xc8, 0x00, 0x62, 0x00, 0xb6, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	  0xaf, 0xc3, 0x00, 0x76, 0x00, 0xaf, 0xb7, 0xae, 0xc4, 0x00, 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 0xf9, 0x00, 0x8b, 0xb9, 0xb3, 0xc7, 0x00, 0x65, 0x00, 0xb7, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	  0xaf, 0xc3, 0x00, 0x7a, 0x00, 0x80, 0xb6, 0xae, 0xc4, 0x00, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 0xf9, 0x00, 0x93, 0xba, 0xb3, 0xc5, 0x00, 0x69, 0x00, 0xb8, 0xb9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	  0xae, 0xc1, 0x00, 0x7f, 0x00, 0xb0, 0xb6, 0xae, 0xc3, 0x00, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ 0xf9, 0x00, 0x97, 0xba, 0xb2, 0xc5, 0x00, 0x6c, 0x00, 0xb8, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	  0xae, 0xc1, 0x00, 0x82, 0x00, 0xb0, 0xb6, 0xae, 0xc2, 0x00, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ 0xf9, 0x00, 0x9a, 0xba, 0xb1, 0xc4, 0x00, 0x6f, 0x00, 0xb8, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	  0xad, 0xc0, 0x00, 0x86, 0x00, 0xb0, 0xb7, 0xad, 0xc0, 0x00, 0x8d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ 0xf9, 0x00, 0x9c, 0xb9, 0xb0, 0xc4, 0x00, 0x72, 0x00, 0xb8, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	  0xac, 0xbf, 0x00, 0x8a, 0x00, 0xb0, 0xb6, 0xac, 0xc0, 0x00, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ 0xf9, 0x00, 0x9e, 0xba, 0xb0, 0xc2, 0x00, 0x75, 0x00, 0xb9, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	  0xab, 0xbe, 0x00, 0x8e, 0x00, 0xb0, 0xb6, 0xac, 0xbf, 0x00, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ 0xf9, 0x00, 0xa0, 0xb9, 0xaf, 0xc3, 0x00, 0x77, 0x00, 0xb9, 0xb7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	  0xab, 0xbe, 0x00, 0x90, 0x00, 0xb0, 0xb6, 0xab, 0xbf, 0x00, 0x97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ 0xf9, 0x00, 0xa2, 0xb9, 0xaf, 0xc2, 0x00, 0x7a, 0x00, 0xb9, 0xb7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	  0xaa, 0xbd, 0x00, 0x94, 0x00, 0xb0, 0xb5, 0xab, 0xbf, 0x00, 0x9a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ 0xf9, 0x00, 0xa4, 0xb9, 0xaf, 0xc1, 0x00, 0x7d, 0x00, 0xb9, 0xb6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	  0xaa, 0xbb, 0x00, 0x97, 0x00, 0xb1, 0xb5, 0xaa, 0xbf, 0x00, 0x9d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ 0xf9, 0x00, 0xa4, 0xb8, 0xb0, 0xbf, 0x00, 0x80, 0x00, 0xb8, 0xb6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	  0xaa, 0xbc, 0x00, 0x9a, 0x00, 0xb0, 0xb5, 0xab, 0xbd, 0x00, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ 0xf9, 0x00, 0xa8, 0xb8, 0xae, 0xbe, 0x00, 0x84, 0x00, 0xb9, 0xb7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	  0xa8, 0xbc, 0x00, 0x9d, 0x00, 0xb2, 0xb5, 0xaa, 0xbc, 0x00, 0xa4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ 0xf9, 0x00, 0xa9, 0xb6, 0xad, 0xbf, 0x00, 0x86, 0x00, 0xb8, 0xb5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	  0xa8, 0xbc, 0x00, 0xa0, 0x00, 0xb3, 0xb3, 0xa9, 0xbc, 0x00, 0xa7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ 0xf9, 0x00, 0xa9, 0xb7, 0xae, 0xbd, 0x00, 0x89, 0x00, 0xb7, 0xb6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	  0xa8, 0xba, 0x00, 0xa4, 0x00, 0xb1, 0xb4, 0xaa, 0xbb, 0x00, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ 0xf9, 0x00, 0xa7, 0xb4, 0xae, 0xbf, 0x00, 0x91, 0x00, 0xb2, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	  0xaa, 0xbb, 0x00, 0xac, 0x00, 0xb3, 0xb1, 0xaa, 0xbc, 0x00, 0xb3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct ld9040 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct regulator_bulk_data supplies[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 power_on_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct videomode vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* This field is tested by functions directly accessing bus before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * transfer, transfer is skipped if it is set. In case of transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * failure or unexpected response the field is set to error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * Such construct allows to eliminate many checks in higher level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline struct ld9040 *panel_to_ld9040(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return container_of(panel, struct ld9040, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ld9040_clear_error(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret = ctx->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ctx->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int ld9040_spi_write_word(struct ld9040 *ctx, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct spi_device *spi = to_spi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct spi_transfer xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.len		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.tx_buf		= &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	spi_message_add_tail(&xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void ld9040_dcs_write(struct ld9040 *ctx, const u8 *data, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ctx->error < 0 || len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	dev_dbg(ctx->dev, "writing dcs seq: %*ph\n", (int)len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = ld9040_spi_write_word(ctx, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	while (!ret && --len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		++data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		ret = ld9040_spi_write_word(ctx, *data | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dev_err(ctx->dev, "error %d writing dcs seq: %*ph\n", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			(int)len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ctx->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	usleep_range(300, 310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ld9040_dcs_write_seq_static(ctx, seq...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	static const u8 d[] = { seq };\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ld9040_dcs_write(ctx, d, ARRAY_SIZE(d));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void ld9040_brightness_set(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ld9040_dcs_write(ctx, ld9040_gammas[ctx->brightness],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			 ARRAY_SIZE(ld9040_gammas[ctx->brightness]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ld9040_dcs_write_seq_static(ctx, MCS_GAMMA_CTRL, 0x02, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void ld9040_init(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ld9040_dcs_write_seq_static(ctx, MCS_USER_SETTING, 0x5a, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ld9040_dcs_write_seq_static(ctx, MCS_PANEL_CONDITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		0x05, 0x65, 0x96, 0x71, 0x7d, 0x19, 0x3b, 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		0x19, 0x7e, 0x0d, 0xe2, 0x00, 0x00, 0x7e, 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		0x07, 0x07, 0x20, 0x20, 0x20, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ld9040_dcs_write_seq_static(ctx, MCS_DISPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		0x02, 0x08, 0x08, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ld9040_dcs_write_seq_static(ctx, MCS_MANPWR, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ld9040_dcs_write_seq_static(ctx, MCS_POWER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		0x0a, 0x87, 0x25, 0x6a, 0x44, 0x02, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ld9040_dcs_write_seq_static(ctx, MCS_ELVSS_ON, 0x0d, 0x00, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ld9040_dcs_write_seq_static(ctx, MCS_GTCON, 0x09, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ld9040_brightness_set(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ld9040_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ld9040_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int ld9040_power_on(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	msleep(ctx->power_on_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	gpiod_set_value(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	msleep(ctx->reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	gpiod_set_value(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	msleep(ctx->reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ld9040_power_off(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int ld9040_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int ld9040_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct ld9040 *ctx = panel_to_ld9040(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ld9040_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ld9040_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ld9040_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return ld9040_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int ld9040_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct ld9040 *ctx = panel_to_ld9040(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = ld9040_power_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ld9040_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ret = ld9040_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ld9040_unprepare(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int ld9040_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int ld9040_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			    struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct ld9040 *ctx = panel_to_ld9040(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mode = drm_mode_create(connector->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(panel->dev, "failed to create a new display mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	drm_display_mode_from_videomode(&ctx->vm, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	mode->width_mm = ctx->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mode->height_mm = ctx->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct drm_panel_funcs ld9040_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.disable = ld9040_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.unprepare = ld9040_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.prepare = ld9040_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.enable = ld9040_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.get_modes = ld9040_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int ld9040_parse_dt(struct ld9040 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ret = of_get_videomode(np, &ctx->vm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	of_property_read_u32(np, "power-on-delay", &ctx->power_on_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	of_property_read_u32(np, "reset-delay", &ctx->reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int ld9040_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct ld9040 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ctx = devm_kzalloc(dev, sizeof(struct ld9040), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	spi_set_drvdata(spi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ctx->brightness = ARRAY_SIZE(ld9040_gammas) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ret = ld9040_parse_dt(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ctx->supplies[0].supply = "vdd3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ctx->supplies[1].supply = "vci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				      ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(dev, "cannot get reset-gpios %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			PTR_ERR(ctx->reset_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	spi->bits_per_word = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		dev_err(dev, "spi setup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	drm_panel_init(&ctx->panel, dev, &ld9040_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		       DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ld9040_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct ld9040 *ctx = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ld9040_power_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct of_device_id ld9040_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{ .compatible = "samsung,ld9040" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DEVICE_TABLE(of, ld9040_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct spi_device_id ld9040_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{ "ld9040", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DEVICE_TABLE(spi, ld9040_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct spi_driver ld9040_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.probe = ld9040_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.remove = ld9040_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.name = "panel-samsung-ld9040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.of_match_table = ld9040_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) module_spi_driver(ld9040_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_DESCRIPTION("ld9040 LCD Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_LICENSE("GPL v2");