^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics SA 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Philippe Cornu <philippe.cornu@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Yannick Fertre <yannick.fertre@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*** Manufacturer Command Set ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* CMD2 P0 commands (Display Options and Power) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCS_SGOPCTR 0x16 /* Source Bias Current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCS_SDCTR 0x1A /* Source Output Delay Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCS_INVCTR 0x1B /* Inversion Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCS_SETVGN 0x52 /* VG M/S N Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCS_SETVGP 0x54 /* VG M/S P Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GOA_VSTV1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GOA_VSTV2 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GOA_VCLK1 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GOA_VCLK2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GOA_VCLK_OPT1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GOA_BICLK1 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GOA_BICLK2 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GOA_BICLK3 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GOA_BICLK4 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GOA_BICLK_OPT1 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GOA_BICLK_OPT2 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCS_GOA_GPO1 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCS_GOA_GPO2 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCS_GOA_EQ 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCS_GOA_CLK_GALLON 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCS_GOA_FS_SEL0 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCS_GOA_FS_SEL1 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCS_GOA_FS_SEL2 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCS_GOA_FS_SEL3 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCS_GOA_BS_SEL0 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCS_GOA_BS_SEL1 0xB5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCS_GOA_BS_SEL2 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCS_GOA_BS_SEL3 0xC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCS_GOA_BS_SEL4 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* CMD2 P3 commands (Gamma) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct rm68200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct drm_display_mode default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .clock = 52582,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .hdisplay = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .hsync_start = 720 + 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .hsync_end = 720 + 38 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .htotal = 720 + 38 + 8 + 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .vdisplay = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .vsync_start = 1280 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .vsync_end = 1280 + 12 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .vtotal = 1280 + 12 + 4 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .width_mm = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .height_mm = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return container_of(panel, struct rm68200, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) err = mipi_dsi_dcs_write_buffer(dsi, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define dcs_write_seq(ctx, seq...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * This panel is not able to auto-increment all cmd addresses so for some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * them, we need to send them one by one...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define dcs_write_cmd_seq(ctx, cmd, seq...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (i = 0; i < ARRAY_SIZE(d) ; i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void rm68200_init_sequence(struct rm68200 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Enter CMD2 with page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dcs_write_seq(ctx, MCS_INVCTR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dcs_write_seq(ctx, MCS_SDCTR, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dcs_write_seq(ctx, GOA_VSTV1, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dcs_write_seq(ctx, 0x02, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dcs_write_seq(ctx, 0x03, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x00, 0x85, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x00, 0x85, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dcs_write_seq(ctx, 0x2D, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dcs_write_seq(ctx, 0x3D, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x16, 0x12, 0x08, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x05, 0x01, 0x3F, 0x3F, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x15, 0x11, 0x0F, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x0D, 0x09, 0x3F, 0x3F, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x02, 0x06, 0x3F, 0x3F, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x3F, 0x3F, 0x0E, 0x10, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dcs_write_seq(ctx, 0xDC, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dcs_write_seq(ctx, 0xDE, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dcs_write_seq(ctx, 0x01, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x12, 0x0C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x12, 0x0C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Exit CMD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int rm68200_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct rm68200 *ctx = panel_to_rm68200(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!ctx->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ctx->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int rm68200_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct rm68200 *ctx = panel_to_rm68200(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_warn(panel->dev, "failed to set display off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ctx->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regulator_disable(ctx->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int rm68200_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct rm68200 *ctx = panel_to_rm68200(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = regulator_enable(ctx->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ctx->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rm68200_init_sequence(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) msleep(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int rm68200_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rm68200 *ctx = panel_to_rm68200(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ctx->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctx->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int rm68200_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mode = drm_mode_duplicate(connector->dev, &default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default_mode.hdisplay, default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) drm_mode_vrefresh(&default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct drm_panel_funcs rm68200_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .disable = rm68200_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .unprepare = rm68200_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .prepare = rm68200_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .enable = rm68200_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .get_modes = rm68200_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int rm68200_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct rm68200 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "cannot get reset GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctx->supply = devm_regulator_get(dev, "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(ctx->supply)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = PTR_ERR(ctx->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(dev, "cannot get regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dsi->lanes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int rm68200_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct of_device_id raydium_rm68200_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .compatible = "raydium,rm68200" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static struct mipi_dsi_driver raydium_rm68200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .probe = rm68200_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .remove = rm68200_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "panel-raydium-rm68200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .of_match_table = raydium_rm68200_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_mipi_dsi_driver(raydium_rm68200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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