^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Novatek NT39016 TFT LCD panel driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, Maarten ter Huurne <maarten@treewalker.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/media-bus-format.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum nt39016_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) NT39016_REG_SYSTEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) NT39016_REG_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) NT39016_REG_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) NT39016_REG_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) NT39016_REG_SRC_TIMING_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) NT39016_REG_GATE_TIMING_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) NT39016_REG_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) NT39016_REG_INITIAL_FUNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) NT39016_REG_CONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) NT39016_REG_BRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) NT39016_REG_HUE_SATURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) NT39016_REG_RB_SUBCONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) NT39016_REG_R_SUBBRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) NT39016_REG_B_SUBBRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) NT39016_REG_VCOMDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) NT39016_REG_VCOMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) NT39016_REG_VGAM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) NT39016_REG_VGAM34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) NT39016_REG_VGAM56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) NT39016_REG_VCOMDC_TRIM = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NT39016_REG_DISPLAY_MODE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NT39016_SYSTEM_RESET_N BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NT39016_SYSTEM_STANDBY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct nt39016_panel_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct drm_display_mode *display_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 width_mm, height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 bus_format, bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct nt39016 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct drm_panel drm_panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct nt39016_panel_info *panel_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline struct nt39016 *to_nt39016(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return container_of(panel, struct nt39016, drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct reg_sequence nt39016_panel_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RV(NT39016_REG_SYSTEM, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RV(NT39016_REG_TIMING, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RV(NT39016_REG_OP, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RV(NT39016_REG_DATA_IN, 0xCC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RV(NT39016_REG_SRC_TIMING_DELAY, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RV(NT39016_REG_GATE_TIMING_DELAY, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RV(NT39016_REG_RESERVED, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RV(NT39016_REG_INITIAL_FUNC, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RV(NT39016_REG_CONTRAST, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RV(NT39016_REG_BRIGHTNESS, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RV(NT39016_REG_HUE_SATURATION, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RV(NT39016_REG_RB_SUBCONTRAST, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RV(NT39016_REG_R_SUBBRIGHTNESS, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RV(NT39016_REG_B_SUBBRIGHTNESS, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RV(NT39016_REG_VCOMDC, 0x67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RV(NT39016_REG_VCOMAC, 0xA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RV(NT39016_REG_VGAM2, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RV(NT39016_REG_VGAM34, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RV(NT39016_REG_VGAM56, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RV(NT39016_REG_DISPLAY_MODE, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #undef RV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct regmap_range nt39016_regmap_no_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) regmap_reg_range(0x13, 0x1D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regmap_reg_range(0x1F, 0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct regmap_access_table nt39016_regmap_access_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .no_ranges = nt39016_regmap_no_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n_no_ranges = ARRAY_SIZE(nt39016_regmap_no_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct regmap_config nt39016_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .reg_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pad_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .max_register = NT39016_REG_DISPLAY_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .wr_table = &nt39016_regmap_access_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .write_flag_mask = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int nt39016_prepare(struct drm_panel *drm_panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct nt39016 *panel = to_nt39016(drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = regulator_enable(panel->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(drm_panel->dev, "Failed to enable power supply: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Reset the NT39016.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * The documentation says the reset pulse should be at least 40 us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * pass the glitch filter, but when testing I see some resets fail and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * some succeed when using a 70 us delay, so we use 100 us instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) gpiod_set_value_cansleep(panel->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) usleep_range(100, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpiod_set_value_cansleep(panel->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Init all registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = regmap_multi_reg_write(panel->map, nt39016_panel_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ARRAY_SIZE(nt39016_panel_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(drm_panel->dev, "Failed to init registers: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto err_disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err_disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regulator_disable(panel->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int nt39016_unprepare(struct drm_panel *drm_panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct nt39016 *panel = to_nt39016(drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gpiod_set_value_cansleep(panel->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regulator_disable(panel->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int nt39016_enable(struct drm_panel *drm_panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct nt39016 *panel = to_nt39016(drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = regmap_write(panel->map, NT39016_REG_SYSTEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) NT39016_SYSTEM_RESET_N | NT39016_SYSTEM_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(drm_panel->dev, "Unable to enable panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (drm_panel->backlight) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Wait for the picture to be ready before enabling backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int nt39016_disable(struct drm_panel *drm_panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct nt39016 *panel = to_nt39016(drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = regmap_write(panel->map, NT39016_REG_SYSTEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) NT39016_SYSTEM_RESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(drm_panel->dev, "Unable to disable panel: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int nt39016_get_modes(struct drm_panel *drm_panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct nt39016 *panel = to_nt39016(drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const struct nt39016_panel_info *panel_info = panel->panel_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < panel_info->num_modes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mode = drm_mode_duplicate(connector->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &panel_info->display_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mode->type = DRM_MODE_TYPE_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (panel_info->num_modes == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mode->type |= DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) connector->display_info.bpc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) connector->display_info.width_mm = panel_info->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) connector->display_info.height_mm = panel_info->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) drm_display_info_set_bus_formats(&connector->display_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) &panel_info->bus_format, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) connector->display_info.bus_flags = panel_info->bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return panel_info->num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct drm_panel_funcs nt39016_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .prepare = nt39016_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .unprepare = nt39016_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .enable = nt39016_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .disable = nt39016_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .get_modes = nt39016_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int nt39016_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct nt39016 *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) spi_set_drvdata(spi, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) panel->panel_info = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!panel->panel_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) panel->supply = devm_regulator_get(dev, "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(panel->supply)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(dev, "Failed to get power supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return PTR_ERR(panel->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) panel->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ERR(panel->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "Failed to get reset GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return PTR_ERR(panel->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spi->mode = SPI_MODE_3 | SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "Failed to setup SPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) panel->map = devm_regmap_init_spi(spi, &nt39016_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(panel->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(dev, "Failed to init regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(panel->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) drm_panel_init(&panel->drm_panel, dev, &nt39016_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err = drm_panel_of_backlight(&panel->drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "Failed to get backlight handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) drm_panel_add(&panel->drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int nt39016_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct nt39016 *panel = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) drm_panel_remove(&panel->drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) nt39016_disable(&panel->drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) nt39016_unprepare(&panel->drm_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct drm_display_mode kd035g6_display_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { /* 60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .clock = 6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .hdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .hsync_start = 320 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .hsync_end = 320 + 10 + 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .htotal = 320 + 10 + 50 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .vdisplay = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .vsync_start = 240 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .vsync_end = 240 + 5 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .vtotal = 240 + 5 + 1 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { /* 50 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .clock = 5400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .hdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .hsync_start = 320 + 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .hsync_end = 320 + 42 + 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .htotal = 320 + 42 + 50 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .vdisplay = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .vsync_start = 240 + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .vsync_end = 240 + 5 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .vtotal = 240 + 5 + 1 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct nt39016_panel_info kd035g6_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .display_modes = kd035g6_display_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_modes = ARRAY_SIZE(kd035g6_display_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .width_mm = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .height_mm = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct of_device_id nt39016_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .compatible = "kingdisplay,kd035g6-54nt", .data = &kd035g6_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DEVICE_TABLE(of, nt39016_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct spi_driver nt39016_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "nt39016",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .of_match_table = nt39016_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .probe = nt39016_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .remove = nt39016_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) module_spi_driver(nt39016_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_AUTHOR("Maarten ter Huurne <maarten@treewalker.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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