^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * drivers/gpu/drm/panel/panel-ld9040.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ld9040 AMOLED LCD drm_panel driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Derived from drivers/video/backlight/ld9040.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <video/of_videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct lg4573 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct videomode vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline struct lg4573 *panel_to_lg4573(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return container_of(panel, struct lg4573, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int lg4573_spi_write_u16(struct lg4573 *ctx, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct spi_transfer xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __be16 temp = cpu_to_be16(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_dbg(ctx->panel.dev, "writing data: %x\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) xfer.tx_buf = &temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) spi_message_add_tail(&xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return spi_sync(ctx->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int lg4573_spi_write_u16_array(struct lg4573 *ctx, const u16 *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = lg4573_spi_write_u16(ctx, buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int lg4573_spi_write_dcs(struct lg4573 *ctx, u8 dcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return lg4573_spi_write_u16(ctx, (0x70 << 8 | dcs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int lg4573_display_on(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = lg4573_spi_write_dcs(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return lg4573_spi_write_dcs(ctx, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int lg4573_display_off(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = lg4573_spi_write_dcs(ctx, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return lg4573_spi_write_dcs(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int lg4573_display_mode_settings(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const u16 display_mode_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x703A, 0x7270, 0x70B1, 0x7208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x723B, 0x720F, 0x70B2, 0x7200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x72C8, 0x70B3, 0x7200, 0x70B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x7200, 0x70B5, 0x7242, 0x7210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x7210, 0x7200, 0x7220, 0x70B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x720B, 0x720F, 0x723C, 0x7213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x7213, 0x72E8, 0x70B7, 0x7246,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x7206, 0x720C, 0x7200, 0x7200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_dbg(ctx->panel.dev, "transfer display mode settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return lg4573_spi_write_u16_array(ctx, display_mode_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ARRAY_SIZE(display_mode_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int lg4573_power_settings(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const u16 power_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x70C0, 0x7201, 0x7211, 0x70C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x7207, 0x7203, 0x7204, 0x7204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x7204, 0x70C4, 0x7212, 0x7224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x7218, 0x7218, 0x7202, 0x7249,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x70C5, 0x726F, 0x70C6, 0x7241,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x7263,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_dbg(ctx->panel.dev, "transfer power settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return lg4573_spi_write_u16_array(ctx, power_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ARRAY_SIZE(power_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int lg4573_gamma_settings(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const u16 gamma_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x70D0, 0x7203, 0x7207, 0x7273,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x7235, 0x7200, 0x7201, 0x7220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x7200, 0x7203, 0x70D1, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x7207, 0x7273, 0x7235, 0x7200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x7201, 0x7220, 0x7200, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x70D2, 0x7203, 0x7207, 0x7273,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x7235, 0x7200, 0x7201, 0x7220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x7200, 0x7203, 0x70D3, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x7207, 0x7273, 0x7235, 0x7200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x7201, 0x7220, 0x7200, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x70D4, 0x7203, 0x7207, 0x7273,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x7235, 0x7200, 0x7201, 0x7220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x7200, 0x7203, 0x70D5, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x7207, 0x7273, 0x7235, 0x7200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x7201, 0x7220, 0x7200, 0x7203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_dbg(ctx->panel.dev, "transfer gamma settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return lg4573_spi_write_u16_array(ctx, gamma_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ARRAY_SIZE(gamma_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int lg4573_init(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_dbg(ctx->panel.dev, "initializing LCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = lg4573_display_mode_settings(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = lg4573_power_settings(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return lg4573_gamma_settings(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int lg4573_power_on(struct lg4573 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return lg4573_display_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int lg4573_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct lg4573 *ctx = panel_to_lg4573(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return lg4573_display_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int lg4573_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct lg4573 *ctx = panel_to_lg4573(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) lg4573_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return lg4573_power_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct drm_display_mode default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .clock = 28341,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .hdisplay = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .hsync_start = 480 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .hsync_end = 480 + 10 + 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .htotal = 480 + 10 + 59 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .vdisplay = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .vsync_start = 800 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .vsync_end = 800 + 15 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .vtotal = 800 + 15 + 15 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int lg4573_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mode = drm_mode_duplicate(connector->dev, &default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(panel->dev, "failed to add mode %ux%ux@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default_mode.hdisplay, default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) drm_mode_vrefresh(&default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) connector->display_info.width_mm = 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) connector->display_info.height_mm = 103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct drm_panel_funcs lg4573_drm_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .disable = lg4573_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .enable = lg4573_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .get_modes = lg4573_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int lg4573_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct lg4573 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ctx = devm_kzalloc(&spi->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ctx->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spi_set_drvdata(spi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(&spi->dev, "SPI setup failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) drm_panel_init(&ctx->panel, &spi->dev, &lg4573_drm_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int lg4573_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct lg4573 *ctx = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) lg4573_display_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct of_device_id lg4573_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .compatible = "lg,lg4573" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DEVICE_TABLE(of, lg4573_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct spi_driver lg4573_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .probe = lg4573_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .remove = lg4573_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "lg4573",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .of_match_table = lg4573_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) module_spi_driver(lg4573_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_AUTHOR("Heiko Schocher <hs@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DESCRIPTION("lg4573 LCD Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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