Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * LG.Philips LB035Q02 LCD Panel Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on the omapdrm-specific panel-lgphilips-lb035q02 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2013 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Based on a driver by: Steve Sakoman <steve@sakoman.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct lb035q02_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct gpio_desc *enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define to_lb035q02_device(p) container_of(p, struct lb035q02_device, panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int lb035q02_write(struct lb035q02_device *lcd, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct spi_transfer index_xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.len		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.cs_change	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct spi_transfer value_xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.len		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u8	buffer[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* register index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	buffer[0] = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	buffer[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	buffer[2] = reg & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	index_xfer.tx_buf = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	spi_message_add_tail(&index_xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	buffer[4] = 0x72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	buffer[5] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	buffer[6] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	value_xfer.tx_buf = buffer + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	spi_message_add_tail(&value_xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return spi_sync(lcd->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int lb035q02_init(struct lb035q02_device *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Init sequence from page 28 of the lb035q02 spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	} init_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		{ 0x01, 0x6300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		{ 0x02, 0x0200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		{ 0x03, 0x0177 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		{ 0x04, 0x04c7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		{ 0x05, 0xffc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		{ 0x06, 0xe806 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		{ 0x0a, 0x4008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		{ 0x0b, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		{ 0x0d, 0x0030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		{ 0x0e, 0x2800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		{ 0x0f, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		{ 0x16, 0x9f80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		{ 0x17, 0x0a0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		{ 0x1e, 0x00c1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		{ 0x30, 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		{ 0x31, 0x0007 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		{ 0x32, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		{ 0x33, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		{ 0x34, 0x0707 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		{ 0x35, 0x0004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		{ 0x36, 0x0302 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		{ 0x37, 0x0202 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		{ 0x3a, 0x0a0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		{ 0x3b, 0x0806 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	for (i = 0; i < ARRAY_SIZE(init_data); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		ret = lb035q02_write(lcd, init_data[i].index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				     init_data[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int lb035q02_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct lb035q02_device *lcd = to_lb035q02_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	gpiod_set_value_cansleep(lcd->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int lb035q02_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct lb035q02_device *lcd = to_lb035q02_device(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	gpiod_set_value_cansleep(lcd->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct drm_display_mode lb035q02_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.clock = 6500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.hdisplay = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.hsync_start = 320 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.hsync_end = 320 + 20 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.htotal = 320 + 20 + 2 + 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.vdisplay = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.vsync_start = 240 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.vsync_end = 240 + 4 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.vtotal = 240 + 4 + 2 + 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.width_mm = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.height_mm = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int lb035q02_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			      struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mode = drm_mode_duplicate(connector->dev, &lb035q02_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	connector->display_info.width_mm = lb035q02_mode.width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	connector->display_info.height_mm = lb035q02_mode.height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * FIXME: According to the datasheet pixel data is sampled on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * rising edge of the clock, but the code running on the Gumstix Overo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * Palo35 indicates sampling on the negative edge. This should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 * tested on a real device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					  | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 					  | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct drm_panel_funcs lb035q02_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.disable = lb035q02_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.enable = lb035q02_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.get_modes = lb035q02_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int lb035q02_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct lb035q02_device *lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	spi_set_drvdata(spi, lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	lcd->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	lcd->enable_gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (IS_ERR(lcd->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dev_err(&spi->dev, "failed to parse enable gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return PTR_ERR(lcd->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = lb035q02_init(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	drm_panel_init(&lcd->panel, &lcd->spi->dev, &lb035q02_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		       DRM_MODE_CONNECTOR_DPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	drm_panel_add(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int lb035q02_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct lb035q02_device *lcd = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	drm_panel_remove(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	drm_panel_disable(&lcd->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct of_device_id lb035q02_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ .compatible = "lgphilips,lb035q02", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_DEVICE_TABLE(of, lb035q02_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct spi_device_id lb035q02_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ "lb035q02", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_DEVICE_TABLE(spi, lb035q02_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct spi_driver lb035q02_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.probe		= lb035q02_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.remove		= lb035q02_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.id_table	= lb035q02_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.name	= "panel-lg-lb035q02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.of_match_table = lb035q02_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) module_spi_driver(lb035q02_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DESCRIPTION("LG.Philips LB035Q02 LCD Panel driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_LICENSE("GPL");