^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Theobroma Systems Design und Consulting GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/media-bus-format.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <video/display_timing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct ltk050h3146w_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ltk050h3146w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct ltk050h3146w_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int (*init)(struct ltk050h3146w *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ltk050h3146w {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regulator *vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regulator *iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct ltk050h3146w_desc *panel_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct ltk050h3146w_cmd page1_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0x22, 0x0A }, /* BGR SS GS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0x31, 0x00 }, /* column inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0x53, 0xA2 }, /* VCOM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 0x55, 0xA2 }, /* VCOM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0x50, 0x81 }, /* VREG1OUT=5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 0x51, 0x85 }, /* VREG2OUT=-5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 0x62, 0x0D }, /* EQT Time setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The vendor init selected page 1 here _again_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Is this supposed to be page 2?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0xA0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0xA1, 0x1A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0xA2, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0xA3, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0xA4, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0xA5, 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0xA6, 0x1D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0xA7, 0x1E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0xA8, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 0xA9, 0x1C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 0xAA, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 0xAB, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0xAC, 0x1A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0xAD, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0xAE, 0x4D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0xAF, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0xB0, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0xB1, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0xB2, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0xB3, 0x39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0xC0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0xC1, 0x1A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0xC2, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0xC3, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0xC4, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0xC5, 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0xC6, 0x1D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0xC7, 0x1E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0xC8, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0xC9, 0x1C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0xCA, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0xCB, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0xCC, 0x1A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0xCD, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0xCE, 0x4D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0xCF, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0xD0, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0xD1, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0xD2, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0xD3, 0x39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct ltk050h3146w_cmd page3_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0x03, 0x73 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0x04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x06, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x07, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x09, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0x0b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0x0c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0x0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0x0e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0x0f, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0x10, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x11, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x12, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x13, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x14, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x15, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x16, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x17, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x18, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x19, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x1a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x1b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x1c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x1d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x1e, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x1f, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x20, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x21, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x22, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x23, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x24, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x25, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x26, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x27, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x28, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x29, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x2a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x2b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x2c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x2d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x2e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x2f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x30, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x31, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x32, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x33, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x34, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x35, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x36, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x37, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x38, 0x3C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x39, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x3A, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x3B, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x3C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x3D, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x3E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x3F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x40, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x41, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x42, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x43, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x44, 0x1F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x50, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x51, 0x23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x52, 0x45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x53, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x54, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x55, 0xab },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x56, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x57, 0x23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x58, 0x45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x59, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x5a, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x5b, 0xab },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x5c, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x5d, 0xef },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x5e, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x5f, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x60, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x61, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x62, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x63, 0x0E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x64, 0x0F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x65, 0x0C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x66, 0x0D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x67, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x68, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x69, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x6a, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x6b, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x6c, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x6d, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x6e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x6f, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x70, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x71, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x72, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x73, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x74, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x75, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x76, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x77, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x78, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x79, 0x0E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x7a, 0x0F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x7b, 0x0C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0x7c, 0x0D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0x7d, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0x7e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x7f, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0x80, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x81, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x82, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x83, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x84, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x85, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x86, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x87, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x88, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x89, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x8A, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct ltk050h3146w_cmd page4_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x70, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x71, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x82, 0x0F }, /* VGH_MOD clamp level=15v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x84, 0x0F }, /* VGH clamp level 15V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x85, 0x0D }, /* VGL clamp level (-10V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x32, 0xAC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x8C, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x3C, 0xF5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0xB5, 0x07 }, /* GAMMA OP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x31, 0x45 }, /* SOURCE OP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x3A, 0x24 }, /* PS_EN OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x88, 0x33 }, /* LVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ltk050h3146w *panel_to_ltk050h3146w(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return container_of(panel, struct ltk050h3146w, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const u8 b[] = { cmd, seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int ltk050h3146w_init_sequence(struct ltk050h3146w *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Init sequence was supplied by the panel vendor without much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dsi_dcs_write_seq(dsi, 0xdf, 0x93, 0x65, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dsi_dcs_write_seq(dsi, 0xb0, 0x01, 0x03, 0x02, 0x00, 0x64, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0xb5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dsi_dcs_write_seq(dsi, 0xb3, 0x00, 0xb5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dsi_dcs_write_seq(dsi, 0xb7, 0x00, 0xbf, 0x00, 0x00, 0xbf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xc4, 0x23, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dsi_dcs_write_seq(dsi, 0xbb, 0x02, 0x01, 0x24, 0x00, 0x28, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x28, 0x04, 0xcc, 0xcc, 0xcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dsi_dcs_write_seq(dsi, 0xbc, 0x0f, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dsi_dcs_write_seq(dsi, 0xbe, 0x1e, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dsi_dcs_write_seq(dsi, 0xc0, 0x26, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dsi_dcs_write_seq(dsi, 0xc3, 0x04, 0x02, 0x02, 0x76, 0x01, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dsi_dcs_write_seq(dsi, 0xc4, 0x24, 0x80, 0xb4, 0x81, 0x12, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x16, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dsi_dcs_write_seq(dsi, 0xc8, 0x7f, 0x72, 0x67, 0x5d, 0x5d, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x56, 0x41, 0x59, 0x57, 0x55, 0x70, 0x5b, 0x5f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x4f, 0x47, 0x38, 0x23, 0x08, 0x7f, 0x72, 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x5d, 0x5d, 0x50, 0x56, 0x41, 0x59, 0x57, 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x70, 0x5b, 0x5f, 0x4f, 0x47, 0x38, 0x23, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dsi_dcs_write_seq(dsi, 0xd0, 0x1e, 0x1f, 0x57, 0x58, 0x48, 0x4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x44, 0x46, 0x40, 0x1f, 0x42, 0x1f, 0x1f, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dsi_dcs_write_seq(dsi, 0xd1, 0x1e, 0x1f, 0x57, 0x58, 0x49, 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x45, 0x47, 0x41, 0x1f, 0x43, 0x1f, 0x1f, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dsi_dcs_write_seq(dsi, 0xd2, 0x1f, 0x1e, 0x17, 0x18, 0x07, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x0b, 0x09, 0x03, 0x1f, 0x01, 0x1f, 0x1f, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dsi_dcs_write_seq(dsi, 0xd3, 0x1f, 0x1e, 0x17, 0x18, 0x06, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x0a, 0x08, 0x02, 0x1f, 0x00, 0x1f, 0x1f, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dsi_dcs_write_seq(dsi, 0xd4, 0x00, 0x00, 0x00, 0x0c, 0x06, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x01, 0x02, 0x00, 0x60, 0x15, 0xb0, 0x30, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x04, 0x00, 0x60, 0x72, 0x0a, 0x00, 0x60, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dsi_dcs_write_seq(dsi, 0xd5, 0x00, 0x06, 0x06, 0x00, 0x30, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x00, 0x00, 0x00, 0x00, 0xbc, 0x50, 0x00, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x21, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dsi_dcs_write_seq(dsi, 0xdd, 0x2c, 0xa3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dsi_dcs_write_seq(dsi, 0xde, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dsi_dcs_write_seq(dsi, 0xb2, 0x32, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dsi_dcs_write_seq(dsi, 0xb7, 0x3b, 0x70, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dsi_dcs_write_seq(dsi, 0xc1, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dsi_dcs_write_seq(dsi, 0xbb, 0x21, 0x22, 0x23, 0x24, 0x36, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dsi_dcs_write_seq(dsi, 0xc2, 0x20, 0x38, 0x1e, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dsi_dcs_write_seq(dsi, 0xde, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = mipi_dsi_dcs_set_tear_on(dsi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(ctx->dev, "failed to set tear on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct drm_display_mode ltk050h3146w_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .hdisplay = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .hsync_start = 720 + 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .hsync_end = 720 + 42 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .htotal = 720 + 42 + 8 + 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .vdisplay = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .vsync_start = 1280 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .vsync_end = 1280 + 12 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .vtotal = 1280 + 12 + 4 + 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .clock = 64018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .width_mm = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .height_mm = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct ltk050h3146w_desc ltk050h3146w_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .mode = <k050h3146w_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .init = ltk050h3146w_init_sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int ltk050h3146w_a2_select_page(struct ltk050h3146w *ctx, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 d[3] = { 0x98, 0x81, page };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return mipi_dsi_dcs_write(dsi, 0xff, d, ARRAY_SIZE(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int ltk050h3146w_a2_write_page(struct ltk050h3146w *ctx, int page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct ltk050h3146w_cmd *cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = ltk050h3146w_a2_select_page(ctx, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(ctx->dev, "failed to select page %d: %d\n", page, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = mipi_dsi_generic_write(dsi, &cmds[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sizeof(struct ltk050h3146w_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(ctx->dev, "failed to write page %d init cmds: %d\n", page, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int ltk050h3146w_a2_init_sequence(struct ltk050h3146w *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Init sequence was supplied by the panel vendor without much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = ltk050h3146w_a2_write_page(ctx, 3, page3_cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ARRAY_SIZE(page3_cmds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = ltk050h3146w_a2_write_page(ctx, 4, page4_cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ARRAY_SIZE(page4_cmds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = ltk050h3146w_a2_write_page(ctx, 1, page1_cmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ARRAY_SIZE(page1_cmds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = ltk050h3146w_a2_select_page(ctx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(ctx->dev, "failed to select page 0: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* vendor code called this without param, where there should be one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = mipi_dsi_dcs_set_tear_on(dsi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(ctx->dev, "failed to set tear on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct drm_display_mode ltk050h3146w_a2_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .hdisplay = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .hsync_start = 720 + 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .hsync_end = 720 + 42 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .htotal = 720 + 42 + 10 + 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .vdisplay = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .vsync_start = 1280 + 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .vsync_end = 1280 + 18 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .vtotal = 1280 + 18 + 4 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .clock = 65595,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .width_mm = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .height_mm = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct ltk050h3146w_desc ltk050h3146w_a2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .mode = <k050h3146w_a2_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .init = ltk050h3146w_a2_init_sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int ltk050h3146w_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct ltk050h3146w *ctx = panel_to_ltk050h3146w(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(ctx->dev, "failed to set display off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regulator_disable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regulator_disable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ctx->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int ltk050h3146w_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct ltk050h3146w *ctx = panel_to_ltk050h3146w(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ctx->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_dbg(ctx->dev, "Resetting the panel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = regulator_enable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(ctx->dev, "Failed to enable vci supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = regulator_enable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto disable_vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) gpiod_set_value_cansleep(ctx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) gpiod_set_value_cansleep(ctx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = ctx->panel_desc->init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* T9: 120ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = mipi_dsi_dcs_set_display_on(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(ctx->dev, "Failed to set display on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto disable_iovcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctx->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) disable_iovcc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regulator_disable(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) disable_vci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) regulator_disable(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int ltk050h3146w_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct ltk050h3146w *ctx = panel_to_ltk050h3146w(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mode = drm_mode_duplicate(connector->dev, ctx->panel_desc->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct drm_panel_funcs ltk050h3146w_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .unprepare = ltk050h3146w_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .prepare = ltk050h3146w_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .get_modes = ltk050h3146w_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int ltk050h3146w_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct ltk050h3146w *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ctx->panel_desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!ctx->panel_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (IS_ERR(ctx->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_err(dev, "cannot get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return PTR_ERR(ctx->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ctx->vci = devm_regulator_get(dev, "vci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(ctx->vci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = PTR_ERR(ctx->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(dev, "Failed to request vci regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ctx->iovcc = devm_regulator_get(dev, "iovcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (IS_ERR(ctx->iovcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = PTR_ERR(ctx->iovcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_err(dev, "Failed to request iovcc regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) drm_panel_init(&ctx->panel, &dsi->dev, <k050h3146w_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(dev, "mipi_dsi_attach failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void ltk050h3146w_shutdown(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct ltk050h3146w *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = drm_panel_unprepare(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = drm_panel_disable(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int ltk050h3146w_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct ltk050h3146w *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ltk050h3146w_shutdown(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct of_device_id ltk050h3146w_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .compatible = "leadtek,ltk050h3146w",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .data = <k050h3146w_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .compatible = "leadtek,ltk050h3146w-a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .data = <k050h3146w_a2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_DEVICE_TABLE(of, ltk050h3146w_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct mipi_dsi_driver ltk050h3146w_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = "panel-leadtek-ltk050h3146w",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .of_match_table = ltk050h3146w_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .probe = ltk050h3146w_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .remove = ltk050h3146w_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .shutdown = ltk050h3146w_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) module_mipi_dsi_driver(ltk050h3146w_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MODULE_DESCRIPTION("DRM driver for Leadtek LTK050H3146W MIPI DSI panel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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