^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Amarula Solutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jagan Teki <jagan@amarulasolutions.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FEIYANG_INIT_CMD_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct feiyang {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct drm_panel panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct regulator *dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regulator *avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return container_of(panel, struct feiyang, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct feiyang_init_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 data[FEIYANG_INIT_CMD_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct feiyang_init_cmd feiyang_init_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .data = { 0x80, 0x58 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .data = { 0x81, 0x47 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .data = { 0x82, 0xD4 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .data = { 0x83, 0x88 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .data = { 0x84, 0xA9 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .data = { 0x85, 0xC3 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .data = { 0x86, 0x82 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int feiyang_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct feiyang *ctx = panel_to_feiyang(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mipi_dsi_device *dsi = ctx->dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = regulator_enable(ctx->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* T1 (dvdd start + dvdd rise) 0 < T1 <= 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = regulator_enable(ctx->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) gpiod_set_value(ctx->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * T5 + T6 (avdd rise + video & logic signal rise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * T5 >= 10ms, 0 < T6 <= 10ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) gpiod_set_value(ctx->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct feiyang_init_cmd *cmd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &feiyang_init_cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FEIYANG_INIT_CMD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int feiyang_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct feiyang *ctx = panel_to_feiyang(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mipi_dsi_dcs_set_display_on(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int feiyang_disable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct feiyang *ctx = panel_to_feiyang(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return mipi_dsi_dcs_set_display_off(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int feiyang_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct feiyang *ctx = panel_to_feiyang(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(panel->dev, "failed to set display off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) gpiod_set_value(ctx->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regulator_disable(ctx->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* T11 (dvdd rise to fall) 0 < T11 <= 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) regulator_disable(ctx->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct drm_display_mode feiyang_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .clock = 55000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hdisplay = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .hsync_start = 1024 + 310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .hsync_end = 1024 + 310 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .htotal = 1024 + 310 + 20 + 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .vdisplay = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .vsync_start = 600 + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .vsync_end = 600 + 12 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .vtotal = 600 + 12 + 2 + 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int feiyang_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct feiyang *ctx = panel_to_feiyang(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mode = drm_mode_duplicate(connector->dev, &feiyang_default_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) feiyang_default_mode.hdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) feiyang_default_mode.vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) drm_mode_vrefresh(&feiyang_default_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct drm_panel_funcs feiyang_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .disable = feiyang_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .unprepare = feiyang_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .prepare = feiyang_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .enable = feiyang_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .get_modes = feiyang_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int feiyang_dsi_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct feiyang *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ctx->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) drm_panel_init(&ctx->panel, &dsi->dev, &feiyang_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ctx->dvdd = devm_regulator_get(&dsi->dev, "dvdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (IS_ERR(ctx->dvdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(&dsi->dev, "Couldn't get dvdd regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return PTR_ERR(ctx->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctx->avdd = devm_regulator_get(&dsi->dev, "avdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (IS_ERR(ctx->avdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(&dsi->dev, "Couldn't get avdd regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return PTR_ERR(ctx->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(ctx->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(ctx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = drm_panel_of_backlight(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) drm_panel_add(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int feiyang_dsi_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct feiyang *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) drm_panel_remove(&ctx->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct of_device_id feiyang_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .compatible = "feiyang,fy07024di26a30d", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_DEVICE_TABLE(of, feiyang_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct mipi_dsi_driver feiyang_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .probe = feiyang_dsi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .remove = feiyang_dsi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "feiyang-fy07024di26a30d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .of_match_table = feiyang_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) module_mipi_dsi_driver(feiyang_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DESCRIPTION("Feiyang FY07024DI26A30-D MIPI-DSI LCD panel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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