^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jitao Shi <jitao.shi@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct panel_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct drm_display_mode *modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int bpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @width_mm: width of the panel's active display area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @height_mm: height of the panel's active display area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) } size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum mipi_dsi_pixel_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const struct panel_init_cmd *init_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool discharge_on_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct boe_panel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct drm_panel base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct panel_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum drm_panel_orientation orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regulator *pp1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regulator *avee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct regulator *avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gpio_desc *enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum dsi_cmd_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) INIT_DCS_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DELAY_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct panel_init_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum dsi_cmd_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define _INIT_DCS_CMD(...) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .type = INIT_DCS_CMD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .len = sizeof((char[]){__VA_ARGS__}), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .data = (char[]){__VA_ARGS__} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _INIT_DELAY_CMD(...) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .type = DELAY_CMD,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .len = sizeof((char[]){__VA_ARGS__}), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .data = (char[]){__VA_ARGS__} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct panel_init_cmd boe_init_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) _INIT_DELAY_CMD(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) _INIT_DCS_CMD(0xB0, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _INIT_DCS_CMD(0xB1, 0xE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) _INIT_DCS_CMD(0xB3, 0x52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) _INIT_DCS_CMD(0xB0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) _INIT_DCS_CMD(0xB3, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) _INIT_DCS_CMD(0xB0, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) _INIT_DCS_CMD(0xB8, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) _INIT_DCS_CMD(0xB0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) _INIT_DCS_CMD(0xB6, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) _INIT_DCS_CMD(0xBA, 0x8B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) _INIT_DCS_CMD(0xBF, 0x1A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) _INIT_DCS_CMD(0xC0, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) _INIT_DCS_CMD(0xC2, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) _INIT_DCS_CMD(0xC3, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) _INIT_DCS_CMD(0xC4, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) _INIT_DCS_CMD(0xC5, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) _INIT_DCS_CMD(0xB0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) _INIT_DCS_CMD(0xE0, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) _INIT_DCS_CMD(0xE1, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) _INIT_DCS_CMD(0xDC, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) _INIT_DCS_CMD(0xDD, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) _INIT_DCS_CMD(0xCC, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) _INIT_DCS_CMD(0xCD, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) _INIT_DCS_CMD(0xC8, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) _INIT_DCS_CMD(0xD2, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) _INIT_DCS_CMD(0xD3, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) _INIT_DCS_CMD(0xE6, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) _INIT_DCS_CMD(0xE7, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) _INIT_DCS_CMD(0xC4, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) _INIT_DCS_CMD(0xC5, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) _INIT_DCS_CMD(0xD8, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) _INIT_DCS_CMD(0xD9, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) _INIT_DCS_CMD(0xC2, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) _INIT_DCS_CMD(0xC3, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) _INIT_DCS_CMD(0xD6, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) _INIT_DCS_CMD(0xD7, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) _INIT_DCS_CMD(0xC0, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) _INIT_DCS_CMD(0xC1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) _INIT_DCS_CMD(0xD4, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) _INIT_DCS_CMD(0xD5, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) _INIT_DCS_CMD(0xCA, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) _INIT_DCS_CMD(0xCB, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) _INIT_DCS_CMD(0xDE, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _INIT_DCS_CMD(0xDF, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) _INIT_DCS_CMD(0xB0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) _INIT_DCS_CMD(0xC0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) _INIT_DCS_CMD(0xC1, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _INIT_DCS_CMD(0xC2, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) _INIT_DCS_CMD(0xC3, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) _INIT_DCS_CMD(0xC4, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) _INIT_DCS_CMD(0xC5, 0x1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) _INIT_DCS_CMD(0xC6, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) _INIT_DCS_CMD(0xC7, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) _INIT_DCS_CMD(0xC8, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) _INIT_DCS_CMD(0xC9, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) _INIT_DCS_CMD(0xCA, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) _INIT_DCS_CMD(0xCB, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) _INIT_DCS_CMD(0xCC, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) _INIT_DCS_CMD(0xCD, 0x2E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) _INIT_DCS_CMD(0xCE, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) _INIT_DCS_CMD(0xCF, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) _INIT_DCS_CMD(0xD0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) _INIT_DCS_CMD(0xD2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) _INIT_DCS_CMD(0xD3, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) _INIT_DCS_CMD(0xD4, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) _INIT_DCS_CMD(0xD5, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) _INIT_DCS_CMD(0xD6, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) _INIT_DCS_CMD(0xD7, 0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) _INIT_DCS_CMD(0xD8, 0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) _INIT_DCS_CMD(0xD9, 0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) _INIT_DCS_CMD(0xDA, 0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) _INIT_DCS_CMD(0xDB, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) _INIT_DCS_CMD(0xDC, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) _INIT_DCS_CMD(0xDD, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) _INIT_DCS_CMD(0xDE, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) _INIT_DCS_CMD(0xDF, 0x2E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) _INIT_DCS_CMD(0xE0, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) _INIT_DCS_CMD(0xE1, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) _INIT_DCS_CMD(0xE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) _INIT_DCS_CMD(0xB0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) _INIT_DCS_CMD(0xC8, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) _INIT_DCS_CMD(0xC9, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) _INIT_DCS_CMD(0xC3, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) _INIT_DCS_CMD(0xE7, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) _INIT_DCS_CMD(0xC5, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) _INIT_DCS_CMD(0xDE, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) _INIT_DCS_CMD(0xCA, 0x43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) _INIT_DCS_CMD(0xC9, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) _INIT_DCS_CMD(0xE4, 0xC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) _INIT_DCS_CMD(0xE5, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) _INIT_DCS_CMD(0xCB, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) _INIT_DCS_CMD(0xB0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) _INIT_DCS_CMD(0xB8, 0xA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) _INIT_DCS_CMD(0xC0, 0xA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) _INIT_DCS_CMD(0xC7, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) _INIT_DCS_CMD(0xD5, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) _INIT_DCS_CMD(0xB8, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) _INIT_DCS_CMD(0xC0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) _INIT_DCS_CMD(0xBC, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) _INIT_DCS_CMD(0xB0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) _INIT_DCS_CMD(0xB1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) _INIT_DCS_CMD(0xB2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) _INIT_DCS_CMD(0xB3, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) _INIT_DCS_CMD(0xB4, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) _INIT_DCS_CMD(0xB5, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) _INIT_DCS_CMD(0xB6, 0x4E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) _INIT_DCS_CMD(0xB7, 0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) _INIT_DCS_CMD(0xB8, 0x97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) _INIT_DCS_CMD(0xB9, 0xDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) _INIT_DCS_CMD(0xBA, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) _INIT_DCS_CMD(0xBB, 0xA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) _INIT_DCS_CMD(0xBC, 0x2B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) _INIT_DCS_CMD(0xBD, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) _INIT_DCS_CMD(0xBE, 0xA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) _INIT_DCS_CMD(0xBF, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) _INIT_DCS_CMD(0xC0, 0x61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) _INIT_DCS_CMD(0xC1, 0x97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) _INIT_DCS_CMD(0xC2, 0xB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) _INIT_DCS_CMD(0xC3, 0xCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) _INIT_DCS_CMD(0xC4, 0xD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) _INIT_DCS_CMD(0xC5, 0xE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) _INIT_DCS_CMD(0xC6, 0xF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) _INIT_DCS_CMD(0xB0, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) _INIT_DCS_CMD(0xB1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) _INIT_DCS_CMD(0xB2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) _INIT_DCS_CMD(0xB3, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) _INIT_DCS_CMD(0xB4, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) _INIT_DCS_CMD(0xB5, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) _INIT_DCS_CMD(0xB6, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) _INIT_DCS_CMD(0xB7, 0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) _INIT_DCS_CMD(0xB8, 0x98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) _INIT_DCS_CMD(0xB9, 0xDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) _INIT_DCS_CMD(0xBA, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) _INIT_DCS_CMD(0xBB, 0xA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) _INIT_DCS_CMD(0xBC, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) _INIT_DCS_CMD(0xBD, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) _INIT_DCS_CMD(0xBE, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) _INIT_DCS_CMD(0xBF, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) _INIT_DCS_CMD(0xC0, 0x62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) _INIT_DCS_CMD(0xC1, 0x9B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) _INIT_DCS_CMD(0xC2, 0xB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) _INIT_DCS_CMD(0xC3, 0xCF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) _INIT_DCS_CMD(0xC4, 0xDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) _INIT_DCS_CMD(0xC5, 0xE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) _INIT_DCS_CMD(0xC6, 0xF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) _INIT_DCS_CMD(0xB0, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) _INIT_DCS_CMD(0xB1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) _INIT_DCS_CMD(0xB2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) _INIT_DCS_CMD(0xB3, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) _INIT_DCS_CMD(0xB4, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) _INIT_DCS_CMD(0xB5, 0x3B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) _INIT_DCS_CMD(0xB6, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) _INIT_DCS_CMD(0xB7, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) _INIT_DCS_CMD(0xB8, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) _INIT_DCS_CMD(0xB9, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) _INIT_DCS_CMD(0xBA, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) _INIT_DCS_CMD(0xBB, 0xAD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) _INIT_DCS_CMD(0xBC, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) _INIT_DCS_CMD(0xBD, 0x3A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) _INIT_DCS_CMD(0xBE, 0xAE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) _INIT_DCS_CMD(0xBF, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) _INIT_DCS_CMD(0xC0, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) _INIT_DCS_CMD(0xC1, 0x9E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) _INIT_DCS_CMD(0xC2, 0xB8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) _INIT_DCS_CMD(0xC3, 0xD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) _INIT_DCS_CMD(0xC4, 0xDD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) _INIT_DCS_CMD(0xC5, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) _INIT_DCS_CMD(0xC6, 0xF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) _INIT_DCS_CMD(0xB0, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) _INIT_DCS_CMD(0xB1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) _INIT_DCS_CMD(0xB2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) _INIT_DCS_CMD(0xB3, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) _INIT_DCS_CMD(0xB4, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) _INIT_DCS_CMD(0xB5, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) _INIT_DCS_CMD(0xB6, 0x4E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) _INIT_DCS_CMD(0xB7, 0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) _INIT_DCS_CMD(0xB8, 0x97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) _INIT_DCS_CMD(0xB9, 0xDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) _INIT_DCS_CMD(0xBA, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) _INIT_DCS_CMD(0xBB, 0xA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) _INIT_DCS_CMD(0xBC, 0x2B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) _INIT_DCS_CMD(0xBD, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) _INIT_DCS_CMD(0xBE, 0xA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) _INIT_DCS_CMD(0xBF, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) _INIT_DCS_CMD(0xC0, 0x61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) _INIT_DCS_CMD(0xC1, 0x97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) _INIT_DCS_CMD(0xC2, 0xB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) _INIT_DCS_CMD(0xC3, 0xCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) _INIT_DCS_CMD(0xC4, 0xD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) _INIT_DCS_CMD(0xC5, 0xE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) _INIT_DCS_CMD(0xC6, 0xF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) _INIT_DCS_CMD(0xB0, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) _INIT_DCS_CMD(0xB1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) _INIT_DCS_CMD(0xB2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) _INIT_DCS_CMD(0xB3, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) _INIT_DCS_CMD(0xB4, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) _INIT_DCS_CMD(0xB5, 0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) _INIT_DCS_CMD(0xB6, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) _INIT_DCS_CMD(0xB7, 0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) _INIT_DCS_CMD(0xB8, 0x98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) _INIT_DCS_CMD(0xB9, 0xDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) _INIT_DCS_CMD(0xBA, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) _INIT_DCS_CMD(0xBB, 0xA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) _INIT_DCS_CMD(0xBC, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) _INIT_DCS_CMD(0xBD, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) _INIT_DCS_CMD(0xBE, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) _INIT_DCS_CMD(0xBF, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) _INIT_DCS_CMD(0xC0, 0x62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) _INIT_DCS_CMD(0xC1, 0x9B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) _INIT_DCS_CMD(0xC2, 0xB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) _INIT_DCS_CMD(0xC3, 0xCF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) _INIT_DCS_CMD(0xC4, 0xDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) _INIT_DCS_CMD(0xC5, 0xE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) _INIT_DCS_CMD(0xC6, 0xF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) _INIT_DCS_CMD(0xB0, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) _INIT_DCS_CMD(0xB1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) _INIT_DCS_CMD(0xB2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) _INIT_DCS_CMD(0xB3, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) _INIT_DCS_CMD(0xB4, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) _INIT_DCS_CMD(0xB5, 0x3B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) _INIT_DCS_CMD(0xB6, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) _INIT_DCS_CMD(0xB7, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) _INIT_DCS_CMD(0xB8, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) _INIT_DCS_CMD(0xB9, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) _INIT_DCS_CMD(0xBA, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) _INIT_DCS_CMD(0xBB, 0xAD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) _INIT_DCS_CMD(0xBC, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) _INIT_DCS_CMD(0xBD, 0x3A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) _INIT_DCS_CMD(0xBE, 0xAE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) _INIT_DCS_CMD(0xBF, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) _INIT_DCS_CMD(0xC0, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) _INIT_DCS_CMD(0xC1, 0x9E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) _INIT_DCS_CMD(0xC2, 0xB8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) _INIT_DCS_CMD(0xC3, 0xD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) _INIT_DCS_CMD(0xC4, 0xDD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) _INIT_DCS_CMD(0xC5, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) _INIT_DCS_CMD(0xC6, 0xF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) _INIT_DCS_CMD(0xC7, 0xFA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) _INIT_DCS_CMD(0xC8, 0xFC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) _INIT_DCS_CMD(0xC9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) _INIT_DCS_CMD(0xCA, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) _INIT_DCS_CMD(0xCB, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) _INIT_DCS_CMD(0xCC, 0xAF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) _INIT_DCS_CMD(0xCD, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) _INIT_DCS_CMD(0xCE, 0xFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) _INIT_DCS_CMD(0xB0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) _INIT_DCS_CMD(0xB3, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) _INIT_DCS_CMD(0xB0, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) _INIT_DCS_CMD(0xB8, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) _INIT_DELAY_CMD(150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) _INIT_DELAY_CMD(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) _INIT_DCS_CMD(0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) _INIT_DELAY_CMD(120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) _INIT_DCS_CMD(0x29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) _INIT_DELAY_CMD(120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) _INIT_DELAY_CMD(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) _INIT_DCS_CMD(0xB0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) _INIT_DCS_CMD(0xC0, 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) _INIT_DCS_CMD(0xC1, 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) _INIT_DCS_CMD(0xC2, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) _INIT_DCS_CMD(0xC3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) _INIT_DCS_CMD(0xC4, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) _INIT_DCS_CMD(0xC5, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) _INIT_DCS_CMD(0xC6, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) _INIT_DCS_CMD(0xC7, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) _INIT_DCS_CMD(0xC8, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) _INIT_DCS_CMD(0xC9, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) _INIT_DCS_CMD(0xCA, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) _INIT_DCS_CMD(0xCB, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) _INIT_DCS_CMD(0xCC, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) _INIT_DCS_CMD(0xCD, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) _INIT_DCS_CMD(0xCE, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) _INIT_DCS_CMD(0xCF, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) _INIT_DCS_CMD(0xD0, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) _INIT_DCS_CMD(0xD1, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) _INIT_DCS_CMD(0xD2, 0x41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) _INIT_DCS_CMD(0xD3, 0x41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) _INIT_DCS_CMD(0xD4, 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) _INIT_DCS_CMD(0xD5, 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) _INIT_DCS_CMD(0xD6, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) _INIT_DCS_CMD(0xD7, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) _INIT_DCS_CMD(0xD8, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) _INIT_DCS_CMD(0xD9, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) _INIT_DCS_CMD(0xDA, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) _INIT_DCS_CMD(0xDB, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) _INIT_DCS_CMD(0xDC, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) _INIT_DCS_CMD(0xDD, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) _INIT_DCS_CMD(0xDE, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) _INIT_DCS_CMD(0xDF, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) _INIT_DCS_CMD(0xE0, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) _INIT_DCS_CMD(0xE1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) _INIT_DCS_CMD(0xE2, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) _INIT_DCS_CMD(0xE3, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) _INIT_DCS_CMD(0xE4, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) _INIT_DCS_CMD(0xE5, 0x4F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) _INIT_DCS_CMD(0xE6, 0x41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) _INIT_DCS_CMD(0xE7, 0x41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) _INIT_DELAY_CMD(150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return container_of(panel, struct boe_panel, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int boe_panel_init_dcs_cmd(struct boe_panel *boe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct mipi_dsi_device *dsi = boe->dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct drm_panel *panel = &boe->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (boe->desc->init_cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (i = 0; init_cmds[i].len != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct panel_init_cmd *cmd = &init_cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) switch (cmd->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case DELAY_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msleep(cmd->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case INIT_DCS_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = mipi_dsi_dcs_write(dsi, cmd->data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cmd->len <= 1 ? NULL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &cmd->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cmd->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(panel->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "failed to write command %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int boe_panel_enter_sleep_mode(struct boe_panel *boe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct mipi_dsi_device *dsi = boe->dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = mipi_dsi_dcs_set_display_off(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int boe_panel_unprepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct boe_panel *boe = to_boe_panel(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!boe->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = boe_panel_enter_sleep_mode(boe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(panel->dev, "failed to set panel off: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (boe->desc->discharge_on_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regulator_disable(boe->avee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regulator_disable(boe->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regulator_disable(boe->pp1800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regulator_disable(boe->avee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) regulator_disable(boe->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) regulator_disable(boe->pp1800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) boe->prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int boe_panel_prepare(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct boe_panel *boe = to_boe_panel(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (boe->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = regulator_enable(boe->pp1800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = regulator_enable(boe->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto poweroff1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = regulator_enable(boe->avee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto poweroffavdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) gpiod_set_value(boe->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) gpiod_set_value(boe->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) usleep_range(6000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = boe_panel_init_dcs_cmd(boe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(panel->dev, "failed to init panel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) boe->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) poweroff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) regulator_disable(boe->avee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) poweroffavdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regulator_disable(boe->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) poweroff1v8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regulator_disable(boe->pp1800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int boe_panel_enable(struct drm_panel *panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) msleep(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct drm_display_mode boe_tv101wum_nl6_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .clock = 159425,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .hdisplay = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .hsync_start = 1200 + 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .hsync_end = 1200 + 100 + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .htotal = 1200 + 100 + 40 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .vdisplay = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .vsync_start = 1920 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .vsync_end = 1920 + 10 + 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .vtotal = 1920 + 10 + 14 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct panel_desc boe_tv101wum_nl6_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .modes = &boe_tv101wum_nl6_default_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .bpc = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .width_mm = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .height_mm = 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MIPI_DSI_MODE_LPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .init_cmds = boe_init_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .discharge_on_disable = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .clock = 157000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .hdisplay = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .hsync_start = 1200 + 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .hsync_end = 1200 + 60 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .htotal = 1200 + 60 + 24 + 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .vdisplay = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .vsync_start = 1920 + 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .vsync_end = 1920 + 16 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .vtotal = 1920 + 16 + 4 + 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct panel_desc auo_kd101n80_45na_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .modes = &auo_kd101n80_45na_default_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .bpc = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .width_mm = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .height_mm = 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MIPI_DSI_MODE_LPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .init_cmds = auo_kd101n80_45na_init_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .discharge_on_disable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .clock = 159916,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .hdisplay = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .hsync_start = 1200 + 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .hsync_end = 1200 + 80 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .htotal = 1200 + 80 + 24 + 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .vdisplay = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .vsync_start = 1920 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .vsync_end = 1920 + 20 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .vtotal = 1920 + 20 + 4 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct panel_desc boe_tv101wum_n53_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .modes = &boe_tv101wum_n53_default_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .bpc = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .width_mm = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .height_mm = 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MIPI_DSI_MODE_LPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .init_cmds = boe_init_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct drm_display_mode auo_b101uan08_3_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .clock = 159667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .hdisplay = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .hsync_start = 1200 + 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .hsync_end = 1200 + 60 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .htotal = 1200 + 60 + 4 + 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .vdisplay = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .vsync_start = 1920 + 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .vsync_end = 1920 + 34 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .vtotal = 1920 + 34 + 2 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const struct panel_desc auo_b101uan08_3_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .modes = &auo_b101uan08_3_default_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .bpc = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .width_mm = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .height_mm = 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MIPI_DSI_MODE_LPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .init_cmds = auo_b101uan08_3_init_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct drm_display_mode boe_tv105wum_nw0_default_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .clock = 159916,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .hdisplay = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .hsync_start = 1200 + 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .hsync_end = 1200 + 80 + 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .htotal = 1200 + 80 + 24 + 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .vdisplay = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .vsync_start = 1920 + 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .vsync_end = 1920 + 20 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .vtotal = 1920 + 20 + 4 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const struct panel_desc boe_tv105wum_nw0_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .modes = &boe_tv105wum_nw0_default_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .bpc = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .width_mm = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .height_mm = 226,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .format = MIPI_DSI_FMT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MIPI_DSI_MODE_LPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .init_cmds = boe_init_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int boe_panel_get_modes(struct drm_panel *panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct boe_panel *boe = to_boe_panel(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) const struct drm_display_mode *m = boe->desc->modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mode = drm_mode_duplicate(connector->dev, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) connector->display_info.width_mm = boe->desc->size.width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) connector->display_info.height_mm = boe->desc->size.height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) connector->display_info.bpc = boe->desc->bpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) drm_connector_set_panel_orientation(connector, boe->orientation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const struct drm_panel_funcs boe_panel_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .unprepare = boe_panel_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .prepare = boe_panel_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .enable = boe_panel_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .get_modes = boe_panel_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int boe_panel_add(struct boe_panel *boe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct device *dev = &boe->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) boe->avdd = devm_regulator_get(dev, "avdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (IS_ERR(boe->avdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return PTR_ERR(boe->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) boe->avee = devm_regulator_get(dev, "avee");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (IS_ERR(boe->avee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return PTR_ERR(boe->avee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) boe->pp1800 = devm_regulator_get(dev, "pp1800");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (IS_ERR(boe->pp1800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return PTR_ERR(boe->pp1800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (IS_ERR(boe->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_err(dev, "cannot get reset-gpios %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PTR_ERR(boe->enable_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return PTR_ERR(boe->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) gpiod_set_value(boe->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) drm_panel_init(&boe->base, dev, &boe_panel_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err = of_drm_get_panel_orientation(dev->of_node, &boe->orientation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) err = drm_panel_of_backlight(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) boe->base.funcs = &boe_panel_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) boe->base.dev = &boe->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) drm_panel_add(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int boe_panel_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct boe_panel *boe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) const struct panel_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!boe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) desc = of_device_get_match_data(&dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dsi->lanes = desc->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dsi->format = desc->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dsi->mode_flags = desc->mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) boe->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) boe->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = boe_panel_add(boe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mipi_dsi_set_drvdata(dsi, boe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) drm_panel_remove(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) drm_panel_disable(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) drm_panel_unprepare(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int boe_panel_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) boe_panel_shutdown(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (boe->base.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) drm_panel_remove(&boe->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct of_device_id boe_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { .compatible = "boe,tv101wum-nl6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .data = &boe_tv101wum_nl6_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { .compatible = "auo,kd101n80-45na",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .data = &auo_kd101n80_45na_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { .compatible = "boe,tv101wum-n53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .data = &boe_tv101wum_n53_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { .compatible = "auo,b101uan08.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .data = &auo_b101uan08_3_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) { .compatible = "boe,tv105wum-nw0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .data = &boe_tv105wum_nw0_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MODULE_DEVICE_TABLE(of, boe_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static struct mipi_dsi_driver boe_panel_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .name = "panel-boe-tv101wum-nl6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .of_match_table = boe_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .probe = boe_panel_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .remove = boe_panel_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .shutdown = boe_panel_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) module_mipi_dsi_driver(boe_panel_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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