^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Ingenic JZ47xx IPU - Register definitions and private API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define JZ_REG_IPU_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define JZ_REG_IPU_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define JZ_REG_IPU_D_FMT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JZ_REG_IPU_Y_ADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define JZ_REG_IPU_U_ADDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define JZ_REG_IPU_V_ADDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define JZ_REG_IPU_IN_GS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define JZ_REG_IPU_Y_STRIDE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define JZ_REG_IPU_UV_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define JZ_REG_IPU_OUT_ADDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ_REG_IPU_OUT_GS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ_REG_IPU_OUT_STRIDE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ_REG_IPU_RSZ_COEF_INDEX 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ_REG_IPU_CSC_C0_COEF 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ_REG_IPU_CSC_C1_COEF 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ_REG_IPU_CSC_C2_COEF 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ_REG_IPU_CSC_C3_COEF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ_REG_IPU_CSC_C4_COEF 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ_REG_IPU_HRSZ_COEF_LUT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ_REG_IPU_VRSZ_COEF_LUT 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ_REG_IPU_CSC_OFFSET 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ_REG_IPU_Y_PHY_T_ADDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ_REG_IPU_U_PHY_T_ADDR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ_REG_IPU_V_PHY_T_ADDR 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ_REG_IPU_OUT_PHY_T_ADDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JZ_IPU_CTRL_ADDR_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JZ_IPU_CTRL_ZOOM_SEL BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JZ_IPU_CTRL_DFIX_SEL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JZ_IPU_CTRL_LCDC_SEL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JZ_IPU_CTRL_SPKG_SEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JZ_IPU_CTRL_VSCALE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JZ_IPU_CTRL_HSCALE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define JZ_IPU_CTRL_STOP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JZ_IPU_CTRL_RST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JZ_IPU_CTRL_FM_IRQ_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define JZ_IPU_CTRL_CSC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JZ_IPU_CTRL_VRSZ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JZ_IPU_CTRL_HRSZ_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JZ_IPU_CTRL_RUN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JZ_IPU_CTRL_CHIP_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JZ_IPU_STATUS_OUT_END BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JZ_IPU_IN_GS_H_LSB 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JZ_IPU_IN_GS_W_LSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define JZ_IPU_OUT_GS_H_LSB 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define JZ_IPU_OUT_GS_W_LSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define JZ_IPU_Y_STRIDE_Y_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JZ_IPU_UV_STRIDE_U_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define JZ_IPU_UV_STRIDE_V_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define JZ_IPU_D_FMT_IN_FMT_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define JZ_IPU_D_FMT_IN_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JZ_IPU_D_FMT_IN_FMT_YUV420 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JZ_IPU_D_FMT_IN_FMT_YUV422 (0x1 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JZ_IPU_D_FMT_IN_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define JZ_IPU_D_FMT_IN_FMT_YUV444 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JZ_IPU_D_FMT_IN_FMT_RGB565 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define JZ_IPU_D_FMT_YUV_FMT_LSB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JZ_IPU_D_FMT_YUV_Y1UY0V (0x0 << JZ_IPU_D_FMT_YUV_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define JZ_IPU_D_FMT_YUV_Y1VY0U (0x1 << JZ_IPU_D_FMT_YUV_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define JZ_IPU_D_FMT_YUV_UY1VY0 (0x2 << JZ_IPU_D_FMT_YUV_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define JZ_IPU_D_FMT_YUV_VY1UY0 (0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define JZ_IPU_D_FMT_IN_FMT_YUV411 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define JZ_IPU_D_FMT_OUT_FMT_LSB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define JZ_IPU_D_FMT_OUT_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_OUT_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define JZ_IPU_D_FMT_OUT_FMT_RGB565 (0x1 << JZ_IPU_D_FMT_OUT_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define JZ_IPU_D_FMT_OUT_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_OUT_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define JZ_IPU_D_FMT_OUT_FMT_YUV422 (0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define JZ_IPU_D_FMT_OUT_FMT_RGBAAA (0x4 << JZ_IPU_D_FMT_OUT_FMT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB (0x0 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG (0x1 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR (0x2 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB (0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG (0x4 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR (0x5 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define JZ4725B_IPU_RSZ_LUT_COEF_LSB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define JZ4725B_IPU_RSZ_LUT_COEF_MASK 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define JZ4725B_IPU_RSZ_LUT_IN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define JZ4725B_IPU_RSZ_LUT_OUT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define JZ4760_IPU_RSZ_COEF20_LSB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define JZ4760_IPU_RSZ_COEF31_LSB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define JZ4760_IPU_RSZ_COEF_MASK 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define JZ4760_IPU_RSZ_OFFSET_LSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define JZ4760_IPU_RSZ_OFFSET_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define JZ_IPU_CSC_OFFSET_CHROMA_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define JZ_IPU_CSC_OFFSET_LUMA_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags