^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Ingenic JZ47xx IPU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2020, Daniel Silsby <dansilsby@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ingenic-drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "ingenic-ipu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_fb_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_plane.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_plane_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <drm/drm_vblank.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ingenic_ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const u32 *formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) size_t num_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bool has_bicubic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool manual_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int sharpness, bool downscale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int weight, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ingenic_ipu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct drm_plane plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct device *dev, *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct soc_info *soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool clk_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int num_w, num_h, denom_w, denom_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dma_addr_t addr_y, addr_u, addr_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct drm_property *sharpness_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int sharpness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Signed 15.16 fixed-point math (for bicubic scaling coefficients) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2F(i) ((s32)(i) * 65536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define F2I(f) ((f) / 65536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FMUL(fa, fb) ((s32)(((s64)(fa) * (s64)(fb)) / 65536))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SHARPNESS_INCR (I2F(-1) / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline struct ingenic_ipu *plane_to_ingenic_ipu(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return container_of(plane, struct ingenic_ipu, plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Apply conventional cubic convolution kernel. Both parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * and return value are 15.16 signed fixed-point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @f_a: Sharpness factor, typically in range [-4.0, -0.25].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * A larger magnitude increases perceived sharpness, but going past
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * -2.0 might cause ringing artifacts to outweigh any improvement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Nice values on a 320x240 LCD are between -0.75 and -2.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @f_x: Absolute distance in pixels from 'pixel 0' sample position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * along horizontal (or vertical) source axis. Range is [0, +2.0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * returns: Weight of this pixel within 4-pixel sample group. Range is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * [-2.0, +2.0]. For moderate (i.e. > -3.0) sharpness factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * range is within [-1.0, +1.0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline s32 cubic_conv(s32 f_a, s32 f_x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const s32 f_1 = I2F(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const s32 f_2 = I2F(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const s32 f_3 = I2F(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const s32 f_4 = I2F(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const s32 f_x2 = FMUL(f_x, f_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const s32 f_x3 = FMUL(f_x, f_x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (f_x <= f_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return FMUL((f_a + f_2), f_x3) - FMUL((f_a + f_3), f_x2) + f_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else if (f_x <= f_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return FMUL(f_a, (f_x3 - 5 * f_x2 + 8 * f_x - f_4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * On entry, "weight" is a coefficient suitable for bilinear mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * which is converted to a set of four suitable for bicubic mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * "weight 512" means all of pixel 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * "weight 256" means half of pixel 0 and half of pixel 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * "weight 0" means all of pixel 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * "offset" is increment to next source pixel sample location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int sharpness, bool downscale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int weight, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s32 w0, w1, w2, w3; /* Pixel weights at X (or Y) offsets -1,0,1,2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) weight = clamp_val(weight, 0, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (sharpness < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * When sharpness setting is 0, emulate nearest-neighbor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * When sharpness setting is 1, emulate bilinear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (sharpness == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) weight = weight >= 256 ? 512 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) w0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) w1 = weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) w2 = 512 - weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) w3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const s32 f_a = SHARPNESS_INCR * sharpness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const s32 f_h = I2F(1) / 2; /* Round up 0.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Note that always rounding towards +infinity here is intended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * The resulting coefficients match a round-to-nearest-int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * double floating-point implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) weight = 512 - weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) w0 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 + weight) / 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) w1 = F2I(f_h + 512 * cubic_conv(f_a, I2F(0 + weight) / 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) w2 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 - weight) / 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) w3 = F2I(f_h + 512 * cubic_conv(f_a, I2F(1024 - weight) / 512));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) w0 = clamp_val(w0, -1024, 1023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) w1 = clamp_val(w1, -1024, 1023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) w2 = clamp_val(w2, -1024, 1023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) w3 = clamp_val(w3, -1024, 1023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = ((w1 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ((w0 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_write(ipu->map, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = ((w3 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ((w2 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ((offset & JZ4760_IPU_RSZ_OFFSET_MASK) << JZ4760_IPU_RSZ_OFFSET_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) regmap_write(ipu->map, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int sharpness, bool downscale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int weight, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 val = JZ4725B_IPU_RSZ_LUT_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) weight = clamp_val(weight, 0, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (sharpness == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) weight = weight >= 256 ? 512 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val |= (weight & JZ4725B_IPU_RSZ_LUT_COEF_MASK) << JZ4725B_IPU_RSZ_LUT_COEF_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (downscale || !!offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val |= JZ4725B_IPU_RSZ_LUT_IN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regmap_write(ipu->map, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (downscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 1; i < offset; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int i, offset, weight, weight_num = denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) weight_num = num + (weight_num - num) % (num * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) weight = 512 - 512 * (weight_num - num) / (num * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) weight_num += denom * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) offset = (weight_num - num) / (num * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) true, weight, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Force nearest-neighbor scaling and use simple math when upscaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * by an integer ratio. It looks better, and fixes a few problem cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int i, offset, weight, weight_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) weight = 512 - 512 * weight_num / num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) weight_num += denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) offset = weight_num >= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) weight_num -= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) false, weight, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int num, unsigned int denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Begin programming the LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) regmap_write(ipu->map, reg, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (denom > num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else if (denom == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int reduce_fraction(unsigned int *num, unsigned int *denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long d = gcd(*num, *denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* The scaling table has only 31 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (*num > 31 * d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *num /= d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *denom /= d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline bool osd_changed(struct drm_plane_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct drm_plane_state *oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return state->src_x != oldstate->src_x ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) state->src_y != oldstate->src_y ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) state->src_w != oldstate->src_w ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) state->src_h != oldstate->src_h ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) state->crtc_x != oldstate->crtc_x ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) state->crtc_y != oldstate->crtc_y ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) state->crtc_w != oldstate->crtc_w ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) state->crtc_h != oldstate->crtc_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct drm_plane_state *oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct drm_plane_state *state = plane->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const struct drm_format_info *finfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 ctrl, stride = 0, coef_index = 0, format = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bool needs_modeset, upscaling_w, upscaling_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!state || !state->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) finfo = drm_format_info(state->fb->format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!ipu->clk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = clk_enable(ipu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(ipu->dev, "Unable to enable clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ipu->clk_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Reset all the registers if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) needs_modeset = drm_atomic_crtc_needs_modeset(state->crtc->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (needs_modeset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Enable the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) JZ_IPU_CTRL_CHIP_EN | JZ_IPU_CTRL_LCDC_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* New addresses will be committed in vblank handler... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ipu->addr_y = drm_fb_cma_get_gem_addr(state->fb, state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (finfo->num_planes > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ipu->addr_u = drm_fb_cma_get_gem_addr(state->fb, state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (finfo->num_planes > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ipu->addr_v = drm_fb_cma_get_gem_addr(state->fb, state, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!needs_modeset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Or right here if we're doing a full modeset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (finfo->num_planes == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Set the input height/width/strides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (finfo->num_planes > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) stride = ((state->src_w >> 16) * finfo->cpp[2] / finfo->hsub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) << JZ_IPU_UV_STRIDE_V_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (finfo->num_planes > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) stride |= ((state->src_w >> 16) * finfo->cpp[1] / finfo->hsub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) << JZ_IPU_UV_STRIDE_U_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) stride = ((state->src_w >> 16) * finfo->cpp[0]) << JZ_IPU_Y_STRIDE_Y_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regmap_write(ipu->map, JZ_REG_IPU_IN_GS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (stride << JZ_IPU_IN_GS_W_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ((state->src_h >> 16) << JZ_IPU_IN_GS_H_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) switch (finfo->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case DRM_FORMAT_XRGB1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case DRM_FORMAT_XBGR1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) format = JZ_IPU_D_FMT_IN_FMT_RGB555 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case DRM_FORMAT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case DRM_FORMAT_BGR565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) format = JZ_IPU_D_FMT_IN_FMT_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case DRM_FORMAT_XRGB8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case DRM_FORMAT_XYUV8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) JZ_IPU_D_FMT_RGB_OUT_OFT_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case DRM_FORMAT_XBGR8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) format = JZ_IPU_D_FMT_IN_FMT_RGB888 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) JZ_IPU_D_FMT_RGB_OUT_OFT_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case DRM_FORMAT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) JZ_IPU_D_FMT_YUV_VY1UY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case DRM_FORMAT_YVYU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) JZ_IPU_D_FMT_YUV_UY1VY0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case DRM_FORMAT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) JZ_IPU_D_FMT_YUV_Y1VY0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case DRM_FORMAT_VYUY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) format = JZ_IPU_D_FMT_IN_FMT_YUV422 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) JZ_IPU_D_FMT_YUV_Y1UY0V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case DRM_FORMAT_YUV411:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) format = JZ_IPU_D_FMT_IN_FMT_YUV411;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case DRM_FORMAT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) format = JZ_IPU_D_FMT_IN_FMT_YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case DRM_FORMAT_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) format = JZ_IPU_D_FMT_IN_FMT_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case DRM_FORMAT_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) format = JZ_IPU_D_FMT_IN_FMT_YUV444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) WARN_ONCE(1, "Unsupported format");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Fix output to RGB888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) format |= JZ_IPU_D_FMT_OUT_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Set pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Set the output height/width/stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) regmap_write(ipu->map, JZ_REG_IPU_OUT_GS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ((state->crtc_w * 4) << JZ_IPU_OUT_GS_W_LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) | state->crtc_h << JZ_IPU_OUT_GS_H_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, state->crtc_w * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (finfo->is_yuv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Offsets for Chroma/Luma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * y = source Y - LUMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * u = source Cb - CHROMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * v = source Cr - CHROMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 128 << JZ_IPU_CSC_OFFSET_CHROMA_LSB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0 << JZ_IPU_CSC_OFFSET_LUMA_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * YUV422 to RGB conversion table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * R = C0 / 0x400 * y + C1 / 0x400 * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * G = C0 / 0x400 * y - C2 / 0x400 * u - C3 / 0x400 * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * B = C0 / 0x400 * y + C4 / 0x400 * u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Must set ZOOM_SEL before programming bicubic LUTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * If the IPU supports bicubic, we enable it unconditionally, since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * can do anything bilinear can and more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ipu->soc_info->has_bicubic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ctrl |= JZ_IPU_CTRL_ZOOM_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) upscaling_w = ipu->num_w > ipu->denom_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (upscaling_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ctrl |= JZ_IPU_CTRL_HSCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ipu->num_w != 1 || ipu->denom_w != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!ipu->soc_info->has_bicubic && !upscaling_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) coef_index |= (ipu->denom_w - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) coef_index |= (ipu->num_w - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ctrl |= JZ_IPU_CTRL_HRSZ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) upscaling_h = ipu->num_h > ipu->denom_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (upscaling_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ctrl |= JZ_IPU_CTRL_VSCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ipu->num_h != 1 || ipu->denom_h != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!ipu->soc_info->has_bicubic && !upscaling_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) coef_index |= ipu->denom_h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) coef_index |= ipu->num_h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ctrl |= JZ_IPU_CTRL_VRSZ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) JZ_IPU_CTRL_HRSZ_EN | JZ_IPU_CTRL_VRSZ_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) JZ_IPU_CTRL_HSCALE | JZ_IPU_CTRL_VSCALE, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Set the LUT index register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ipu->num_w != 1 || ipu->denom_w != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ipu->num_w, ipu->denom_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ipu->num_h != 1 || ipu->denom_h != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ipu->num_h, ipu->denom_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Clear STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Start IPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) JZ_IPU_CTRL_RUN | JZ_IPU_CTRL_FM_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) state->src_w >> 16, state->src_h >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) state->crtc_w, state->crtc_h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ipu->num_w, ipu->denom_w, ipu->num_h, ipu->denom_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int num_w, denom_w, num_h, denom_h, xres, yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct drm_crtc *crtc = state->crtc ?: plane->state->crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct drm_crtc_state *crtc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (WARN_ON(!crtc_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Request a full modeset if we are enabling or disabling the IPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!plane->state->crtc ^ !state->crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!state->crtc ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) !crtc_state->mode.hdisplay || !crtc_state->mode.vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Plane must be fully visible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (state->crtc_x < 0 || state->crtc_y < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) state->crtc_x + state->crtc_w > crtc_state->mode.hdisplay ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) state->crtc_y + state->crtc_h > crtc_state->mode.vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Minimum size is 4x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if ((state->src_w >> 16) < 4 || (state->src_h >> 16) < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Input and output lines must have an even number of pixels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (((state->src_w >> 16) & 1) || (state->crtc_w & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!osd_changed(state, plane->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) xres = state->src_w >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) yres = state->src_h >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Adjust the coefficients until we find a valid configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (denom_w = xres, num_w = state->crtc_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) num_w <= crtc_state->mode.hdisplay; num_w++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!reduce_fraction(&num_w, &denom_w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (num_w > crtc_state->mode.hdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) for (denom_h = yres, num_h = state->crtc_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) num_h <= crtc_state->mode.vdisplay; num_h++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!reduce_fraction(&num_h, &denom_h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (num_h > crtc_state->mode.vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ipu->num_w = num_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ipu->num_h = num_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ipu->denom_w = denom_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ipu->denom_h = denom_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void ingenic_ipu_plane_atomic_disable(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ingenic_drm_plane_disable(ipu->master, plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ipu->clk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_disable(ipu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ipu->clk_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct drm_plane_helper_funcs ingenic_ipu_plane_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .atomic_update = ingenic_ipu_plane_atomic_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .atomic_check = ingenic_ipu_plane_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .atomic_disable = ingenic_ipu_plane_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .prepare_fb = drm_gem_fb_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ingenic_ipu_plane_atomic_get_property(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) const struct drm_plane_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct drm_property *property, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (property != ipu->sharpness_prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *val = ipu->sharpness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ingenic_ipu_plane_atomic_set_property(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct drm_plane_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct drm_property *property, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct drm_crtc_state *crtc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (property != ipu->sharpness_prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ipu->sharpness = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (state->crtc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (WARN_ON(!crtc_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct drm_plane_funcs ingenic_ipu_plane_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .update_plane = drm_atomic_helper_update_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .disable_plane = drm_atomic_helper_disable_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .reset = drm_atomic_helper_plane_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .destroy = drm_plane_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .atomic_get_property = ingenic_ipu_plane_atomic_get_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .atomic_set_property = ingenic_ipu_plane_atomic_set_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static irqreturn_t ingenic_ipu_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct ingenic_ipu *ipu = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned int dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* dummy read allows CPU to reconfigure IPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ipu->soc_info->manual_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* ACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Set previously cached addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Run IPU for the new frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ipu->soc_info->manual_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) drm_crtc_handle_vblank(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const struct regmap_config ingenic_ipu_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .max_register = JZ_REG_IPU_OUT_PHY_T_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int ingenic_ipu_bind(struct device *dev, struct device *master, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const struct soc_info *soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct drm_device *drm = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct ingenic_ipu *ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int sharpness_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) soc_info = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!soc_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_err(dev, "Missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ipu->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ipu->drm = drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ipu->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ipu->soc_info = soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(dev, "Failed to get memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (IS_ERR(ipu->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(dev, "Failed to create regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return PTR_ERR(ipu->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ipu->clk = devm_clk_get(dev, "ipu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (IS_ERR(ipu->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(dev, "Failed to get pixel clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return PTR_ERR(ipu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) err = devm_request_irq(dev, irq, ingenic_ipu_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_name(dev), ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(dev, "Unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) plane = &ipu->plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_set_drvdata(dev, plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) drm_plane_helper_add(plane, &ingenic_ipu_plane_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err = drm_universal_plane_init(drm, plane, 1, &ingenic_ipu_plane_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) soc_info->formats, soc_info->num_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(dev, "Failed to init plane: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Sharpness settings range is [0,32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * 0 : nearest-neighbor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * 1 : bilinear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * 2 .. 32 : bicubic (translated to sharpness factor -0.25 .. -4.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sharpness_max = soc_info->has_bicubic ? 32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 0, sharpness_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!ipu->sharpness_prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(dev, "Unable to create sharpness property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Default sharpness factor: -0.125 * 8 = -1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ipu->sharpness = soc_info->has_bicubic ? 8 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) drm_object_attach_property(&plane->base, ipu->sharpness_prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ipu->sharpness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) err = clk_prepare(ipu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(dev, "Unable to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void ingenic_ipu_unbind(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct device *master, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct ingenic_ipu *ipu = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) clk_unprepare(ipu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct component_ops ingenic_ipu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .bind = ingenic_ipu_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .unbind = ingenic_ipu_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int ingenic_ipu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return component_add(&pdev->dev, &ingenic_ipu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int ingenic_ipu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) component_del(&pdev->dev, &ingenic_ipu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const u32 jz4725b_ipu_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * While officially supported, packed YUV 4:2:2 formats can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * random hardware crashes on JZ4725B under certain circumstances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * It seems to happen with some specific resize ratios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Until a proper workaround or fix is found, disable these formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DRM_FORMAT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) DRM_FORMAT_YVYU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DRM_FORMAT_UYVY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) DRM_FORMAT_VYUY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) DRM_FORMAT_YUV411,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) DRM_FORMAT_YUV420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DRM_FORMAT_YUV422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) DRM_FORMAT_YUV444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct soc_info jz4725b_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .formats = jz4725b_ipu_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .num_formats = ARRAY_SIZE(jz4725b_ipu_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .has_bicubic = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .manual_restart = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .set_coefs = jz4725b_set_coefs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const u32 jz4760_ipu_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) DRM_FORMAT_XRGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) DRM_FORMAT_XBGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) DRM_FORMAT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) DRM_FORMAT_BGR565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DRM_FORMAT_XBGR8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DRM_FORMAT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DRM_FORMAT_YVYU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DRM_FORMAT_UYVY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) DRM_FORMAT_VYUY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) DRM_FORMAT_YUV411,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) DRM_FORMAT_YUV420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DRM_FORMAT_YUV422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DRM_FORMAT_YUV444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DRM_FORMAT_XYUV8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct soc_info jz4760_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .formats = jz4760_ipu_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .num_formats = ARRAY_SIZE(jz4760_ipu_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .has_bicubic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .manual_restart = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .set_coefs = jz4760_set_coefs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const struct of_device_id ingenic_ipu_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MODULE_DEVICE_TABLE(of, ingenic_ipu_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static struct platform_driver ingenic_ipu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "ingenic-ipu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .of_match_table = ingenic_ipu_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .probe = ingenic_ipu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .remove = ingenic_ipu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct platform_driver *ingenic_ipu_driver_ptr = &ingenic_ipu_driver;
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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